JPH08186183A - Non-volatile semiconductor memory device and its manufacture - Google Patents

Abstract

PURPOSE: To provide a non-volatile semiconductor memory device which can effectively and simultaneously prevent the punch through between memory cell transistors and that between wiring layers consisted of an impurity diffusion layer and further can be miniaturized and its manufacturing method. CONSTITUTION: A non-volatile semiconductor memory device is provided with a semiconductor substrate 20 where a plurality of stripe-shaped trenches 26 are formed at a specific space, impurity diffusion layers 22a, 22b, and 22c which are formed nearly in parallel with the trench 26 on the surface of the semiconductor substrate between the trenches 26, and a control gate 34 which is extended in a direction nearly crossing the impurity diffusion layer through an insulation layer 24 on the impurity diffusion layer. Memory cell transistors 40a and 40b are formed at a part where the control gate 34 enters the trench 26. The memory cell transistors have a floating gate 30a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly, to effectively prevent punch-through between memory cell transistors and punch-through between wiring layers composed of impurity diffusion layers at the same time. The present invention relates to a nonvolatile semiconductor memory device to be obtained.

[0002]

2. Description of the Related Art In recent years, with the spread and development of portable information terminal equipment, the need for a large-capacity flash memory as an external storage device is increasing. By the way, in order to reduce the memory cell size of a flash memory, a method of using an impurity diffusion layer to a substrate as a wiring of a source / drain region has been proposed. 5 and 6 show a perspective sectional view and a plan view of a main portion of a nonvolatile semiconductor memory device adopting this method, respectively.

As shown in FIGS. 5 and 6, in this non-volatile semiconductor memory device, N-type impurity diffusion layers 4 are formed in stripes on the surface of a semiconductor substrate 2, and the impurity diffusion layers 4 are used in the memory device. Used as a bit line or source line. A silicon oxide film 6 is formed on the impurity diffusion layer 4 in the same stripe shape. A gate insulating film 8 is formed on the surface of the semiconductor substrate 2 located between the silicon oxide films 6, and floating gates 10 are formed in a matrix thereon.

Control gates 14 are formed on the floating gate 10 via an intermediate insulating film 12 in stripes at predetermined intervals so as to be substantially orthogonal to the longitudinal direction of the impurity diffusion layer 4. On the surface of the semiconductor substrate 2 directly below the gate insulating film 8 located between the control gates 14, an isolation impurity diffusion layer 13 for isolating the wiring between the diffusion layers 4 and 4 is formed. The conductivity type of the separation impurity diffusion layer 13 is P type. The pattern on the plane side of the separation impurity diffusion layer 13 is the hatched pattern shown in FIG.

The channel of each memory cell transistor is
For each floating gate 10, it is formed on the surface of the semiconductor substrate 2 directly below the gate insulating film 8 located directly below it. In the nonvolatile semiconductor memory device having such a structure,
It is not necessary to form a bit line contact in the memory cell, and the memory cell area is about 30 as compared with a non-volatile semiconductor memory device having a normal floating gate.
It can be reduced by more than%.

[0006]

However, in such a recently proposed non-volatile semiconductor memory device, the wiring isolation between the impurity diffusion layers 4 and 4 serving as the bit line or the source line is not provided by the field oxide film. , Only the separation impurity diffusion layer 13 formed by the ion implantation method. For this reason, it becomes easy to reduce the cell area, while
If the design rule is miniaturized, there is a problem that punch through occurs between the impurity diffusion layers 4 and 4.

In particular, in the process of growing the silicon oxide film 6 on the impurity diffusion layer 4 by the thermal oxidation method, the impurities of the impurity diffusion layer 4 are accelerated and diffused, so that the channel direction of the memory cell transistor and the substrate direction. Spread to. Therefore, not only the above problem is further increased, but also punch-through may occur between memory cell transistors.

The present invention has been made in view of the above situation, and effectively prevents punch-through between memory cell transistors and punch-through between wiring layers formed of impurity diffusion layers at the same time, and further miniaturization. An object of the present invention is to provide a non-volatile semiconductor memory device that can be manufactured and a manufacturing method thereof.

[0009]

In order to achieve the above-mentioned object, a nonvolatile semiconductor memory device according to the present invention is sandwiched between a semiconductor substrate having a plurality of stripe-shaped trenches formed at predetermined intervals and the trenches. An impurity diffusion layer formed substantially parallel to the trench on the surface of the semiconductor substrate, and a control gate extending on the impurity diffusion layer in a direction substantially orthogonal to the impurity diffusion layer via an insulating layer. A memory cell transistor is formed in a portion where the control gate enters the trench.

It is preferable that a floating gate is formed inside the trench via a gate insulating film, and the control gate is formed on the floating gate via an intermediate insulating film. A memory insulating film is formed on the inner peripheral surface of the trench, and a control gate may be formed on the memory insulating film.

The memory insulating film may be formed of a film capable of storing and releasing charges. An example of such a film is an insulating film containing nitrogen. Specifically, an ONO film (SiO ₂ / SiN / SiO ₂ ), O
The N film (SiN / SiO ₂ ), SiN film and the like can be exemplified.

The memory insulating film may be made of a ferroelectric thin film. It is preferable that a region having the same conductivity type as the impurity diffusion layer and a high impurity concentration is formed on one side wall of the trench below the trench sidewall of the impurity diffusion layer.

The impurity diffusion layer separated from the trench is formed so that the impurity diffusion layer portion facing one sidewall of the trench has a higher impurity concentration than the impurity diffusion layer portion facing the other sidewall. It may be composed of a low-concentration impurity diffusion layer portion extending in the direction and a high-concentration impurity diffusion layer portion adjacent to and parallel to the low-concentration impurity diffusion layer portion.

It is preferable that an impurity diffusion layer for separating wirings having a conductivity type opposite to that of the impurity diffusion layer is formed at the bottom of the trench where the control gate is not formed. The conductivity type of the impurity diffusion layer is preferably N type.

A method of manufacturing a nonvolatile semiconductor memory device according to the present invention comprises a step of forming an impurity diffusion layer on the entire surface of a memory cell region of a semiconductor substrate, and then the impurity diffusion layer in the memory cell region of the semiconductor substrate. At the depth to separate
Forming a plurality of stripe-shaped trenches at predetermined intervals; forming a control gate on the impurity diffusion layer through an insulating layer in a direction substantially orthogonal to the impurity diffusion layer, the control gate forming the trench; And a step of forming a memory cell transistor in a portion which enters inside.

Using the control gate as a mask,
It is preferable to further include a step of forming an impurity diffusion layer for inter-wiring isolation in a self-alignment with the control gate and the trench at the bottom of the trench other than the portion where the memory cell transistor is formed.

It is preferable that a floating gate is formed inside the trench via a gate insulating film, and the control gate is formed on the floating gate via an intermediate insulating film. It is preferable that a region having the same conductivity type as the impurity diffusion layer and a high impurity concentration is formed on one side wall of the trench below the trench side wall of the impurity diffusion layer by an oblique ion implantation method.

The impurity diffusion layer separated from the trench is formed so that the impurity diffusion layer portion facing one side wall of the trench has a higher impurity concentration than the impurity diffusion layer portion facing the other side wall. It may be composed of a low-concentration impurity diffusion layer portion extending in the direction and a high-concentration impurity diffusion layer portion adjacent to and parallel to the low-concentration impurity diffusion layer portion.

[0019]

In the nonvolatile semiconductor memory device according to the present invention,
Since the stripe-shaped impurity diffusion layer formed on the surface of the semiconductor substrate is used as a bit line or a source line, a contact for a bit line contact is not required for each memory cell transistor, which reduces the size of the memory cell. Is realized. Further, according to the present invention, since the memory cell transistor is formed in the trench, the memory cell can be easily reduced in this respect as well.

Further, in the nonvolatile semiconductor memory device according to the present invention, since the impurity diffusion layers to be the bit lines or the source lines are separated by the trenches, the wiring separation between them is ensured, and the diffusion layers are diffused. It is possible to reliably prevent punch through. Furthermore, punch through between memory cell transistors can be effectively prevented.

If an impurity diffusion layer for separating wirings of a conductivity type opposite to that of the impurity diffusion layer is formed at the bottom of the trench where the control gate is not formed, punch-through prevention between diffusion layers and punch-through between memory cell transistors are performed. Preventive action is improved. If a region having the same conductivity type as the impurity diffusion layer and a high impurity concentration is formed on one side wall of the trench below the side wall of the trench of the impurity diffusion layer, it becomes a write target when data is written by the virtual ground method. A high electric field can be selectively generated only in the vicinity of the drain of the memory cell transistor. Therefore,
Data can be written to a target memory cell transistor without erroneously writing to an adjacent memory cell transistor.

Further, the same effect is obtained by forming the impurity diffusion layer separated by the trench in a low-concentration impurity diffusion layer portion extending in the trench direction and a high-concentration impurity layer formed adjacent to and parallel to the low-concentration impurity diffusion layer portion. It can also be obtained by configuring with the impurity diffusion layer portion. With the method for manufacturing a nonvolatile semiconductor memory device according to the present invention, the nonvolatile semiconductor memory device having the above structure can be manufactured by a relatively simple manufacturing process.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A non-volatile semiconductor memory device according to the present invention and a method of manufacturing the same will now be described with reference to the embodiments shown in the drawings
The details will be described. In manufacturing the nonvolatile semiconductor memory device according to an embodiment of the present invention shown in the first embodiment Figure 1 and 2, first, as shown in FIG. 1 (A), a semiconductor substrate 20. A single crystal silicon substrate is used as the semiconductor substrate 20. Semiconductor substrate 20
The conductivity type may be P-type or N-type. However, when the memory cell transistor is composed of an N-type MOS transistor, a P-type substrate or an N-type substrate with a P well formed so that the substrate surface of the memory cell region is P-type is used.

An N-type impurity such as As is introduced into the entire surface of the memory cell region of the semiconductor substrate 20 by an ion implantation method to form an N-type impurity diffusion layer 22. An insulating film 24 such as a silicon oxide film is formed on the surface of the substrate by thermal oxidation, CVD or the like on the surface of the impurity diffusion layer 22. The thickness of the insulating film 24 is not particularly limited, but is, for example, 50 to
It is about 200 nm.

Next, the insulating film 24 and the impurity diffusion layer 22.
The trenches 26 are formed in stripes at predetermined intervals on the surface of the semiconductor substrate 20 on which the impurity diffusion layers 22 are formed.
The stripe-shaped impurity diffusion layers 22a, 22b, 22
c ... The groove width and depth of the trench 26 are
Although not particularly limited, for example, the groove width is 200 to 500.
and the groove depth is at least the impurity diffusion layer 2
2 is a depth that can be separated, for example, 200 to 500 n
m. Separated impurity diffusion layers 22a, 22b, 2
2c becomes a bit line or a source line of the memory device.

Next, as shown in FIG. 1C, gate oxidation is performed after heat treatment to form a gate insulating film 28 on the inner peripheral surface of the trench 26. The thickness of the gate insulating film 28 is not particularly limited, but is about 10 nm, for example. Next, a first conductive layer 30 to be a floating gate is formed on the gate insulating film 28. This first conductive layer 3
0 is composed of, for example, polysilicon into which phosphorus is introduced, and its film thickness is, for example, 50 to 200 nm. The first conductive layer 30 is formed by CVD or the like, and is etched in the trench direction after the film is formed.

Next, as shown in FIG. 1D, after forming an intermediate insulating film 32 on the entire surface, a second conductive layer to be the control gate 34 is formed. The intermediate insulating film 32 is composed of, for example, an ONO film (SiO ₂ / SiN / SiO ₂ ) or a two-layer film (SiN / SiO ₂ ) without a lower oxide film. To form the ONO film, the surface of the first conductive layer 30 is thermally oxidized to form an oxide film of about 14 nm or less, and a silicon nitride film of about 11 nm or less is formed on the thermal oxide film by the CVD method. The film is formed with
An oxide film of about m or less is formed. Through such steps, an ONO film having a three-layer structure can be formed. This ONO film has a low leak current and excellent film thickness controllability.
The film thickness of this ONO film is 22n in terms of silicon oxide film.
It is about m or less.

The second conductive layer serving as the control gate 34 is not particularly limited, but is formed of, for example, a polycide film which is a laminated film of a polysilicon film and a silicide film. The second conductive layer is etched by RIE (reactive ion etching) or the like at predetermined intervals in a direction substantially perpendicular to the longitudinal direction of the trench 26, and the control gate 34 is formed.
To form. Subsequent to the etching, the intermediate insulating film 32 and the first conductive layer 30 are also etched with the pattern of the control gate 34 to form the floating gate 30a in the trench 26. The control gate 34 also serves as a word line of the memory device.

Next, as shown in FIG. 1E, ion implantation is performed using the control gate 34 as a mask, and the conductivity type opposite to that of the impurity diffusion layer 22 is formed at the bottom of the trench 26 where the control gate is not formed. An impurity diffusion layer 38 for separating wirings is formed. As an impurity used for ion implantation, for example, boron which is a P-type impurity is used. The conditions for ion implantation are not particularly limited, but the implantation energy is, for example, 20 to 50 KeV, and the dose amount is about 1 × 10 ^{12 to} 5 × 10 ¹² / cm ² .

The inter-wiring isolation impurity diffusion layer 38 thus formed reinforces the wiring isolation between the diffusion layers 22a, 22b and 22c and the element isolation of the memory cell in the trench 26 direction. The pattern of the inter-wiring isolation impurity diffusion layer 38 is shown by the hatched portion in FIG.

Although not shown in FIGS. 1 and 2, a shunt metal wiring layer for reducing the resistance of the impurity diffusion layers 22a, 22b, 22c is formed on the control gate 34 via an interlayer insulating film. However, it is preferable that the metal wiring layer and the diffusion layer are connected through a contact for each predetermined cell in parallel with the diffusion layer.

In the nonvolatile semiconductor memory device according to this embodiment manufactured by the above manufacturing process, the memory cell transistors 40a and 40b are provided inside the trench 26 located at the intersection of the control gate 34 and the trench 26.
... is formed. In the present embodiment, the wiring formed of the impurity diffusion layers 22a, 22b, 22c which will be the bit line or the source line is separated by the trench 26 and has a large effective separation width. Further, the memory cell transistors 40a, 40b ... Are formed in the trench, and the trench 2 is formed in the direction perpendicular to the longitudinal direction of the trench 26.
6 has a large effective channel length. That is, by adopting the structure according to the present embodiment, it is possible to prevent punch through of the memory cell transistor and punch through between the wirings at the same time.

Second Embodiment In a non-volatile semiconductor memory device according to a second embodiment of the present invention, the same wiring (striped impurity diffusion layer) is connected to a bit line and a source line according to a memory cell to be accessed. The present invention relates to a non-volatile semiconductor memory device using a so-called “virtual ground method” that is properly used.

The non-volatile semiconductor memory device according to the present embodiment will be described below. The same members as those of the non-volatile semiconductor memory device according to the first embodiment are designated by the same reference numerals, and overlapping description will be omitted. , Partly omitted. In the virtual ground type non-volatile semiconductor memory device, for example, FIG.
When writing data to the memory cell transistor 40a shown in (B), the wiring formed of the impurity diffusion layers 22a is set to a high potential, and the wiring one layer formed of the impurity diffusion layers 22b and 22c is fixed to the ground potential. . On the other hand, when writing data to the memory cell transistor 40b, the wiring formed of the impurity diffusion layers 22b is set to a high potential, and the wiring formed of the impurity diffusion layers 22a and 22c is fixed to the ground potential.

Therefore, in this embodiment, by adopting the following structure and manufacturing method, erroneous writing to the adjacent memory cell transistor is prevented. That is, as shown in FIG. 3A, after forming the trench 26 on the surface of the semiconductor substrate 20, the direction orthogonal to the trench 26 and inclined from 45 to 60 degrees is obtained.
Ion implantation is performed. As a result, a high-concentration region 42 having the same conductivity type as the impurity diffusion layers 22a, 22b, 22c and a high impurity concentration is formed on one side wall of the trench 26 below the trench side walls of the impurity diffusion layers 22a, 22b, 22c. To do. The ion implantation conditions for forming the high concentration region are not particularly limited, but when phosphorus is used as the impurity, the implantation energy is 10 to 30 KeV, and 1
The condition is a dose amount of × 10 ^{15 to} 5 × 10 ¹⁵ / cm ² .

The subsequent steps are the same as in the case of the first embodiment shown in FIG. As a result of the process, a cross-sectional perspective view of a main part of the manufactured nonvolatile semiconductor memory device is shown in FIG.
Shown in As in the case shown in FIG. 1, the memory cell transistors 40a and 40b are formed in the trench 26 located at the intersection of the control gate 34 and the trench 26.

In the nonvolatile semiconductor memory device according to the present embodiment, the high concentration region 42 is selectively written only near the drain of the transistor to be written when writing data to the memory cell transistors 40a and 40b. A high electric field is generated and data can be written by hot carriers. Thereby, for example, when the diffusion layer 22b is set to a high potential and the diffusion layers 22a and 22c are set to the ground potential, data can be written in the memory cell transistor 40b without erroneous writing in the memory cell transistor 40a.

The other operation is the same as that of the first embodiment. Third Embodiment A non-volatile semiconductor memory device according to a third embodiment of the present invention also relates to a non-volatile semiconductor memory device using a so-called “virtual ground method”.

The non-volatile semiconductor memory device according to the present embodiment will be described below. The members common to those of the non-volatile semiconductor memory device according to the first embodiment are designated by the same reference numerals, and the overlapping description will be omitted. , Partly omitted. In the present embodiment, as shown in FIG. 4, the impurity diffusion layers 48a, 48b, 48c ... Separated by the trench 26 are respectively formed into a low-concentration impurity diffusion layer portion 44 extending in the trench direction and the low-concentration impurity diffusion layer. The high-concentration impurity diffusion layer portion 46 is formed adjacent to and parallel to the portion 44. These impurity diffusion layer portions 44 and 46 have the same conductivity type,
For example, it is of N type.

Diffusion layer portions 44 and 4 having different impurity concentrations
To form 6 in a stripe shape, for example, as shown in FIG.
In the step shown in, the ion implantation step is performed at least twice,
The diffusion layer portions 44 and 46 are formed in stripes. Then, a trench is formed. As a result of these, the trench 26
The impurity diffusion layer portion 46 facing one side wall has a higher impurity concentration than the impurity diffusion layer portion 44 facing the other side wall.

By adopting this structure, the electric field applied near the junction of the high-concentration impurity diffusion layer portion 46 is selectively strengthened. Therefore, the impurity diffusion layer 48b
Is set to a high potential and the diffusion layers 46a and 46c are set to the ground potential, data can be written in the memory cell transistor 40b without erroneous writing in the memory cell transistor 40a.

The other operations are similar to those of the first embodiment. The present invention is not limited to the above-mentioned embodiments, but can be modified in various ways within the scope of the present invention. For example, in the above embodiment, the memory cell transistor provided in the trench is of the double gate type having a floating gate, but the present invention is not limited to this, and for example, an ONO film, an ON film or an S film.
MONOS type having an iN film as a memory film, MONS
Type, MNS type single gate type memory cells may be used. Alternatively, it may be a memory cell transistor having a structure in which a ferroelectric thin film having hysteris in a polarized state is used as a memory film.

[0043]

As described above, according to the present invention, since the stripe-shaped impurity diffusion layer formed on the surface of the semiconductor substrate is used as the bit line or the source line, the memory cell transistor is formed. Each time, the contact for the bit line contact is not required, and the memory cell can be reduced. Further, according to the present invention, since the memory cell transistor is formed in the trench, the memory cell can be easily reduced in this respect as well.

Further, in the non-volatile semiconductor memory device according to the present invention, since the impurity diffusion layers which become the bit lines or the source lines are separated by the trenches, the wiring between them is surely secured and the diffusion layers It is possible to reliably prevent punch through. Furthermore, punch through between memory cell transistors can be effectively prevented.

By forming an impurity diffusion layer for separating wirings of a conductivity type opposite to that of the impurity diffusion layer at the bottom of the trench where the control gate is not formed, punch-through between diffusion layers and punch-through between memory cell transistors are prevented. The prevention effect is improved. If a region having the same conductivity type as the impurity diffusion layer and a high impurity concentration is formed on one side wall of the trench below the side wall of the trench of the impurity diffusion layer, it becomes a write target when data is written by the virtual ground method. A high electric field can be selectively generated only in the vicinity of the drain of the memory cell transistor. Therefore,
Data can be written to a target memory cell transistor without erroneously writing to an adjacent memory cell transistor.

Further, the same effect is obtained by forming the impurity diffusion layers separated by the trenches in the low-concentration impurity diffusion layer portions extending in the trench direction and the high-concentration impurities formed adjacent to and parallel to the low-concentration impurity diffusion layer portions. It can also be obtained by configuring with the impurity diffusion layer portion. With the method for manufacturing a nonvolatile semiconductor memory device according to the present invention, the nonvolatile semiconductor memory device having the above structure can be manufactured by a relatively simple manufacturing process.

[Brief description of drawings]

1A to 1E are cross-sectional perspective views of relevant parts showing a manufacturing process of a nonvolatile semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a plan view of a main part of a nonvolatile semiconductor memory device obtained by the manufacturing process shown in FIG.

3 (A) and 3 (B) are cross-sectional perspective views of relevant parts showing a manufacturing process of a nonvolatile semiconductor memory device according to another embodiment of the present invention.

FIG. 4 is a cross-sectional perspective view of essential parts of a nonvolatile semiconductor memory device according to still another embodiment of the present invention.

FIG. 5 is a cross-sectional perspective view of essential parts of a non-volatile semiconductor memory device according to a conventional example.

6 is a plan view of relevant parts of the conventional nonvolatile semiconductor memory device shown in FIG.

[Explanation of symbols]

20 ... Semiconductor substrate 22 ... Impurity diffusion layer 22a, 22b, 22c, 48a, 48b, 48c ...
Impurity diffusion layer 24 ... Insulating film 26 ... Trench 28 ... Gate insulating film 30 ... First conductive layer 30a ... Floating gate 32 ... Intermediate insulating film 34 ... Control gate (word line) 38 ... Wiring isolation impurity diffusion layers 40a, 40b Memory cell transistor 42 High concentration region 44 Low concentration impurity diffusion layer portion 46 High concentration impurity diffusion layer portion

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 27/115

Claims (14)

[Claims] 1. A semiconductor substrate having a plurality of stripe-shaped trenches formed at predetermined intervals, an impurity diffusion layer formed substantially parallel to the trench on a surface of the semiconductor substrate sandwiched between the trenches, and the impurity. A control gate extending on the diffusion layer in a direction substantially orthogonal to the impurity diffusion layer via an insulating layer, wherein a memory cell transistor is formed in a portion where the control gate enters the trench; Semiconductor memory device. 2. A floating gate is formed inside the trench via a gate insulating film, and the control gate is formed on the floating gate via an intermediate insulating film. 1. The nonvolatile semiconductor memory device according to 1. 3. The non-volatile semiconductor memory device according to claim 2, wherein an insulating film for memory is formed on an inner peripheral surface of the trench, and a control gate is laminated on the insulating film for memory. . 4. The non-volatile semiconductor memory device according to claim 3, wherein the memory insulating film is a film capable of storing and releasing charges. 5. The nonvolatile semiconductor memory device according to claim 3, wherein the memory insulating film is a ferroelectric thin film. 6. A region of the same conductivity type as the impurity diffusion layer and having a high impurity concentration is provided on only one side wall of the trench,
The non-volatile semiconductor memory device according to claim 1, wherein the non-volatile semiconductor memory device is formed below the sidewall of the trench of the impurity diffusion layer. 7. The impurity diffusion layer separated by the trench is formed so that an impurity diffusion layer portion facing one sidewall of the trench has a higher impurity concentration than an impurity diffusion layer portion facing the other sidewall. 6. A low-concentration impurity diffusion layer portion extending in the trench direction, and a high-concentration impurity diffusion layer portion adjacent to and parallel to the low-concentration impurity diffusion layer portion. Non-volatile semiconductor memory device. 8. The impurity diffusion layer for separating wirings of a conductivity type opposite to that of the impurity diffusion layer is formed at the bottom of the trench in which the control gate is not formed. A nonvolatile semiconductor memory device according to claim 1. 9. The nonvolatile semiconductor memory device according to claim 1, wherein the conductivity type of the impurity diffusion layer is N type. 10. A step of forming an impurity diffusion layer on the entire surface of a memory cell region of a semiconductor substrate, and thereafter, forming a stripe-shaped trench in the memory cell region of the semiconductor substrate at a depth for separating the impurity diffusion layer. Forming a plurality of control gates at predetermined intervals, and forming a control gate on the impurity diffusion layer in a direction substantially orthogonal to the impurity diffusion layer via an insulating layer, and at a portion where the control gate enters the trench. And a step of forming a memory cell transistor, a method of manufacturing a nonvolatile semiconductor memory device. 11. An impurity diffusion layer for separating wirings is formed in the bottom of the trench other than a portion where a memory cell transistor is formed, in a self-aligned manner with the control gate and the trench, using the control gate as a mask. The method for manufacturing a nonvolatile semiconductor memory device according to claim 10, further comprising a step. 12. The floating gate is formed inside the trench via a gate insulating film, and the control gate is formed on the floating gate via an intermediate insulating film. 12. The method for manufacturing a nonvolatile semiconductor memory device according to 10 or 11. 13. A region having the same conductivity type as the impurity diffusion layer and a high impurity concentration is formed on one side wall of the trench below the trench side wall of the impurity diffusion layer by an oblique ion implantation method. Claims 10 to 12
9. The method for manufacturing a nonvolatile semiconductor memory device according to any one of 1. 14. An impurity diffusion layer separated by the trench is formed so that an impurity diffusion layer portion facing one sidewall of the trench has a higher impurity concentration than an impurity diffusion layer portion facing the other sidewall. 13. The low-concentration impurity diffusion layer portion extending in the trench direction, and the high-concentration impurity diffusion layer portion adjacent to and parallel to the low-concentration impurity diffusion layer portion, according to claim 10. Manufacturing method of non-volatile semiconductor memory device.