JPS63301554A - Method of forming polycrystalline silicon layer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Field of application] Unpublished No. 151 relates to a method for forming a polysilicon layer having both a high sheet resistance value and a low sheet resistance value. The present invention relates to a method for simultaneously fabricating resistor and capacitor elements on a surface. ■Conventional technology l When manufacturing analog circuits, it is safe to obtain capacitors with accurate internal capacitance ratios and resistors with high precision. More specifically, capacitors need to be fabricated to have low voltage coefficients of their capacitance, and precision resistors need to be fabricated to have low temperature and voltage coefficients of their resistance. Devices of this type are typically formed from a layer of doped polysilicon; however, the requirements for fabricating such devices are often competing; for example, for resistance, By introducing impurities into the polysilicon layer to obtain a high sheet resistance value. It is desirable to minimize the size of a resistive element for a given resistance value, while for capacitors, the capacitance can be reduced by introducing impurities into the polysilicon electrode layer to achieve a low sort resistance value. Conventional processes for fabricating these devices include the introduction of impurities in a given polysilicon layer to achieve high and low sheet resistance values, preferably to minimize the voltage coefficient. Then, patterning and etching of the resistive element was performed from the high sheet resistance value region, and patterning and etching of the capacitor element was performed from the low sheet resistance value region. (Problem 1 attempts to solve) However, in the case of 1.L, the etch rate of the polysilicon region with a high sheet resistance value and the polysilicon region with a low sheet resistance value is unfortunately 1!II These different etch rates make it difficult to accurately control the dimensions of each individual element.Thus, the object of the present invention is to achieve high sheet resistance and low sheet resistance. It is an object of the present invention to provide a method for forming a polysilicon layer having a uniform value.A further object of the present invention is to provide a method for fabricating resistive and capacitor elements using a layer of polysilicon. Means for Solving the Problem] 'In order to achieve these objects, the present invention provides a method for forming a polysilicon layer having both high and low sheet resistance values on the surface of a semiconductor. This method of forming a polysilicon layer first includes the step of depositing a lower polysilicon layer on the surface of the semiconductor and doping the lower polysilicon layer with an impurity of a first conductivity type to a low sheet resistance value. A lower electrode is formed by patterning and etching the lower polysilicon layer.After forming a dielectric layer on this lower electrode, an upper polysilicon layer is deposited. Then, the upper polysilicon layer is doped to a high sheet resistance value greater than the low sheet resistance value, and the upper ft pole and resistance element are formed by patterning and etching the upper polysilicon layer. After masking this resistance element, the sheet resistance value of the upper electrode is reduced to the low sheet resistance value by ion-implanting the impurity of the first conductivity type into one surface. It is preferable that the lower electrodes are superimposed on each other to form a capacitor element. The process for forming a polysilicon layer having both a high sheet resistance value and a low sheet resistance value is shown in order of steps.In this conventional process, first, a P-type silicon substrate 10 is
A P-type epitaxial silicon region ffl+2 is grown thereon, and then an N-type well 14 is formed in the P-type epitaxial silicon region 12 by an ion implantation/diffusion method (also referred to as an "indentation" method) according to 7J4. Also using conventional methods, field oxide isolation regions 16 are
jE& let. For this purpose, for example, after depositing a thin oxide layer on the substrate io, silicon nitride (not shown) can be used.
is deposited and patterned and kneed to define moat regions 20.22. Then, the plate 10 is heated to 900°C in an oxidizing atmosphere in a furnace.
The thickness is approximately to, o at a temperature within the range of
Heat until oo angstroms of field oxide layer 16 is grown. The silicon nitride is then etched away and a new thin oxide layer 19 approximately 300 to 500 Angstroms thick is grown. This process is performed on silicon slices with a diameter of about 3 to 6 inches, or other dimensions determined by the configuration of the manufacturing equipment, and each such silicon slice has a number of bars or chips. It is formed. Each chip has a length of, for example, about 1 inch and a radius of about 1/4 inch, and is usually commercially available in a packaged state, and each chip consists of tens of thousands of circuits. As shown in FIG. 1, a polysilicon film having a thickness of about 3,500 angstroms to 5.500 angstroms is deposited on such slices by chemical vapor deposition.
(LPCVD method). Next, on the 1st day of this 15th polysilicon layer, ion implantation with phosphorus was performed to increase the sheet resistance of the exposed portion to approximately 150.
Reduce to ohm/mouth. (This is because it is preferable to reduce the voltage coefficient of capacitance by reducing the sheet resistance value of both electrodes of the capacitor element. On the other hand, by making the resistance element have a high sheet resistance value, the size of the semiconductor bar can be reduced. However, the exact value of the sheet resistance value in this case is determined depending on the design requirements in each case. followed by a sufficient thickness to provide a mask for doping with phosphorus, eg, s, oo. After depositing an angstrom oxide layer (not shown) on the polysilicon layer 18, it is patterned and etched to form the desired resistor and capacitor electrode areas, as shown in FIG. Leaving the mask 25 for forming a resistor element and the mask 27 for forming a capacitor electrode whose radius and length are 18 microns to I/2 microns large, the polysilicon layer 18 is then placed in a high temperature heating furnace (311!). by exposure to phosphoryl (POCI). A sheet resistance of 20 to 30 ohm/m is doped with phosphorus and exposed to this phosphoryl 3111 compound.
Let it be your mouth. Note that during this doping process, phosphorus diffuses below the resistor element forming phase mask 25 and the capacitor electrode forming mask 27 along the knee and jig portions of these masks, resulting in high sheet resistance regions corresponding to each other. It will be slightly smaller than the mask. Next, the oxide layer serving as the resistive element forming mask 25 and the capacitor electrode forming mask 27 is removed by etching, and then a photoresist is deposited and patterned to form a mask 31 on the resistive element 32.
Ti electrode formation mask 35. and gate formation mask 3
3 is formed as shown in FIG. By subsequently etching the polysilicon layer 18, a gate 24 is formed in the moat region 20F, a resistor element 32 is formed in some of the field oxide regions 1B, as shown in FIG. Further, electrodes of capacitor elements or mere electrode portions are left in other field oxide regions 1B. A thermal oxide layer is then grown on the capacitor electrode 26 to a thickness of approximately 1,110 angstroms. At this time, a thermal oxide layer 28 similar to the oxide layer 28 is simultaneously formed on the polysilicon gate 24 and the resistor element 32. An important requirement for a switched capacitor is that the thickness of its oxide layer be uniform. However, since it is difficult to control the growth of oxide on polysilicon electrodes with low sheet resistance, it is difficult to control the growth of oxides on polysilicon electrodes with low sheet resistance.
It remains n. To this end, following the growth step of the oxide layer 28, a second polyurethane film is deposited on the Mu slice (not shown) to a thickness of about 3,000 to 5,000 angstroms, as shown in FIG. A silicon layer 30 is deposited and doped with phosphorus by exposing it to phosphoryl 11-11 in a high temperature furnace to reduce its sheet resistance to approximately 20 ohms per mouth. do. By then patterning and etching this second polysilicon layer 30,
An upper @pole 34 is left, a portion 38 of which overlaps the lower electrode 26, as shown in FIG. Subsequently, the photoresist layer 3B is examined. This is patterned and etched to cover the resistive element portion 32 as shown in FIG. Next, arsenic ion implantation is performed to form the source/moat region 20.
The drain region and N medium region 22 are each approximately 20 to 40 ohms 10. After that, the 8th
removing the photoresist layer 36 as shown in the figure;
By annealing the device,
At the same time as activating the arsenic impurity, the ion implantation region is subjected to 7-annealing. The main problem with the procedure described above is: It is in the etching process from FIG. 3 to FIG. 4. Generally, the etch rate of a polysilicon layer depends on the doping level. Therefore, the etch rate of the polysilicon layer below the photoresist mask 33 is faster than that of the polysilicon layer below the masks 31 and 35. As a result, the portion of the polysilicon layer below the gate mask 33 and along the mask is etched away. Therefore, the dimensions of the polysilicon layer 24 are adjusted to the photoresist mask 33.
It will be smaller than that. As a result of this, it becomes difficult to simultaneously and accurately control the respective dimensions of the resistive element 32, the capacitor element electrode layer 26, and the transistor gate layer 24. Two major requirements for analog circuits are that the capacitor element has an accurate internal capacitance ratio, and the resistor element has high precision. Furthermore, considering that a process of forming two polysilicon layers is generally used when constructing analog circuits, a polysilicon layer that is doped multiple times can be used to construct circuits with the above requirements. This is a serious hindrance to configuration. The demand for increasing the sheet resistance of a resistive element while decreasing the sheet resistance of a bare capacitor element makes the problem of etch rate even more difficult. A further consequence of having to perform the polysilicon etch process in two separate steps is that a mask with an etch bias used within the low sheet resistance value φ region while defining resistive elements, capacitor elements, gate regions, etc. There may be a need to use masks with different etch biases for high sheet resistance regions. As a result of these requirements, it is difficult to accurately set the resistance, capacitance, and gate length of transistor devices. □ 1st Embodiment The present invention will be described in detail below with reference to FIGS. 9 to 15. In the embodiment shown in FIGS. 9-15, a thickness of approximately 3,500 to 5,000 .ANG. A poly-silicon layer 50 of 1,000 angstroms is deposited. This polysilicon P! :50, ion implantation with phosphorus is performed to such an extent that the sheet resistance of the layer is reduced to within the range of 15 to 50 ohms, 10, or more preferably to 20 ohms, 10, as shown in FIG. However, this phosphorus doping step may be carried out by exposing the polysilicon layer 5G to phosphoryl trichloride in a high-temperature heating furnace.Then, as shown in FIG. 11, the photoresist layer is patterned. Masks 80 and 82 are left and these masks form the gate 64 and the lower electrode 6 of the capacitor element.
The first F! ! Bolinlicon layer 50
Etch the gate 64 and the bottom plate of the capacitor element. jj J41 Ei After leaving 8,
+i: Remove photoresist mask 80.62. An oxide layer about 100 to 200 angstroms thick is then deposited or grown by oxidation of a polysilicon layer, followed by a nitride layer also about 100 to 200 angstroms thick by low pressure chemical vapor deposition. . After deposition of this nitride layer. A portion of the thickness of the nitride layer is oxidized to form a second oxide layer having a thickness of about 20 to 50 angstroms. The oxide/nitride/oxide layer thus formed provides a dielectric with higher gear passance per unit area and lower defect density than would be obtained with a single oxide layer of equivalent thickness. The body layer is obtained. Yet again. The dielectric layer is not affected by other processing steps. That is, since it does not have a pro-7 dependence, the layer can be made thinner than f5 previously described with respect to FIGS. Next, a second fi polysilicon layer F2 with a thickness of about 3 and Q
QO or 5. After being deposited to a thickness of 0.00 angstroms, the layer is ion-implanted with phosphorus to a phosphorus density in the range of about 2 to 6XH+5atoms/crn', which is about 150 ohms. However, depending on design requirements, the sheet resistance value may be within a wider range, such as 100 to 1,000 ohms. After the slice is then ion-implanted with phosphorus again, a mask 74.7G for the upper plate of the resistor and capacitor elements is formed as shown in FIG.
, and then the second polysilicon layer 72
The oxide in the moat region 20.22 is then etched away to form a new moat oxide layer while leaving the resistor element portion 8G and the upper plate or electrode 78 of the capacitor element. An oxide film is grown on the device 80 and the top electrode 78 of the capacitor device. Then, as shown in FIG. 14, a photoresist layer 82 is formed.
After covering the resistive element portion 80 by depositing and patterning the same, the exposed portion of the slice is exposed to approximately 8×10 at an output of approximately 80 to 120 keV.
By performing arsenic ion implantation at a ve degree of 1f1atoss/crn', N-type source/drain regions 82,84. A contact portion 8B is formed, and an upper portion 1t of the capacitor element is formed.
Ion implantation for t8i lowers its sheet resistance to about 30-50 ohms/mouth. After the arsenic ion implantation, the slice is subjected to 7-anneal treatment at a temperature of 800° C. to 1.000° C. for about 1/2 to 1 hour. Figure m16 is a top view corresponding to the cross-sectional view of Figure 15, and shows the resistance element 80 in the semiconductor chip and the el
llm contact portion B1. transistor gate 6
4 and polysilicon wiring #s, gate contact portion SO formed on portion 8B, source/drain regions 82, 84
Source/drain contact portions 92, 94 . correspondingly formed thereon. It shows the arrangement of a switching capacitor element 7S having an upper electrode 78 and a lower electrode 66, a contact region 86 of an N-type tank, and the like. As a variant of the process described above, the gate of the transistor element may be formed not from the first polysilicon layer as described above, but from a second or upper polysilicon layer. In this case, ions are implanted into the second polysilicon layer using a lithium ion so that its sheet resistance (1 is finally 30 to 50 ohm/mouth). In the process according to the present invention described with reference to FIG. 15 (hereinafter referred to as the process according to the present invention), a single mask is first used to pattern the first polysilicon layer as described with reference to FIG. , only another mask is used to pattern the @2B polysilicon layer as described with respect to FIG. 13, but the process described with respect to FIGS. The conventional process requires a mask that defines the oxide pattern for the resistive element, a mask that defines the pattern of the first polysilicon layer, and a mask that defines the pattern of the second polysilicon layer. Thus, the Lufrous process according to the present invention corresponding to FIGS. In the process according to the invention, or variations thereof, forming complementary devices typically involves patterning and ion implantation of P-type regions, steps which are not directly relevant to the subject matter of the invention. Further, in the process according to the present invention, it is also possible to perform the doping treatment of the polysilicon layer only once, in which case the above-mentioned doping treatment is omitted. The etch rate of each part of the semiconductor bar is no longer different, as would be the case if multiple doping processes were carried out.A further advantage of the process according to the present invention is that the thickness of the interlayer dielectric layer can be reduced. , the capacitance per unit area can be increased without affecting other process parameters.Furthermore, the resistive element, the lower capacitor electrode and the gate of the transistor can be An important feature of the present invention is that it does not require the use of separate masks to obtain different doping levels of type 21a in a given polysilicon layer, as in conventional methods. Thus, by using the process according to the present invention, it is possible to reduce the gou area by 10% to 30%, and the performance of the resulting device is also better.
The noise level is also low, and M and the source unsuitability rate are also improved compared to the conventional method. In conjunction with the above description, the following sections will be further disclosed. (1) In forming a polysilicon layer having both high and low sheet resistance values on the surface of a semiconductor. depositing a lower polysilicon layer on the surface of the semiconductor;
a step of doping this lower polysilicon layer with an impurity of conduction type 51 to a sheet resistance value of t51; forming a lower electrode by patterning and etching the monolayer lower polysilicon layer; forming a dielectric layer on the lower electrode; coating an upper polysilicon layer on the surface of the semiconductor; and adjusting the upper polysilicon layer to a second sheet resistance value using impurities of the first conductivity type. and the process of doping. forming an upper electrode by patterning and etching the upper polysilicon layer; A step of forming a polysilicon layer as a resistive element in any of the patterning and etching steps for the polysilicon layer of the lower layer and the -E layer; After masking the polysilicon layer as a resistive element 9
ion-implanting impurities of the first conductivity type into the surface, thereby setting the sheet resistance value of the upper electrode to the lower one of the first and second sheet resistance values. A method for forming a polysilicon layer characterized by: (2) The upper electrode and the lower electrode are overlapped with each other to form a capacitor element. The polysilicon layer forming method described above. (3) The polysilicon according to item 1, which includes a step of patterning and etching a gate of a transistor element from one of the upper and lower polysilicon layers in addition to the above steps. Layer formation method. (4) The dielectric layer is formed by forming an oxide layer, then forming a nitride layer, and then partially oxidizing this nitride layer. Silicon layer formation method. (5) The gate of the transistor element is formed by patterning and etching the lower polysilicon layer, and the ion implantation into the source/drain region self-aligned with the gate of the transistor element is performed by the ion implantation into the upper electrode. The third step was performed at the same time.
The polysilicon layer forming method described in . (6) The thickness of the oxide layer is 100 to 200 mm.
The thickness of the adjacent nitride layer is in the range of 100 to 200 angstroms, and the thickness of the partially catalyzed nitride region is in the range of 20 to 50 angstroms. 5. The method for forming a polysilicon layer according to item 4. (7) The method for forming a polysilicon layer according to item 1, wherein the first conductivity type is N type. (8) The thickness of the lower polysilicon layer is 3°5
00 to 4. 2. The method for forming a polysilicon layer according to item 1 above, wherein the polysilicon layer is formed within a range of 10 angstroms. (9) The method for forming a polysilicon layer according to item 1, wherein the impurity implanted into the upper electrode layer is arsenic. (lO) In forming a resistance element and a capacitor element on the surface of a semiconductor. Depositing a lower polysilicon layer on the surface of the semiconductor and doping the lower polysilicon layer with impurities of a first conductivity type to a low sheet resistance. patterning and etching the lower polysilicon layer to form a lower electrode of the capacitor; forming a dielectric layer on the surface of the semiconductor; further depositing an upper polysilicon layer on the surface of the semiconductor and doping the upper polysilicon layer to a high sheet resistance with impurities of the first conductivity type. patterning and etching the upper polysilicon layer to form an upper electrode of a capacitor covering a resistive element and a lower electrode of the capacitor; After masking this polysilicon layer as a resistive element,
A resistor comprising the step of ion-implanting the impurity of the first conductivity type into the surface so that the sheet resistance value of the upper part '\tJ4i of the capacitor becomes the low sheet resistance value. and a method for forming a capacitor element. (The resistor according to item 1O above, wherein the dielectric layer is formed by forming an oxide layer, then forming a nitride layer, and further oxidizing a part of this nitride layer, and A method for forming a capacitor element. (12) A method for forming a resistor and a capacitor element according to the above item 10, in which the first conductivity type is Ny!:i. (13) In addition to each of the steps, □ The method for forming resistor and capacitor elements as described in paragraph jSlo above, comprising the step of patterning and etching the gate of the transistor element on the moat region from the polysilicon layer. (14) High sheet resistance on the surface of the semiconductor. To form a polysilicon layer having both high and low sheet resistance, a lower polysilicon layer is first deposited on the surface of the semiconductor, and a first conductivity type impurity is used to form the lower polysilicon layer with a low sheet resistance. A bottom electrode is formed by doping the polysilicon to a certain level and patterning and etching the bottom polysilicon layer, forming a dielectric layer on top of the bottom electrode, and then depositing the top polysilicon layer. The upper polysilicon layer is then doped to a high sheet resistance value greater than the low sheet resistance value, and the upper polysilicon layer is patterned and etched to form an upper electrode and a resistive element. After masking the resistor element, impurities of the first conductivity type are ion-implanted onto the surface of the resistor element to set the sheet resistance value of the upper electrode to the low sheet resistance value, thereby forming a high sheet resistance on the surface of the semiconductor. A method for forming a polysilicon layer having both a low sheet resistance value and a low sheet resistance value. Hereinafter, I have explained about the embodiments of the present invention. The method using unexploded IJ+ has been added as appropriate to the described embodiments. It goes without saying that it may be implemented with some modifications.

[Brief explanation of drawings]

1 to 8 are partially enlarged cross-sectional views of a semiconductor chip showing the process of manufacturing a resistor element, a capacitor element, and a MOS transistor element using a conventional method in the order of steps, and FIGS. 9 to 15 are Resistive elements, capacitor elements and MOS devices using an embodiment of the method according to the invention
FIG. 16 is a partially enlarged cross-sectional view of a semiconductor chip showing the process of manufacturing a transistor element in order of steps.
6 is a top view showing the arrangement of a gate of a transistor, a moat region resistance element, and a capacitor element in the semiconductor chip shown in FIG. 5; FIG. 10. Silicon substrate. 12. P-type epitaxial region. 14. N-type well. 1B, , field oxide region. 64,,,,,gate. ee, lower electrode. 7B...Top electrode. 79, Capacitor element. 80,..., resistance element. 82784, , Source/drain region. Applicant: Texas Instruments Incorporated = T'tr:; Right and wrong (method) 1. Indication of the case 1988 Patent Application No. 6714 2. Name of the invention Method for forming a polysilicon layer 3. Person making the amendment Relationship with the case Patent applicant address: Dallas, Texas, USA 135004 Central Expressway Agent:
150 Address 1-20F Dogenzaka, Shibuya-ku, Tokyo! i2 issue (shipped on May 31, 1988)

Claims (2)

[Claims] (1) In forming a polysilicon layer having both a high sheet resistance value and a low sheet resistance value on the surface of a semiconductor, a lower polysilicon layer is deposited on the surface of the semiconductor and an impurity of the first conductivity type is formed. doping the lower polysilicon layer to a first sheet resistance value; patterning and etching the lower polysilicon layer to form a lower electrode; and depositing a dielectric on the lower electrode. forming a layer of polysilicon, depositing an upper polysilicon layer on the surface of the semiconductor;
doping the upper polysilicon layer with impurities of the first conductivity type to a second sheet resistance value; and forming an upper electrode by patterning and etching the upper polysilicon layer. , a step of forming a polysilicon layer as a resistive element in either of the patterning and etching steps for the lower and upper polysilicon layers, and after masking the polysilicon layer as the resistive element,
The step of ion-implanting impurities of the first conductivity type into the surface makes the sheet resistance value of the upper electrode the lower of the first and second sheet resistance values. A polysilicon layer forming method characterized by: (2) When forming a resistor element and a capacitor element on the surface of a semiconductor, a lower polysilicon layer is deposited on the surface of the semiconductor, and the lower polysilicon layer is made to have a low sheet resistance by doping with impurities of the first conductivity type. forming a lower electrode of a capacitor by patterning and etching a lower polysilicon layer of the polysilicon; forming a dielectric layer on a surface of the semiconductor; depositing an upper polysilicon layer on the surface of the semiconductor, doping the upper polysilicon layer to a high sheet resistance with impurities of the first conductivity type, and patterning the upper polysilicon layer. and a step of forming an upper electrode of the capacitor that covers the resistive element and the lower electrode of the capacitor by performing etching, and after masking the polysilicon layer as the resistive element,
A resistor and a capacitor characterized in that the resistor and the capacitor include the step of ion-implanting the impurity of the first conductivity type into the surface so that the sheet resistance value of the upper electrode of the capacitor becomes the low sheet resistance value. Element formation method.