JPH0247853B2 - - Google Patents
Info
- Publication number
- JPH0247853B2 JPH0247853B2 JP57052775A JP5277582A JPH0247853B2 JP H0247853 B2 JPH0247853 B2 JP H0247853B2 JP 57052775 A JP57052775 A JP 57052775A JP 5277582 A JP5277582 A JP 5277582A JP H0247853 B2 JPH0247853 B2 JP H0247853B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- conductive film
- conductivity type
- window
- base region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 16
- 239000012535 impurity Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000002844 melting Methods 0.000 claims description 4
- 230000008018 melting Effects 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 229910021332 silicide Inorganic materials 0.000 claims description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 229910016006 MoSi Inorganic materials 0.000 description 17
- 229910004298 SiO 2 Inorganic materials 0.000 description 15
- 229910052698 phosphorus Inorganic materials 0.000 description 7
- 239000011574 phosphorus Substances 0.000 description 7
- 229910052796 boron Inorganic materials 0.000 description 6
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- -1 phosphorus ions Chemical class 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910020968 MoSi2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
Description
【発明の詳細な説明】
(a) 発明の技術分野
本発明は半導体装置およびその製造方法に関
し、特にバイポーラトランジスタ形集積回路装置
に応用される構造とその製法に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a structure applied to a bipolar transistor type integrated circuit device and a method for manufacturing the same.
(b) 従来技術と問題点
従来のバイポーラトランジスタは、その断面構
造が第１図に示されているように半導体基板１上
にベース領域２およびエミツタ領域３を設け、そ
の上に形成した二酸化シリコン（SiO2）膜４に
窓あけして、ベース電極５およびエミツタ電極６
が形成される。一方、MOSトランジスタはゲー
ト電極を設けて、セルフアライン（自己整合）に
よつて形成する方法が汎用されており、小型化・
高密度化が容易で、LSI，VLSIは殆んどMOS形
素子で形成されるといつてよい。そのため、バイ
ポーラトランジスタも高密度化の検討がなされて
おり、多種提案されているが、MOSトランジス
タに対抗しうる方法は未だ開発に至つていない。
同一形状なれば基本的には、バイポーラトランジ
スタはすぐれた周波数特性・スイツチング特性が
えられる筈である。(b) Prior Art and Problems A conventional bipolar transistor has a cross-sectional structure as shown in FIG. 1, in which a base region 2 and an emitter region 3 are provided on a semiconductor substrate 1, and a silicon dioxide film formed thereon is used. A window is opened in the (SiO 2 ) film 4, and a base electrode 5 and an emitter electrode 6 are formed.
is formed. On the other hand, MOS transistors are commonly formed by providing a gate electrode and using self-alignment.
It is easy to increase the density, and it can be said that most LSIs and VLSIs are formed using MOS type elements. Therefore, studies have been made to increase the density of bipolar transistors, and various proposals have been made, but a method that can compete with MOS transistors has not yet been developed.
As long as they have the same shape, bipolar transistors should basically have excellent frequency characteristics and switching characteristics.
(c) 発明の目的
本発明はこのようなバイポーラトランジスタに
おいて、その形状を極めて小型化して、動作速度
を速くすることを目的とした半導体装置およびそ
の製法を提案するものである。(c) Object of the Invention The present invention proposes a semiconductor device and a method for manufacturing the same, which aim to significantly reduce the size of such a bipolar transistor and increase its operating speed.
(d) 発明の構成
その目的は、ベース領域に接する一導電型不純
物ドープの高融点メタルシリサイドからなり窓を
設けた導電膜と、該導電膜の窓部においてエミツ
タ領域と接し、且つ該導電膜表面酸化の絶縁膜を
介して上記導電膜上に延在する第２の導電膜とが
設けられた半導体装置と、半導体基板上に一導電
型不純物ドープの高融点メタルシリサイドからな
り窓を設けた導電膜を形成し、熱酸化により表面
に絶縁膜を形成する工程と、上記導電膜より該半
導体基板に該一導電型不純物を導入してベース領
域の周囲部分を形成する工程と、上記導電膜をマ
スクとして、該導電膜に設けた窓より一導電型不
純物および反対導電型不純物を導入し、ベース領
域の中心部分およびエミツタ領域を形成する工程
とが含まれてなる製造方法によつて達成すること
ができる。(d) Structure of the Invention The object of the invention is to provide a conductive film made of high melting point metal silicide doped with one conductivity type impurity and provided with a window, which is in contact with a base region, and which is in contact with an emitter region at the window portion of the conductive film, and which is in contact with an emitter region. A semiconductor device is provided with a second conductive film extending on the conductive film through a surface oxidized insulating film, and a window is provided on the semiconductor substrate made of high melting point metal silicide doped with one conductivity type impurity. a step of forming a conductive film and forming an insulating film on the surface by thermal oxidation, a step of introducing the one conductivity type impurity into the semiconductor substrate from the conductive film to form a peripheral portion of the base region, and the conductive film This is achieved by a manufacturing method that includes the step of introducing impurities of one conductivity type and impurities of opposite conductivity through a window provided in the conductive film using as a mask to form a central portion of a base region and an emitter region. be able to.
(e) 発明の実施例
第２図は本発明にかゝる半導体装置の一実施例
の断面構造図を示しており、モリブデンシリサイ
ド膜７からなり窓を設けたベース導電膜によつて
ベース領域２の周囲部分が形成され、表面酸化に
よる絶縁膜８を介して、上記窓部にエミツタ導電
膜９が形成され、その直下にベース領域２の中心
部分と、エミツタ領域３とが形成された構造であ
る。(e) Embodiment of the invention FIG. 2 shows a cross-sectional structural diagram of an embodiment of the semiconductor device according to the invention, in which a base conductive film made of a molybdenum silicide film 7 and provided with a window forms a base region. 2 is formed, an emitter conductive film 9 is formed in the window portion via an insulating film 8 formed by surface oxidation, and the central portion of the base region 2 and the emitter region 3 are formed directly below it. It is.
その製造方法を説明すると第３図ないし第６図
は本発明にかゝる製法の工程順断面図を示す。先
づ、第３図に示すようにＰ型半導体基板１１上に
高温酸化して膜厚1μｍ程度のSiO2膜１２からな
るフイールド絶縁膜を形成する。次いで、第３図
に示すようにその表面にスパツタ法により膜厚
3000Åのモリブデンシリサイド（MoSi2）膜１３
を被着し、リソグラフイ技術を用いて、パターン
ニングしてエミツタ領域のみ露出させる。MoSi2
膜１３は高濃度に燐を含有させた膜とする。 To explain the manufacturing method, FIGS. 3 to 6 show step-by-step cross-sectional views of the manufacturing method according to the present invention. First, as shown in FIG. 3, a field insulating film made of an SiO 2 film 12 having a thickness of about 1 μm is formed on a P-type semiconductor substrate 11 by high-temperature oxidation. Next, as shown in Figure 3, a thick film is applied to the surface by sputtering.
3000Å molybdenum silicide (MoSi 2 ) film 13
is deposited and patterned using lithography techniques to expose only the emitter region. MoSi 2
The film 13 is a film containing phosphorus at a high concentration.
次いで、第５図に示すように700℃の加湿酸素
気流中で100分間処理すれば、燐をドープした
MoSi2膜１３の表面が酸化されて、膜厚2000Å程
度のSiO2膜１４が形成され、次に上面から燐イ
オンを注入し、更に硼素イオンを注入する。燐イ
オンは加速電圧100KeV、ドーズ量１×1012／cm2、
硼素イオンは加速電圧40KeV、ドーズ量１×
1015／cm2程度にする。尚、第７図は700℃、加湿
酸素気流中でのドープMoSi2膜表面のSiO2膜厚と
処理時間との関係図表であり、線がドープ
MoSi2膜上のSiO2膜のそれらの関係を示す。 Then, as shown in Figure 5, the phosphorus-doped material was treated in a humidified oxygen stream at 700°C for 100 minutes.
The surface of the MoSi 2 film 13 is oxidized to form a SiO 2 film 14 with a thickness of about 2000 Å, and then phosphorus ions are implanted from the top surface and boron ions are further implanted. Phosphorus ions have an acceleration voltage of 100 KeV, a dose of 1×10 12 /cm 2 ,
Boron ion has an acceleration voltage of 40KeV and a dose of 1×
Make it about 10 15 / cm 2 . Furthermore, Figure 7 is a graph showing the relationship between the SiO 2 film thickness on the surface of the doped MoSi 2 film and the processing time at 700°C in a humidified oxygen stream, and the line indicates the doped
The relationship between them for SiO2 film on MoSi2 film is shown.
次いで、第６図に示すように900〜1000℃の高
温度で熱処理して、上記のイオン注入によるｎ型
ベース領域１５とP+型エミツタ領域１６とを画
定し、且つ燐ドープMoSi2膜からの拡散によりそ
の周囲にｎ型ベース領域１７を形成し、エミツタ
領域１６は完全にベース領域で取り囲ませる。ベ
ース領域１７はその形成方法からしてMoSi2膜と
の接合抵抗が極めて低いものとなる。以降はエミ
ツタ電極を公知の方法で形成して素子を完成し、
MoSi2膜はベース電極に利用する。 Next, as shown in FIG. 6, heat treatment is performed at a high temperature of 900 to 1000° C. to define the n-type base region 15 and the P + type emitter region 16 by the above-mentioned ion implantation, and to form the phosphorus-doped MoSi 2 film. An n-type base region 17 is formed around it by diffusion, and the emitter region 16 is completely surrounded by the base region. The base region 17 has an extremely low bonding resistance with the MoSi 2 film due to its formation method. After that, emitter electrodes are formed using a known method to complete the device.
MoSi 2 film is used for the base electrode.
次に、第８図ないし第１０図は本発明にかゝる
他の実施例を示す工程順断面図である。第８図
は、前記実施例における工程順と同様にして、燐
をドープしたMoSi2膜１３を被着してパターンニ
ングし、700℃で加湿酸化して、その表面にSiO2
膜１４を形成した工程断面図である。次いで、弗
酸溶液によつて数10秒エツチングし、表層の
SiO2膜を除去するが、これはエミツタを形成せ
んとする基板露出面上のSiO2膜をエツチング除
去する目的であり、その膜厚は300Å程度である
から、MoSi2膜１３上の膜厚2000ÅのSiO2膜１４
と比べると充分に薄いため、全面のSiO2膜をエ
ツチングしても露出面のSiO2膜を除去し、MoSi2
膜上のSiO2膜１４を残存させることができる。
第７図に示す線はシリコン基板上のSiO2膜の
生成膜厚と処理時間との関係を示し、線と比較
すれば、その差は明かで、このようにドープ
MoSi2膜は酸化されやすくて、基板は酸化されに
くい。 Next, FIGS. 8 to 10 are process-order sectional views showing other embodiments of the present invention. FIG. 8 shows that a phosphorous-doped MoSi 2 film 13 is deposited and patterned in the same manner as in the process order of the previous embodiment, and then humidified and oxidized at 700°C to form SiO 2 on its surface.
FIG. 3 is a cross-sectional view of the process in which the film 14 was formed. Next, etching is performed for several tens of seconds using a hydrofluoric acid solution to remove the surface layer.
The purpose of removing the SiO 2 film is to remove the SiO 2 film on the exposed surface of the substrate where emitters are not to be formed, and the film thickness is approximately 300 Å, so the film thickness on the MoSi 2 film 13 is approximately 300 Å. 2000Å SiO 2 film 14
Because it is sufficiently thin compared to the MoSi 2 film, even if the entire SiO 2 film is etched, the exposed SiO 2 film will be removed and the MoSi 2 film will be etched.
The SiO 2 film 14 on the film can remain.
The line shown in Figure 7 shows the relationship between the thickness of the SiO 2 film formed on the silicon substrate and the processing time.If you compare it with the line, the difference is obvious.
The MoSi 2 film is easily oxidized, and the substrate is not easily oxidized.
次いで、第９図に示すように、その上面に燐と
硼素との双方を含んだMoSi2膜１８をスパツタ法
で被着し、リソグラフイ技術を用いて、パターン
ニングしてエミツタ電極形状にする。次いで、
1000℃、20分間熱処理すると、第１０図に示すよ
うに、MoSi2膜１３より燐が拡散して周囲にｎ型
ベース領域１９を形成し、MoSi2膜１８より硼素
を拡散してP+型エミツタ領域２０を形成すると
共に燐を拡散して、その下層にｎ型ベース領域２
１を形成する。このように都合良くベース領域が
形成されるが、これは拡散係数が相異しているか
らで、上記のように1000℃、20分処理では、燐は
0.6〜0.7μｍ程度まで拡散し、硼素は0.4μｍ程度の
拡散層が形成される。したがつて、約2000Åのベ
ース幅を形成することができる。かくして、
MoSi2膜はそのまゝエミツタ電極として利用され
る。 Next, as shown in FIG. 9, a MoSi 2 film 18 containing both phosphorus and boron is deposited on its upper surface by sputtering, and patterned using lithography to form an emitter electrode shape. . Then,
When heat treated at 1000°C for 20 minutes, as shown in FIG. 10, phosphorus diffuses from the MoSi 2 film 13 to form an n-type base region 19 around it, and boron diffuses from the MoSi 2 film 18 to form a P + type base region. An emitter region 20 is formed, phosphorus is diffused, and an n-type base region 2 is formed under the emitter region 20.
Form 1. The base region is conveniently formed in this way, but this is because the diffusion coefficients are different.As mentioned above, in the treatment at 1000℃ for 20 minutes, phosphorus is
Boron is diffused to a depth of about 0.6 to 0.7 μm, and a diffusion layer of boron of about 0.4 μm is formed. Therefore, a base width of about 2000 Å can be formed. Thus,
The MoSi 2 film is used as is as an emitter electrode.
これらの実施例のように形成すれば、ベース電
極はMoSi2膜１３をそのまゝ利用し、エミツタ電
極とベース電極とは膜厚2000Å前後のSiO2膜１
４で絶縁されているから、極めて高密度化された
素子となり、これ以上の小型化は難しい形状で、
現状のパターン精度では、そのバイポーラトラン
ジスタを２〜3μｍ角の面積内に形成することが
できる。 If formed as in these embodiments, the base electrode will use the MoSi 2 film 13 as is, and the emitter electrode and the base electrode will be formed using the SiO 2 film 1 with a film thickness of about 2000 Å.
Since it is insulated by 4, it becomes an extremely high-density element, and the shape is difficult to miniaturize further.
With the current pattern accuracy, the bipolar transistor can be formed within an area of 2 to 3 μm square.
(f) 発明の効果
以上の説明から判るように、本発明はセルフア
ラインによつてバイポーラ素子を形成する製造方
法で、このようにすれば極度に高集積化されて、
極めて高速化された半導体装置がえられるもので
ある。(f) Effects of the invention As can be seen from the above explanation, the present invention is a manufacturing method for forming bipolar elements by self-alignment, and by doing so, extremely high integration can be achieved.
A semiconductor device with extremely high speed can be obtained.
第１図は従来のバイポーラトランジスタの構造
断面図、第２図は本発明にかゝる半導体装置の構
造断面図、第３図ないし第６図及び第８図ないし
第１０図は本発明にかゝる製造方法の工程順断面
図、第７図はSiO2膜の生成膜厚と熱処理時間と
の関係図表である。
図中、１，１１は半導体基板、２，１５，１
７，１９，２１はベース領域、３，１６，２０は
エミツタ領域、４，１２，１４はSiO2膜、１３，
１８はMoSi2膜を示す。
FIG. 1 is a structural cross-sectional view of a conventional bipolar transistor, FIG. 2 is a structural cross-sectional view of a semiconductor device according to the present invention, and FIGS. 3 to 6 and 8 to 10 are structural cross-sectional views of a semiconductor device according to the present invention. FIG. 7 is a cross-sectional view showing the steps in the manufacturing method, and is a chart showing the relationship between the thickness of the SiO 2 film and the heat treatment time. In the figure, 1 and 11 are semiconductor substrates, 2, 15, 1
7, 19, 21 are base regions, 3, 16, 20 are emitter regions, 4, 12, 14 are SiO 2 films, 13,
18 indicates a MoSi 2 film.
Claims (1)
高融点メタルシリサイドからなり窓を設けた導電
膜と、該導電膜の窓部においてエミツタ領域と接
し、且つ該導電膜表面酸化の絶縁膜を介して上記
導電膜上に延在する第２の導電膜とが設けられた
ことを特徴とする半導体装置。 ２ 半導体基板上に一導電型不純物ドープの高融
点メタルシリサイドからなり窓を設けた導電膜を
形成し、熱酸化により表面に絶縁膜を形成する工
程と、上記導電膜より該半導体基板に該一導電型
不純物を導入してベース領域の周囲部分を形成す
る工程と、上記導電膜をマスクとして、該導電膜
に設けた窓より一導電形不純物および反対導電型
不純物を導入し、ベース領域の中心部分およびエ
ミツタ領域を形成する工程とが含まれてなること
を特徴とする半導体装置の製造方法。[Claims] 1. A conductive film made of high melting point metal silicide doped with one conductivity type impurity and provided with a window, which is in contact with a base region, and which is in contact with an emitter region at the window portion of the conductive film, and whose surface is oxidized. A semiconductor device comprising: a second conductive film extending over the conductive film with an insulating film interposed therebetween. 2. A step of forming a conductive film made of high melting point metal silicide doped with one conductivity type impurity and provided with a window on a semiconductor substrate, forming an insulating film on the surface by thermal oxidation, and applying the conductive film to the semiconductor substrate. A process of introducing conductivity type impurities to form the peripheral portion of the base region, and using the conductive film as a mask, introducing one conductivity type impurity and an opposite conductivity type impurity through the window provided in the conductive film to form the center of the base region. 1. A method of manufacturing a semiconductor device, comprising the steps of forming a portion and an emitter region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5277582A JPS58169971A (en) | 1982-03-30 | 1982-03-30 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5277582A JPS58169971A (en) | 1982-03-30 | 1982-03-30 | Semiconductor device and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58169971A JPS58169971A (en) | 1983-10-06 |
| JPH0247853B2 true JPH0247853B2 (en) | 1990-10-23 |
Family
ID=12924230
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5277582A Granted JPS58169971A (en) | 1982-03-30 | 1982-03-30 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58169971A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3230050A1 (en) * | 1982-08-12 | 1984-02-16 | Siemens AG, 1000 Berlin und 8000 München | INTEGRATED SEMICONDUCTOR CIRCUIT WITH BIPOLAR COMPONENTS AND METHOD FOR THE PRODUCTION THEREOF |
| US5077227A (en) * | 1986-06-03 | 1991-12-31 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
| JP2692292B2 (en) * | 1989-09-02 | 1997-12-17 | 富士電機株式会社 | Vertical bipolar transistor for integrated circuit devices |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5690561A (en) * | 1979-12-22 | 1981-07-22 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS5735370A (en) * | 1980-08-12 | 1982-02-25 | Nec Corp | Semiconductor device |
| JPS5843573A (en) * | 1981-09-08 | 1983-03-14 | Matsushita Electric Ind Co Ltd | Bi-polar transistor |
| JPS58142573A (en) * | 1982-02-19 | 1983-08-24 | Hitachi Ltd | Semiconductor integrated circuit and preparation thereof |
-
1982
- 1982-03-30 JP JP5277582A patent/JPS58169971A/en active Granted
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5690561A (en) * | 1979-12-22 | 1981-07-22 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS5735370A (en) * | 1980-08-12 | 1982-02-25 | Nec Corp | Semiconductor device |
| JPS5843573A (en) * | 1981-09-08 | 1983-03-14 | Matsushita Electric Ind Co Ltd | Bi-polar transistor |
| JPS58142573A (en) * | 1982-02-19 | 1983-08-24 | Hitachi Ltd | Semiconductor integrated circuit and preparation thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58169971A (en) | 1983-10-06 |
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