JP2692292B2 - Vertical bipolar transistor for integrated circuit devices - Google Patents

Description

The present invention relates to a vertical bipolar transistor suitable for having a relatively large current capacity in a small chip area when incorporated in an integrated circuit device.

[Conventional technology]

The operating speed and current capacity of the bipolar transistor incorporated in the integrated circuit device are often different from those of the MOS transistor, and thus the required chip area tends to be slightly larger. A structure has been developed in which electrodes and wirings are formed by using a crystalline silicon film. An outline of a conventional example of this type of bipolar transistor will be described below with reference to FIG.

As shown in FIG. 5 (a), first, as is customary, an n-type epitaxial layer 3 is grown on a p-type substrate 1 in which an n-type buried layer 2 is diffused to form a collector region, and the collector region is oxidized. After forming the film 21 in a predetermined pattern, boron or the like is ion-implanted for the p-type base layer using the photoresist film as a mask M.

In FIG. 2B, the polycrystalline silicon layer 23 and the silicon nitride film 24 are grown on the entire surface, and then the silicon nitride film is patterned, and the polycrystalline silicon layer 23 is selectively used as an oxide film 25 by using this as a mask. By oxidizing, a polycrystalline silicon film 23 is formed on the electrode and wiring patterns, and at the same time, the ion-implanted impurities are thermally diffused as shown in FIG. In FIG. 3C, first, a silicon nitride film
Part of 24 is removed by photoetching to expose a predetermined portion of polycrystalline silicon layer 23, and then n-type impurities such as phosphorus are ion-implanted through the exposed portion of polycrystalline silicon film 23 and thermally diffused. As a result, the emitter layer 26 and the collector connection layer 27 are formed in the n-type.

As described above, the vertical bipolar transistor is formed with the epitaxial layer 3 as the collector region. In FIG. 5 (c), each portion of the polycrystalline silicon film 23 which also serves as an electrode and a wiring for the bipolar transistor is shown in the form of terminals for the collector C, the emitter E and the base B for the sake of convenience. Has been done.

[Problems to be solved by the invention]

In the above-mentioned conventional technique, the electrodes and the wiring pattern are formed by selective oxidation of the polycrystalline silicon film before completion of the diffusion of the semiconductor layer into the epitaxial layer, and the connection between the electrode and the semiconductor layer is formed by a so-called self-alignment method. Since it can be achieved, it is easy to miniaturize the pattern of the semiconductor layer, the electrode and the polycrystalline silicon film for wiring, and thus the required chip area can be considerably reduced, but the number of steps, especially the number of photo processes is considerably large, which is troublesome to manufacture. There is a problem that it is easy to take and the effect of reducing the chip area is not always sufficient.

That is, as can be seen from FIG. 5, the first patterning for the oxide film 21 and the second patterning for the mask M in FIG. 5A, the silicon nitride film 24 in FIG.
Separate photomasks are required for the third patterning for the silicon nitride film and the fourth patterning for the silicon nitride film 24 in FIG. 3C, and therefore, at least four photoprocesses are required to form the bipolar transistor. You will need it.

Further, a selective oxide film for separating the polycrystalline silicon films for electrodes and wiring from each other, for example, a selective oxide film 25 between the polycrystalline silicon films 23 for the base B and the emitter E in FIG. Since a certain minimum lateral dimension is required, the effect of reducing the chip area will be reduced accordingly.
In particular, if a multi-emitter structure is adopted in order to increase the current capacity of the bipolar transistor, this selective oxide film size is repeatedly required, which becomes a bottleneck in reducing the chip area. Also, in a bipolar transistor that requires high-speed operation, a so-called clamp diode is often connected between its collector and base,
If a Zener diode for this purpose is to be built, a window must be formed in the polycrystalline silicon film, which requires more work and requires a larger chip area.

SUMMARY OF THE INVENTION It is an object of the present invention to solve such a problem and provide a vertical bipolar transistor which can be manufactured in an integrated circuit device with a smaller number of steps and within a smaller chip area.

[Means for solving the problem]

According to the present invention, a conductive film formed in a pattern having a semiconductor region having one conductivity type, an opening provided in contact with the surface of the semiconductor region and exposing the semiconductor region, and an opening of the conductive film. Base layer diffused in the other conductivity type so that the peripheral edge part goes under the conductive film from the surface of the semiconductor region of the other part, and from the surface of the semiconductor region of the opening of the conductive film to the narrower and lower side than the base layer. An emitter layer diffused with one conductivity type so as to form an effective base layer on the surface of the junction between the base layer and the emitter layer, and the conductive film is on the lower edge of the base layer. Forming a vertical field effect transistor with an insulating film provided so as to leave a portion in contact with the semiconductor part, and deriving terminals for the collector, base, and emitter from the semiconductor region, the conductive film, and the emitter layer, respectively. Thus it is achieved.

Note that it is preferable to use a polycrystalline silicon film or a silicide film for at least part of the conductive film in the above structure.

Most basically, it is sufficient to form this conductive film in a pattern having the openings described in the above configuration. For example, a frame-shaped pattern having a plurality of elongated openings depending on the current capacity of the bipolar transistor, In practice, it is advantageous to form a fork-shaped pattern having a plurality of elongated openings between the legs, a narrow opening or a collective pattern in which a plurality of strip-shaped conductive film portions are arranged at intervals.

Further, as the insulating film in the above structure, an oxide film or a silicon nitride film grown by a CVD method or the like can be appropriately used if necessary, but the surface of a conductive film such as a polycrystalline silicon film is oxidized. The use of the obtained oxide film is most advantageous in reducing the number of photo processes during manufacturing.

Furthermore, the structure in which an impurity diffusion layer of the same conductivity type as the base layer is shallowly provided on the surface of the semiconductor region under the electrode film, enhances the vertical transistor effect by using only the lower portion of the emitter layer in the base layer as an effective base region, Moreover, it is advantageous in ensuring the connection of the conductive film from which the base terminal is led out to the base layer.

[Action]

As in the above structure, in the present invention, the conductive film is formed in a pattern having an opening, and the base layer and the emitter layer can be diffused from the surface of the semiconductor region exposed in the opening using the conductive film as a mask. No photo process is required for both.

Further, the conductive film is provided in contact with the surface of the semiconductor region, and the base layer is diffused under the peripheral region so that the conductive film is conductively connected to the peripheral region of the base layer. In addition to its role as a diffusion mask, it is also used as a base layer electrode film or wiring film.

Furthermore, the insulating film in the present invention need only be provided so as to cover the surface portion of the junction between the base layer and the emitter layer, and therefore the chip area is not eaten as in the conventional selective oxide film.

As described above, according to the configuration of the present invention, the photoprocess for the base layer and the emitter layer can be omitted, and the chip area required for the insulating film can be reduced to the minimum to solve the above-mentioned problems.

〔Example〕

Hereinafter, some embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a cross-sectional view and a top view of a first reference example of a vertical bipolar transistor for an integrated circuit device, and FIG. 2 shows a cross-sectional view of each of the main manufacturing steps thereof.

In FIG. 1A, the n-type semiconductor region 3 constituting the collector region in this example is an epitaxial layer grown on a p-type substrate 1 in which an n-type buried layer 2 is diffused, In this example, the n-type collector connection layer 4 reaching the buried layer 2 from its surface is diffused in order to reduce the collector resistance as much as possible. However, the collector connection layer 4 can be omitted as appropriate.

The conductive film 5 is a polycrystalline silicon film provided in contact with the surface of the semiconductor region 1 in this example, and is formed in a frame-shaped pattern having four elongated openings W in this example as shown in FIG. 1B. To be done. However, this pattern can be formed into, for example, a fork-shaped pattern having five legs or an aggregate pattern composed of five strip-shaped conductive film portions.

In this example, the conductive film 5 is used to form an electrode film for the collector terminal C that is in conductive contact with the buried layer 4. This collector electrode film may be formed of aluminum or the like, like the emitter electrode film described later.

The conductive film 5 is formed in a pattern having a plurality of openings W as described above in order to increase the current capacity of the bipolar transistor, and the p-type base layer 6 and the n-type epitaxial layer 7 are provided with these openings W. It is formed by diffusion using the conductive film 5 as a mask from the surface of the semiconductor region 3 exposed inside. The base layer 6 is diffused so that the peripheral edge portion thereof digs into the lower side of the conductive film 5 and is connected to the conductive film 5, and the emitter layer 7 is diffused narrower and shallower than that. The effective base layer is formed by the lower part of this emitter layer 7 of the base layer 6.

In this example, the insulating film 8 is formed of a polycrystalline silicon oxide film for the conductive film 5 and covers the surface portion of the junction between the base layer 6 and the emitter layer 7, provided that the contact portion of the conductive film 5 with the base layer 6 is in contact. It is provided to leave. This procedure will be described later with reference to FIG.

As can be seen from these, the conductive film 5 serves as an electrode film for the base layer 6, from which the base terminal B is led out or a wiring film therefor is extended as shown in FIG. In order to lead out the emitter terminal E from the layer 7, an electrode film 10 made of aluminum or the like, which is in conductive contact with the emitter layer 7 in each opening W, is provided in this example in a fork-shaped pattern as shown. The emitter electrode film 10 is insulated from the conductive film 5 by the insulating film 8 as shown in the figure.

The bipolar transistor having the above structure is a vertical transistor in which the lower portion of the emitter layer 7 of the base layer 6 is used as an effective base layer, and a plurality of base layers 6 and emitter layers 7 of the same shape are formed as in this embodiment. By arranging them close to each other, the total peripheral length of the emitter layer formed in the small chip area is increased to increase the current capacity, and the depletion layer DL is formed from each base layer 6 when the reverse voltage is applied as shown in the figure. The withstand voltage value can be increased by extending the semiconductor region 1 in a shape connected to each other.

Next, the manufacturing process will be described with reference to FIG. FIG. 3A shows a state in which the conductive film 5 is formed. p-type substrate 1
For example, 10 ¹⁵ atoms / cm ³ of boron-doped one is used, and 10 ²⁰ atoms / cm ³ is used for the n-type buried layer 2 within a predetermined range.
After diffusing antimony or the like at a high surface concentration of about 10 μm, a highly resistive n-type epitaxial layer doped with phosphorus at a relatively low concentration of, for example, 10 ¹⁵ atoms / cm ³ is grown to a thickness of, for example, 6 μm and integrated. The semiconductor region 3 in which the circuit should be built,
If necessary, a p-type separation layer (not shown) is diffused from the surface thereof at a boron concentration of about 10 ¹⁹ atoms / cm ³ until reaching the substrate 1, and junction separation is performed for each collector region. When the collector connection layer 4 is provided as in this example, n-type impurities such as phosphorus are added to the substrate.
The surface concentration of about ¹⁹ atoms / cm ^{3 is} diffused until the buried layer 2 is reached.

Next, in this example, for the conductive film 5, polycrystalline silicon is grown over the semiconductor region 1 to a thickness of, for example, 0.5 μm by a CVD method or the like, and is photo-etched to form a first film.
This is patterned as shown in FIG. 2 (a) by patterning the planar shape of FIG.

As a result, since the above-mentioned opening W for forming the base layer and the emitter layer is formed in the conductive film 5, the subsequent second
In the steps of FIGS. (B) and (c), using the conductive film 5 and the photoresist film M as a mask, for example, arsenic As for the emitter layer and the base layer for the base layer are exposed on the surface of the semiconductor region 1 exposed in the opening W. Boron B is ion-implanted into each. FIG.
Arsenic As ion implantation is performed with an acceleration voltage of 50 kV and a dose of 4
Under the condition of x10 ¹⁵ atoms / cm ² , the ion implantation of boron B shown in FIG. 7C is performed, for example, with an acceleration voltage of 30 kV and a dose of 2 × 10 ¹⁴ atoms / cm ^2.
It is carried out under each condition.

In the process of FIG. 2D in this reference example, the conductive film 5 is oxidized to form the insulating film 8 made of an oxide film, and at the same time,
Arsenic ion-implanted in the previous steps (b) and (c) of FIG.
The base layer 6 and the emitter layer 7 are formed by thermally diffusing As and boron B.
Build in. At this time, the surface portion of the junction between the base layer 6 and the emitter layer 7 is covered with the insulating film 8, and at the same time, the base layer 6 also digs into the lower side of the electrode film 5 to be diffused.
To be connected.

In order to satisfy such conditions, the heating temperature and the oxygen content of the atmosphere can be controlled. For example, the insulating film 8 is formed to a thickness of about 0.2 μm by heating at 950 ° C. for 30 minutes, and at the same time, the base layer 6 is formed. Is about 0.5 μm and the emitter layer 7 is 0.2
It suffices if each is made to a depth of about μm. However, in some cases, it is desired to set the diffusion depth of the base layer and the emitter layer independently of the thickness of the insulating film 8. Therefore, for example, the following steps can be performed in addition to the above.

(A) After ion implantation of arsenic in FIG. 2 (b), FIG.
Before the boron ion implantation, the step of slightly etching the conductive film 5 is inserted.

(B) In FIG. 2 (d), first, the conductive film 5 is oxidized in a strong oxidizing atmosphere to form the insulating film 8, and then the ion-implanted impurities are heated in FIGS. 2 (b) and (c). A base layer and an emitter layer are formed by diffusion.

(C) In FIG. 2 (d), first, the ion-implanted impurities in FIGS. 2 (b) and (c) are thermally diffused to form a base layer and an emitter layer, and then the conductive film 5 is slightly etched. , CV
The insulating film 8 is grown by the D method or the like.

In addition, the ion implantation of arsenic in FIG.
It is also possible to replace the boron ion implantation described above. Of course, also in this case, formation of the insulating film 8 and formation of the base layer 6 and the emitter layer 7 by impurity thermal diffusion are simultaneously performed in the step of FIG. Although it can be carried out, the following steps can be taken as a modification thereof.

(D) After ion implantation of boron, formation of the insulating film 8 by oxidation of the conductive film 5 and formation of the base layer 6 by thermal diffusion of boron are carried out simultaneously, and after ion implantation of arsenic or phosphorus, this is thermally diffused. Then, the emitter layer 7 is formed.

In any of these aspects, by appropriately selecting the process conditions depending on the aspect, the surface portion of the junction between the base layer and the emitter layer, which is a feature of the present invention, is covered with the insulating film, and the conductive film is formed. It is possible to ensure that the portion that contacts the peripheral portion of the lower base layer is left.

After the step shown in FIG. 2 (d), the electrode film 10 is provided to complete the state shown in FIG.

FIG. 3 is a sectional view showing a second reference example of the present invention in a completed state. In this reference example, a p-type impurity such as boron having the same conductivity type as that of the base layer 6 is heavily doped in advance in a predetermined range on the surface of the semiconductor region 1 before the conductive film 5 is provided by an ion implantation method or the like. Different from the embodiment. As a result, when the base layer 6 and the emitter layer 7 are formed in the opening of the conductive film 5, a base connection layer continuous with the base layer 6 as shown in the figure.
6a is formed below the conductive film 5.

In this reference example, the number of ion implantation steps is increased by one, but as can be easily understood, the connection between the base layer 6 and the conductive film 5 becomes more reliable, and the active region of the base layer 6 is connected to the emitter layer 7.
The characteristics such as current amplification factor as a vertical transistor can be stabilized strictly by limiting only to the lower side part, and the process such as temperature at the time of forming the insulating film and forming the base layer and the emitter layer. The selection of conditions can be made easier than in the previous reference example. In this example, the collector terminal is led out through the electrode film 11 made of aluminum or the like on the oxide film 9 as shown in the figure.

FIG. 4 shows a first embodiment of the present invention in which a Schottky diode is formed in a bipolar transistor by utilizing silicide for the conductive film 5. FIG.
As shown in the cross section of FIG. 1, unlike the reference example of FIG. 1 in that a silicide film 5a is provided at a portion of the conductive film 5 that contacts the semiconductor region 1, a silicide such as platinum, tungsten or molybdenum is used for the silicide film 5a. May be deposited very thinly by a sputtering method or the like, and polycrystalline silicon may be grown thereon to form the conductive film 5. Of course, the conductive film 5 may be composed of only a silicide film.

As can be seen from the figure, this silicide film 5a forms a Schottky junction with the semiconductor region 1 which is the collector region,
Moreover, since it is connected to the base layer 6, the Schottky diode SD is formed between the collector and the base of the bipolar transistor as shown in FIG. 2 (b). As is well known, this Schottky diode SD has the effect of extracting the charge that is likely to be accumulated in the base to the collector side and increasing the operating speed of the bipolar transistor.

When the present invention is applied to a multi-emitter structure as shown in FIG.
A bipolar transistor having a large current capacity of A, capable of high-speed operation and small parasitic capacitance can be built in, and its current amplification factor is 100 or more and its withstand voltage is several tens of volts.
Can be easily obtained.

〔The invention's effect〕

As described above, according to the present invention, a conductive film is provided in a pattern having an opening that exposes the semiconductor region in contact with the surface of the semiconductor region having one conductivity type for an integrated circuit device, and the opening of the conductive film is provided. The base layer of the other conductivity type is diffused from the surface of the semiconductor region to the lower side of the conductive film so that the peripheral portion of the emitter layer is narrowed, and the emitter layer of the one conductivity type is narrower than the base layer and below the effective base layer. Is formed so as to diffuse shallower than that, and an insulating film is provided so as to cover the surface part of the junction between the base layer and the emitter layer and leave the part where the conductive film is in contact with the peripheral part of the lower base layer. hand,
The following effects can be obtained by deriving the collector, base and emitter terminals from the semiconductor region, the conductive film and the emitter layer, respectively.

(A) By diffusing the base layer and the emitter layer by the self-alignment method using the conductive film as a mask, the photo process required for them can be omitted and the manufacturing process can be simplified.

(B) It is possible to reduce the required chip by omitting the dimension that required the conventional selective oxide film, and particularly in the case of a bipolar transistor having a multi-emitter structure, the repeating arrangement pitch is reduced to half that of the conventional one. It is possible to build a transistor with a large current capacity in a chip area that is almost halved.

(C) A Schottky diode can be incorporated into a transistor to increase its operating speed without increasing the required chip area.

(D) Since the base terminal can be led out through the conductive film in close proximity to the base layer, a bipolar transistor having a small parasitic capacitance and excellent operating characteristics can be incorporated in an integrated circuit device.

(E) Since the mutual spacing of the emitter layers can be reduced in the case of a multi-emitter structure, when the reverse voltage is applied, the depletion layer can be smoothly spread in the semiconductor region with a small curvature shape to increase the breakdown voltage value. it can.

As described above, the present invention has a remarkable effect that a bipolar transistor having excellent characteristics can be formed in a small chip area by a simple process.

[Brief description of the drawings]

1 to 4 relate to the present invention. FIG. 1 is a sectional view and a top view of a first reference example of a vertical bipolar transistor for an integrated circuit device according to the present invention (the same FIG. 2) is a cross-sectional view showing the manufacturing method of this reference example in the state of each main step, and FIG. 3 is a cross-sectional view of the second reference example. FIG. 4 is a sectional view of the first embodiment. FIG. 5 is a sectional view showing the structure and manufacturing process of a conventional bipolar transistor of the same kind in a manner similar to FIG. In these figures, 1: substrate of integrated circuit device, 2: buried layer, 3: semiconductor region or epitaxial layer, 4: collector connection layer, 5: conductive film, 5
a: silicide film, 6: base layer, 6a: base connection layer, 7: emitter layer, 8: insulating film, 9: oxide film, 10, 11: electrode film, 21: oxide film, 22: base layer, 23: Polycrystalline silicon film, 24: Silicon nitride film, 25: Selective oxide film, 26: Emitter layer, 27: Collector connection layer, As: Arsenic, B: Boron or base terminal, C: Collector terminal, DL: Depletion layer, E : Emitter terminal, M: Mask or photoresist film, SD: Schottky diode,
W: The opening.

Claims (2)

(57) [Claims] 1. A semiconductor region for an integrated circuit device, the semiconductor region having a flat surface having one conductivity type, and an opening formed in contact with the surface of the semiconductor region to expose the semiconductor region. A conductive film, a base layer diffused in the other conductivity type so that a peripheral edge portion goes under the conductive film from the surface of the semiconductor region of the opening of the conductive film, and the opening of the conductive film An emitter layer narrower than the surface of the semiconductor region and shallower than the base layer so as to form an effective base layer and diffused in one conductivity type, and the base layer formed on the surface of the semiconductor region. An insulating film provided so as to cover the surface of the junction between the emitter layer and the emitter layer and leave a portion of the conductive film in contact with the peripheral edge of the base layer. It has Tokibaria bonding, the semiconductor region and the conductive layer and the integrated circuit device for vertical bipolar transistor, wherein the terminal for each collector and base and emitter of the emitter layer is derived. 2. The vertical bipolar transistor for an integrated circuit device according to claim 1, wherein the conductive film is made of silicide.