JPS63157467A - Hetero junction bipolar transistor - Google Patents

Abstract

PURPOSE:To manufacture pertinent element for microwave by a method wherein, within a hetero junction bipolar transistor wherein multiple emitter electrodes and base electrodes are arranged in pairs, emitter wirings and base wiring are made to be of a cross wiring structure. CONSTITUTION:An n<+> type GaAs 2, an n-type GaAs 3, a p-type GaAs 4 are epitaxially formed on a semiinsulating GaAs substrate 1 and then successively an n-type Al GaAs emitter layer 5 and an n<+> GaAs layer 6 in wide forbidden band width are laminated. First the n type collector layer 3 is divided by mesa etching process to division-form an n layer 6 and n<+> layer 7 to be pairs of emitter layers on the p base layers 4 respectivley formed. Second, base electrodes 9 and collector electrodes 8 are arranged in a manner of comb- engagement with the emitter electrodes 7. Third, the electrodes 7, 8 and 9 are respectively connected to wirings 10, 11 and 12. In such a constitution, the parasitic capacity, parasitic inductance and resistance of wirings can be made sufficiently smaller to manufacture excellent device as an element for microwave.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] <Industrial Application Field> The present invention relates to a heterojunction bipolar transistor using a semiconductor material having a larger bandgap in the emitter region than in the base region.

(Prior Art) It is known that a heterojunction bipolar transistor in which the emitter region is made of a semiconductor material with a larger bandgap than the base region has many advantages over a homojunction bipolar transistor. These advantages are summarized as follows.

(2) Since carrier injection from the base to the emitter can be suppressed, high emitter injection efficiency can be obtained even if the impurity concentration in the emitter region and the impurity concentration in the base region are set independently.

(2) As a result of (2), the impurity concentration in the base region can be increased, and the base resistance can therefore be lowered while reducing the base layer thickness.

■ Since the impurity concentration in the emitter region can be lowered, the emitter junction volume can be made smaller.

Because of these advantages, heterojunction bibolar transistors have excellent high frequency characteristics and switching characteristics, and are considered promising as microwave transistors and high-speed logic transistors. In order to further improve the performance of a heterojunction bipolar transistor as a microwave device, it is desirable to form the device on a semi-insulating substrate.

This is because the capacitance between each region of the element and between the electrode pad and the substrate can be reduced.

However, when constructing a microwave heterojunction bipolar transistor using a semi-insulating substrate, the three-terminal wires of the collector, base, and emitter must all be formed on the substrate surface, making the electrode wiring structure complicated. Become. That is, in a microwave transistor, the emitter electrode and the base electrode are usually divided into a plurality of parts and combined into a tooth shape. For example, in the conventional structure where an n+ type semiconductor substrate is used and a collector electrode is provided on the back surface of the substrate, there are two types of electrodes, an emitter electrode and a base electrode, arranged on the surface of the substrate, so these are divided into multiple electrodes. However, it is easy to connect them in common and provide one emitter electrode pad and one base electrode pad. However, when all three electrodes, the collector, base, and emitter, are arranged on the substrate surface, when the emitter electrode and the base electrode are each divided into multiple pieces and combined,
If the wiring that commonly connects the divided electrodes is formed using only one layer as in the conventional method, the wiring length will be extremely long, and the parasitic capacity, parasitic inductance, and resistance will increase. This impairs the high frequency characteristics of the transistor. In order to avoid long wiring lengths, the emitter and base electrode pads must be divided into multiple parts. This also leads to an increase in parasitic capacitance, which impedes improvement in the performance of the element.

(Problems to be Solved by the Invention) As described above, it is desirable to use a semi-insulating substrate in a heterojunction transistor as a microwave device in order to improve performance; There was a problem in that the electrode wiring became complicated, which hindered high performance.

In view of the above points, an object of the present invention is to provide a heterojunction transistor with improved performance using a semi-insulating substrate.

[Structure of the Invention] (Means for Solving the Problems) A heterojunction transistor according to the present invention includes a first semiconductor layer of a first conductivity type that is divided into a plurality of pieces and formed on a semi-insulating substrate. , comprising a second conductivity type second semiconductor layer serving as a base layer formed on each first semiconductor layer, and a first conductivity type third semiconductor layer dividedly formed on each second semiconductor layer, The first semiconductor layer is used as a collector or an emitter, a plurality of emitter electrodes and a base electrode are each combined in a comb-like shape, and the base electrode is commonly connected to a wiring that commonly connects each of the plurality of emitter electrodes. It is characterized by having a cross-wiring structure with the wiring.

With this kind of configuration, the emitter divided into multiple parts,
Each of the collector and base electrodes can be commonly drawn out to one pad without running long wiring. Therefore, an increase in parasitic inductance and wiring resistance is prevented, and a Peter junction bipolar transistor exhibiting excellent microwave characteristics can be realized.

(Example) The present invention will be explained in detail below.

FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along line AA' of a heterojunction transistor according to an embodiment of the present invention using an AffiGaAs/GaAS system. To manufacture this transistor, it is first necessary to sequentially epitaxially grow semiconductor layers on the semi-insulating GaAS substrate 1. As this epitaxial growth method, for example, a molecular beam epitaxial method (MBE method) or an organic gold wave vapor phase epitaxy method (MOCVD method) may be used. To explain the specific manufacturing conditions in the order of steps, first, an n9 type GaASII layer is formed on the substrate 1, which will become the first collector layer containing a high concentration of Sl.
2. Next, an n-type GaAs layer 3 (first semiconductor layer) which will become a second collector layer is epitaxially grown. Next, p+ type Ga is used as the base region containing, for example, Be as an impurity.
Epitaxially growing an As layer 4 (second semiconductor layer),
Next, there is an n-type AcGaAS layer 5 (third semiconductor layer) which becomes a wide bandgap emitter region containing $1 as an impurity.
, and further n1 type Ga which becomes an n+ type emitter/cap layer.
The AS layer 6 is grown sequentially. For example, n+ type GaASI
! 2 is the impurity concentration 2×1018/, t3. Thickness Lc
zm, and the n-type GaAs layer 3 has an impurity concentration of 1×10”
/cm3. The thickness is 1 μm. p+ type Ga in the base region
The AS layer 4 has an impurity concentration lXl0”/as3.Thickness 20
00 people. The AgGaASI layer 5 serving as the emitter has an impurity concentration of 3x 10''/ctn3.thickness of 1500 layers, and the n1 type GaAS layer 6 serving as the cap layer has an impurity concentration of 5x 10''/ax3. The thickness is assumed to be 1000 people. In this example, AnGaAsWI5 has a he2 composition ratio of 0.
It is set at 3.

The epitaxial wafer thus formed is first subjected to mesa etching to form base and collector contacts, leaving an emitter region. Further, mesa etching is performed until reaching the substrate 1 for element isolation. In this embodiment, the n-type GaAS layer 3 which becomes the collector region is divided into two parts, and the p-type GaAS layer 3 which becomes the base region is formed in each part.
Two n-type AnGaAS layers 6 and two n+-type GaAs layers 17, each serving as two emitter regions, are formed on ff4. After this, collector electrode 8. An emitter terminal 7 and a base electrode 9 are formed. In this embodiment, emitter electrode 7
A total of four base electrodes 9 and three collector electrodes 8 are disposed so as to mesh with each other in a shape of IiIm. And emitter wiring 1 that commonly connects emitter electrodes 7
0, a collector wiring 11 that commonly connects the collector electrodes 8 and a base wiring [1i12 that commonly connects the base electrodes 9] are provided. These wirings are made of, for example, Ti/Pt/A
The base wiring 12 is a two-layer wiring using the three-layer structure of u.
and the emitter arrangement J110 intersect.

Specifically, for example, after the electrode is formed, 5iOzll
A first grade interlayer insulating film is formed, a contact hole is formed in this, and the base wiring 12 and the collector wiring 1 are connected by the 111th wiring.
After that, an interlayer insulating film is formed, a contact hole is formed therein, and an emitter wiring 10 is formed by a second layer wiring that intersects with the base wiring 12.

In this embodiment, the area of the intersection between the emitter interconnection Mio and the base interconnection 12 is small, and the increase in parasitic capacitance caused by this interconnection intersection is small. The parasitic capacitance and parasitic inductance are sufficiently small, and the resistance is also small, compared to the conventional case of forming a wiring that commonly connects the electrodes of three terminals using only one layer of wiring. In fact, as a result of prototyping a microwave heterojunction bipolar transistor with the structure of this example, the cutoff frequency fT
= 20 GHz, maximum frequency fvAx - 400)t
z was obtained. When a class C amplifier was constructed using this element, excellent characteristics such as an output of 1 W and a gain of 5 dB at 15 GHz were obtained.

FIGS. 2(a) and 2(b) are a plan view and a sectional view taken along line AA' of a heterojunction bipolar transistor according to another embodiment of the present invention. In the previous embodiment, the emitter was provided on the top, but in this embodiment, the collector is provided on the top, so-called a collector top structure. On a semi-insulating GaAs substrate 1, an n" type GaAs layer 2 which will become a high concentration emitter layer is grown, and on top of this an n type AnGaAs layer (first semiconductor H) 13 which will become a wide bandgap emitter layer, and then a base layer. ρ1 type GaAsff (second semiconductor layer) 1
4. N-type GaAsl1I (third half, conductor layer) 15 which becomes the collector layer, and n+-type G which becomes the collector/cap layer
The aAs layer 16 is grown sequentially. The n+ type GaAS layer 12 has an impurity concentration of 3×10"/an" and a thickness of 1 μm.
, n! MAff'GaAs1113 has an impurity concentration lXl
0"/as3. Thickness 5000, p+ type GaAS layer 1
4 is an impurity concentration of 1×1019/cttr3. nza100
0 people, n-type GaAS1115 has an impurity concentration of 1×10”/
The n'' GaAs layer 16 has an impurity concentration of 5×101a/α3 and a thickness of 1000 μm.

After forming such an epitaxial wafer, etching is first performed leaving the collector region to form a plurality of divided collector regions a, and then ion implantation is performed for base contact to form the external base layer 17. . After this, two steps of mesa etching are performed: mesa etching to reach the n+ type GaAs layer 2 to divide the n type AJ2 GaAS layer 13, and mesa etching to reach the substrate 1 for element isolation.
Perform etching. Then, a plurality of collector electrodes, a plurality of base electrodes 19, and a plurality of emitter electrodes 20 are formed as shown in the figure. In this embodiment, the base electrode 19
is embedded in the substrate. After forming the interlayer insulating film, the emitter wiring 21 is formed using the first wiring layer.
Then, a collector wiring 22 is formed, an interlayer insulating film is formed again, and a base wiring 23 is formed using a second wiring layer. Similarly to the previous embodiment, in this embodiment as well, the base wiring 23 and the emitter wiring 21 are intersecting wirings.

The device of this example also exhibited excellent performance almost on the same level as the device of the previous example.

The present invention is not limited to the above embodiments.

For example, GaAS is used as a semiconductor material constituting a heterojunction.
Although the A2 composition ratio of AffiGaAs was set to 0.3, other composition ratios may be used as necessary. In addition, as a combination of semiconductor materials constituting a heterojunction, GaAS, InGaAs, AffiGaAs
and I nGaAS, InP and InGaAs, lnP and I
Even when using nGaAsP, GaAs and Ge, etc.
The present invention is effective.

[Effects of the Invention] As described above, according to the present invention, in a heterojunction bipolar transistor having a structure in which a plurality of emitter electrodes and a plurality of base electrodes are arranged in combination, the emitter wiring and the base wiring are arranged in a cross wiring structure. By doing so, a heterojunction transistor excellent as a microwave device can be obtained.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are a plan view and a sectional view taken along line AA' of a heterojunction transistor according to one embodiment of the present invention, and FIGS. FIG. 1 is a plan view and a cross-sectional view taken along line AA' of a telojunction bipolar transistor. 1... Semi-insulating GaAS substrate, 2... n+ type GaA
S layer, 3-n-type GaAS layer (collector region), 4-o+
type GaAS layer (base region), 5...n type AffiG
aAs layer (emitter region), 6... emitter cap layer, 7... emitter electrode, 8... collector electrode, 9...
...Base electrode, 10...Emitter wiring, 11...
Collector interconnection, 12...Base interconnection, 13...n-type AnGaAs layer (emitter region), 14-...p+ type GaAs1 (base region), 15.n-type GaA9m
(:l collector region), 16-n+ type GaAS layer (collector/cap layer), 17... external base region, 18...
...Collector electrode, 19...Base electrode, 20...
Emitter electrode, 21... Emitter wiring, 22... Collector wiring, 23... Base wiring. Applicant's agent Patent attorney Takehiko Suzue No. 1

Claims (1)

[Claims] A first plate formed on a semi-insulating substrate by being divided into a plurality of pieces.
A first semiconductor layer of a conductivity type, a second semiconductor layer of a second conductivity type formed on each first semiconductor layer, and a first conductivity type divided into a plurality of pieces formed on each second semiconductor layer. In a heterojunction bipolar transistor comprising a third semiconductor layer, the first semiconductor layer is the collector or emitter, and a heterojunction is used as the emitter-base junction, a plurality of emitter electrodes and base electrodes are alternately arranged. is,
A heterojunction bipolar transistor characterized in that the wiring that commonly connects these emitter electrodes and the wiring that commonly connects the base electrodes intersect.