JPS58142573A - Semiconductor integrated circuit and preparation thereof - Google Patents

Abstract

PURPOSE:To obtain a high performance IC apparatus through formation of base and emitter by using a metal silicide for leadout of base in view of reducing a resistance and by forming base and emitter on the self-alignment basis utilizing growth of silicides. CONSTITUTION:A buried collector 2 and a epitaxial layer 3 are stacked on an Si substrate 1, forming a collector leadout layer 5 and a base layer 6. Layers SiO2 4, Si3N4 13 are stacked and window is opened selectively and then an Mo 16 is also stacked thereon. An MoSi 17 is formed by the heat processing under the N2 ambient under the control of temperature and time and the length of eaves part 18 is set to the desired value within the range of 0.5-1.5mum. Then, the Mo 16 is removed by phosphoric acid and an SiO2 19 is formed on the MoSi 17 through high temperature heat processing in the O2 ambient. After forming an emitter layer 7, the base, emitter and collector electrodes 10-12 are attached. The space between base and emitter is kept at 1mum or less in such a structure and moreover since the resistance of MoSi 17 is low, an external resistance of base can be reduced up to about 1/5 of the ordinary one, thus extremely improving the high frequency characteristic.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a highly integrated, high-performance semiconductor integrated circuit in which the emitter and base of a bipolar transistor are formed in a self-aligned manner, and a method for manufacturing the same.

Recent bipolar integrated circuits are required to have smaller elements and higher performance transistors. However, when trying to miniaturize a bipolar transistor with a conventional structure, the spacing between the emitter and base contacts is limited by the alignment accuracy of the photomask, so the transistor dimensions cannot be reduced very much, and the external base resistance increases, resulting in poor high-frequency characteristics. However, problems such as power failure occurred, which hindered the high integration and performance of bipolar integrated circuits.

In order to solve the above problems, a structure has been proposed in which the distance between the base and the emitter is narrowed using self-line technology. An example of this is shown in FIG.

FIG. 1 is a cross-sectional view showing the main structure of a conventional bipolar integrated circuit. In the figure, 1 is a silicon substrate, 2 is a buried layer, 6 is a silicon epitaxial layer, 4 is a silicon oxide film, 5 is a diffusion layer for taking out the collector, 6 is a base diffusion layer, 7 is an emitter diffusion layer 8 is a multilayer a crystalline silicon layer, 9 a silicon oxide film, 10 a base electrode, 11 an emitter electrode,
12 is a collector electrode.

Since the above structure is well known, a description of its manufacturing method will be omitted. However, since the polycrystalline silicon layer 8 is used for drawing out the base, ■ the drawing resistance of the base is high; and ■ the base and emitter are connected to a self-aligned line. It has drawbacks such as requiring a complicated process to form it.

The present invention was made in order to eliminate these drawbacks of the conventional technology, and aims to reduce the resistance by using a metal silicide layer in the lead-out of the base, and by using silicide growth to easily connect the base and emitter with a self-alignment line. The present invention provides a semiconductor integrated circuit with excellent characteristics. Another object of the present invention is to form a base electrode of a transistor on an isolation region.
An object of the present invention is to provide a semiconductor integrated circuit that reduces the area of an active region and improves the performance of a transistor, and a method for manufacturing the same.

Below, the present invention will be explained in detail by way of examples.

FIGS. 2(a) to 2(f) show the first part of the semiconductor integrated circuit of the present invention.
FIG.
1 shows the structure of a semiconductor integrated circuit according to the present invention.

The manufacturing process will be explained in accordance with the order (a) to (f) in the figures. In the figures, the same reference numerals as those mentioned above indicate the same or equivalent parts.

(a): A buried layer (collector buried layer) 2 was provided on the surface of a silicon substrate 1, and a silicon epitaxial layer 3 (layer thickness: 1.5 μm, for example) was formed thereon. The surface was thermally oxidized to form a silicon oxide film 4. Next, a diffusion layer 5 for taking out the collector is formed, and then a base diffusion layer 6 is formed by ion implantation, and a CV
A silicon nitride film (insulating film) 13 (film thickness: 1000×, for example) was formed by the D method. Note that a KP8G film may be formed instead of the silicon nitride film.

(b) Second, the silicon nitride film 16 and silicon oxide film 4 around the region 14 where the emitter is to be formed were etched using a normal photoetching technique to form a hole 15 for a base contact.

(C): Next, a molybdenum film 16 (the thickness of the film is, for example, 3000 Å) is formed on the entire surface by vapor deposition, sputtering, etc., and then heat treatment is performed at 400 to 1000° C. in a nitrogen atmosphere. By this heat treatment, the base contact hole 15
The upper molybdenum film and silicon were reacted to form a molybdenum silicide film 17. At this time, the molybdenum silicide film 17 was also grown in the lateral direction of the molybdenum film 16 so as to form the eaves 18. The amount of molybdenum silicide eaves is controlled by the temperature and time of the heat treatment in the nitrogen atmosphere, for example, 800°C, 60°C.
It becomes about 0.5 μm in minutes, and about 1 μm in 30 minutes at 900°C. For element formation, the length of the eaves 18 is 0.5 to 1.5 μm.
The above heat treatment conditions are set so that the desired value is obtained within the range of .

(d): Next, the molybdenum film 16 is removed with phosphoric acid, and then heated at 600 to 1100°C in an oxygen atmosphere.
A heat treatment is performed for about one hour to form a silicon oxide film 19 on the molybdenum silicide film 17. At this time, the thickness of the silicon oxide film 19 (for example, 4000 Å) needs to be thicker than the silicon oxide film 4.

(e): Next, the surface of the silicon nitride film 13 other than the region 14 where the emitter (emitter diffusion layer 7) is to be formed is covered with a resist, and the silicon nitride film 13 on the emitter region is removed by etching. At this time, since the silicon oxide film 19 is a mask donal, an emitter hole is formed at a predetermined distance from the base contact hole 15 (determined by the thickness of the molybdenum silicide eaves 18 and the silicon oxide film 19) in a self-aligned manner. Furthermore, the silicon oxide film is etched to expose the silicon surface of a portion where an emitter will be formed, and an emitter diffusion layer 7 is formed by ion implantation or thermal diffusion.

(f)=Next, a collector contact hole is made on the diffusion layer 5 for extracting the collector using a photoetching technique, and a base contact hole is further made on the silicon oxide film 19 to form an electrode, and the base electrode 10. Emitter electrode 11. A collector electrode 12 is provided to complete the transistor.

The bipolar transistor of the present invention manufactured in this way has a small distance between the base contact and the emitter (1
1zm or less), and because the electrical resistance of the silicide layer (molybdenum silicide film 17) is low, the external resistance of the base (rbb/) is reduced to 1/3 to 115 of that of the conventional structure, and the high frequency characteristics are significantly improved. .

Although a molybdenum film is used as the silicide electrode material in this embodiment, it is of course possible to use a transition metal material such as tungsten in the present invention.

Figures 5(-1) to (e) are cross-sectional views showing the second embodiment of the semiconductor integrated circuit of the present invention in the order of manufacturing steps;
) shows the structure of the semiconductor integrated circuit according to the present invention.

The bipolar transistor of this embodiment has a base electrode formed on an isolation region, thereby achieving higher performance and higher integration than the transistor described in the first embodiment (FIG. 2).

The manufacturing process will be explained in accordance with the order of the figures. In addition, the first
The explanation of steps similar to those explained in the embodiment will be simplified.

(a): An n-type collector buried layer 2 is provided on the surface of a p-type silicon substrate 1, a silicon epitaxial layer 6 is formed thereon, and a silicon oxide film 4 is formed by thermally oxidizing the surface. Furthermore, a silicon nitride film 13 is formed thereon by the CVD method. Then, the silicon nitride film 13 and the silicon oxide film 4 are patterned using a normal photoetching method to form a pattern for an iso-rayon.

(b): Next, the exposed epitaxial layer 3 is etched to approximately 1/2 the thickness of the epitaxial layer 6.
form a groove with a depth of Then, boron is introduced into the bottom of the trench by ion implantation to prevent channel generation, and after annealing, selective oxidation is performed using the silicon nitride film 16 as a mask to form a silicon oxide layer 20 for isolating. Form. After removing the surface pattern and forming a new silicon oxide film 4, a diffusion layer (CN diffusion layer) 5 for extracting the collector is formed, and boron ions are implanted to form the base. A diffusion layer 6 is formed.

(C): Next, a silicon nitride film 21 is formed on the entire surface by CVD method, and a polycrystalline silicon layer 22 is further formed thereon. Then, the polycrystalline silicon layer 22 is left only in the area where the base electrode is taken out, and the other parts are removed by etching. Next, a region (
The nitride 7'J contact film 21 and the silicon oxide film 4' of the base contact 11L15) are removed by photoetching.

(d) Second, after forming a molybdenum film on the entire surface, heat treatment is performed in a nitrogen atmosphere to cause the molybdenum film on the base contact hole to react with 7lico/, and at the same time, the polycrystalline silicon layer 22 and the molybdenum film are reacted. A molybdenum silicide film 17 is formed by the reaction. Next, after removing the remaining molybdenum film 2*, heat treatment is performed in an oxygen atmosphere to form a silicon oxide film 1 on the molybdenum dot side film 17.
form 9.

(e): Next, an emitter diffusion layer 7 is formed in the same manner as in the first embodiment, and a contact hole for a base electrode and a contact hole for a collector electrode are formed.
The base electrode io, the emitter electrode 11. A collector electrode 12 is provided to complete the transistor.

The bipolar transistor of the present invention manufactured in this way has the advantage that the distance between the base and the emitter is narrow, and the area of the base region (base diffusion layer 6) is small. This is because the base electrode 10 is formed on the isolation region (oxidized 7937 layer 2-0), so the base contact hole around the emitter can be made smaller, and the area of the base region is smaller. Base-collector junction capacitance (CT) of a transistor.

) became smaller, and the high-frequency characteristics of the transistor were significantly improved.

As explained above, the semiconductor integrated circuit of the present invention uses a metal silicide film for the lead-out of the base, and has various advantages compared to silicon (115~/1o), and
Since the manufacturing method uses silicide growth to form the base and emitter in a self-aligned manner, it has the advantage of simplifying the process.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the main part configuration of a conventional bipolar integrated circuit, FIGS. 2(a) to (f), and FIGS. 6(8) to (e).
) are cross-sectional views showing embodiments of the semiconductor integrated circuit of the present invention in the order of manufacturing steps. 1...Silicon substrate 2...Buried layer 6...Silicon epitaxial layer 4.4', 9.19...Silicon oxide film 5...Diffusion layer for collector extension 6...Base diffusion layer 7... Emitter diffusion layer 8
．． 22... Polycrystalline silicon layer 10... Base electrode 11... Emitter electrode 1
2...Collector electrode 13.21...Nilicon nitride film 16...Molybdenum film 17...Molybdenum silicide film 18...Eaves 20...Silicon oxide layer Patent attorney Junnosuke Nakamura IP1 Figure 1- Figure 2 Figure 2

Claims (2)

[Claims] (1) Take out the base electrode using a metal silicide film from a place around the emitter diffusion layer at a predetermined distance of 1.5 μm or less from the emitter diffusion layer, and insulate the base electrode and emitter electrode from the metal silicide film. A bipolar semiconductor integrated circuit characterized by being formed using an oxide film. (2) A method for manufacturing a bipolar semiconductor integrated circuit including the following steps. (2) A first step that includes a step of covering the silicon substrate surface with a silicon oxide film and then with an insulating film such as a silicon nitride film or a dPsQ film. ■ A step of removing the above insulating film and silicon oxide film around the emitter region and opening holes. ■ A step of forming a transition metal film on the above insulating film and on the entire surface of the substrate including the openings. A step of causing the transition metal film and the silicon substrate to react by O heat treatment to form a metal silicide film on and around the opening. ■ A step of oxidizing the metal silicide film to form a silicon oxide film on the surface. (2) Using the silicon oxide film formed in step (2) above as a mask, the insulating film and silicon oxide film on the emitter region are removed to form an emitter hole. (b) The first step is a step of covering the silicon substrate surface with a silicon oxide film, and then covering it with an insulating film such as a silicon nitride film or a PSG film, and forming a polycrystalline silicon layer on the insulating film; 3. The method of manufacturing a bipolar semiconductor integrated circuit according to claim 2, further comprising the step of leaving the polycrystalline silicon layer only in the region where the electrodes are taken out.