JPH02291120A - Manufacture of gaas field-effect transistor - Google Patents

Abstract

PURPOSE:To reduce a contact resistance of a GaAs field-effect transistor in which an N<+> layer has been formed and to increase a mutual conductance by a method wherein, after ions of a group VI element have been implanted, a reactive ion etching treatment of the surface of an ion-implanted region is executed. CONSTITUTION:Si<+> ions 21 are implanted selectively into one surface of a semi- insulating GaAs crystal substrate 10; a first ion-implanted region 51 is formed. Then, a W5Si3 film 31 is applied to a gate electrode formation region of the first ion-implanted region; an SiO2 film 41 is applied selectively to its side faces. Then, S ions 23 are implanted selectively; a second ion-implanted region 52 is formed. Then, a reactive ion etching operation 24 of the second ion-implanted region is executed; a damage region 25 is formed. Lastly, an SiO2 film 42 is applied; it is heat-treated at 800 to 830 deg.C; an n-type active layer 13 and an N<+> layer 14 are formed; a source electrode 32 and a drain electrode 33 are formed. At the N<+> layer which has been manufactured by this method, an electron concentration is distributed highest at a crystal surface; the surface concentration at this time becomes about five times as high as that according to a conventional manufacturing method.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing an electronic device having an N+ layer with high electron concentration;
In particular, the present invention relates to a method for manufacturing a GaAs field effect transistor having an ohmic contact N+ layer with high electron concentration and low resistance.

[Conventional technology]

Conventionally, this type of GaAs field effect transistor has a resistivity of 10'Ωc as shown in FIGS. 3(a) to 3(e).
The Si concentration is 1017 cm by S1+ ion implantation 21 on the surface of the semi-insulating GaAs crystal substrate 10 with a diameter of 10 cm or more.
-3 A first ion implantation layer 51 is selectively formed, a Schottky metal layer 31 of Wssi3, for example, is formed in the gate electrode formation region on the surface of the first ion implantation layer 51, and further this The sidewall of the Schottky metal layer 31 has a width of 0.
．． After depositing a 2 μm Si02 film 41, a second ion-implanted layer 5 is formed which exposes a high dose of Si+ using the Schottky metal layer 31 and the Sin2 film 41 as an implantation mask.
Ion implantation 22 is performed on the surface of the semi-insulating GaAs crystal substrate 10 containing 1, and the entire surface is further covered with a SiO2 film 42.
C. for 20 minutes to form an N+ layer 12 for ohmic contact with the active layer 13 and a high electron concentration.
It was manufactured by forming an Au-based source electrode 32 on the + layer 12 and forming a drain electrode 33 on the other side.

[Problem to be solved by the invention]

The conventional manufacturing method of the GaAs field effect transistor described above has the disadvantage that the contact resistance of the ohmic contact is large because the N+ layer is formed by Si+ ion implantation. 800 to 830 for activation of ion-implanted Si+
Although a heat treatment in the range of °C is optimal, the maximum surface electron concentration of the resulting N+ layer is 4 x 10 17crrV in height.
”The contact resistance of the source and drain ohmic electrodes formed on this solid N+ layer I2 is at most 0.4Ω.
/ mm. As a result, G a
A s transconductance g obtained in a field effect transistor. is 80 m when the gate length is 1.0 μm.
It is about S/mm.

[Means to solve the problem]

The manufacturing method of the GaAs field effect transistor of the present invention includes a first ion implantation step using a Si element to form an N-type active layer, and a step of implanting Group 6 elements of S, Se, and Te to form an N+ layer. The method includes a second ion implantation step, a step of selectively performing reactive ion etching after the second ion implantation step, and a step of further performing heat treatment at 800° C. to 830° C.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(f) are longitudinal sectional views of an embodiment of the present invention. As shown in FIG. 3A, one surface of the semi-insulating GaAs crystal substrate 10 is exposed to an accelerating voltage of 100 keV and a dose of 100 keV.
A first ion implantation region 51 is formed by selectively implanting 81+ ions at t3×10”cm−2.

Next, in the gate electrode formation region of the first ion implantation region, there is a W5S13 film 3l, which is a Schottky metal, and an S
The state in which the iO2 film 41 is selectively deposited is shown in FIG. 2(b). In the same figure (c), the acceleration voltage is 5okeV, the dose is 2
．． A second ion implantation region 52 is formed by selectively implanting S ions 23 at 5×10” cm −2 .At this time, the thickness of the W5Si3 film 34 and the SIO2 film 41 is set to the same value as that during the S ion implantation. A value (approximately 3000) is required so that S does not reach directly under the WsSi3 film or SiO2 film.Next, reactive ion etching 24 is performed at a gas pressure of 0.2.
P a and applied power of 100 W are applied to the second ion implantation region for 5 minutes.

As a result, a damaged region 25 caused by the reactive ion etching is shown in FIG. 2(d). Finally, in the same figure (e), a SiCh film 42 with a thickness of 3000 was deposited and heated to 830°C.
Heat treatment is performed for 20 minutes to form the n-type active layer 13 and N+
FIG. 3(f) shows the formation of the layer 14, and the formation of the source electrode 32 and drain electrode 33, respectively.

FIG. 2(a) shows a comparison of an electron concentration distribution 101 of the N4 layer obtained in the above-mentioned example by measuring the Hall coefficient with an electron concentration distribution 103 of a conventional N+ layer formed using Si+. The N+ layer of the GaAs field effect transistor manufactured by the method of the present invention has the highest electron concentration distribution at the crystal surface, and the surface concentration at this time is 1.8 X 10 Ia.
cm-3. This surface concentration is about five times that of the conventional manufacturing method, and is a high concentration that cannot be obtained with the Sj4 ion implantation layer.

The contact resistance was O, 09Ω/mm. g. of such a GaAs field effect transistor. n is 1.0 with a gate length of 1.0 μm. It was possible to increase it to 10 mS/mm.

Next, another embodiment of the present invention will be described using FIG. 1 in the same manner as the embodiment of the present invention. First, semi-insulating Ga As
A first ion implantation region 51 is formed on one surface of the crystal substrate 10 (FIG. 2(a)). In addition, a SiCh film 41 is selectively deposited on the w5Si3 film 31 and its side surface (see figure (b)).
). Next, an acceleration voltage of 100 keys and a dose of 5. 5
FIG. 2C shows how Se is selectively implanted 23 at X 10 13 cm-2 to form a second ion implantation region 52. Furthermore, reactive ion etching 34 is performed in the same manner as in the first embodiment to form a damaged region 25 (FIG. 4(d)). Finally, a heat treatment is performed at 830° C. for 20 minutes to form an n-type active layer 13 and N+14 (FIG. 4(e)).

Electron concentration distribution 102 of the N+ layer obtained in the above example
A comparison of the electron concentration distribution 103 of a conventional N+ layer formed using S]+ is shown in FIG. 2(b). The N+ layer of the GaAs field effect transistor produced by the method of the present invention had a surface concentration of 9 x 10"cm'. This surface concentration was increased 25 times compared to that produced by the conventional method. We were able to obtain a contact resistance of 0.03 Ω/mm.
,,, is the gate length] 125 mS/m at 0 μm
It was m. By using Se in this way, it is possible to obtain a device with a higher electron concentration distribution, lower contact resistance, and higher gm.

〔Effect of the invention〕

As explained above, the present invention reduces the surface concentration of the ion implantation region to 5 by performing reactive ion etching treatment on the surface of the ion implantation region after ion implantation of Group 6 elements.
The contact resistance of GaAs field effect transistors formed with such an N+ layer can be increased by a factor of ~25, thus reducing the transconductance g. This has the effect of increasing n to 1.6 to 2.0 times the conventional value.

Although it is not fully understood what is the effect of the ion implantation and active etching treatment of Group 6 elements that bring about this effect, it is possible to obtain the effect of the present invention in which the surface concentration increases for Group 4 Si elements. Because it is impossible to do this, and reactive etching has a great effect, the active ion etching process removes S, Se, and Te, which are members of group VI and tend to enter the lattice points of As in GaAs crystals and become donors. It is believed that As easily enters As vacancies formed by detachment from the GaAs crystal surface, and its activation is promoted.

Conventionally, ion implantation of Group 6 elements S, Se, and Te has been carried out to form the N+ layer, but activation of these Group 6 elements requires 850 to 900°C for S and 850 to 900°C for Se and Te. High temperature heat treatment at 900-930°C was essential. However, at such high temperatures, the thermal diffusion of these impurities becomes large, which poses a problem in obtaining a fine device structure. However, according to the present invention, the temperature is 800 to 83, which is the same as the activation temperature of Si, which is lower due to the heat treatment temperature required for activation of S and Se.
Even with heat treatment in the temperature range of 0°C, an N+ layer with an activation rate comparable to that of the conventional heat treatment temperature described above can be obtained, and the low temperature treatment also has the effect of suppressing thermal diffusion. .

[Brief explanation of the drawing]

1(a) to (f) are longitudinal sectional views of a GaAs crystal wafer for explaining each embodiment of the present invention, FIG. 2 is a diagram for explaining the effects of the present invention, and FIG. Figure 3 (a) to (e)
) is a longitudinal sectional view for explaining a conventional manufacturing method. 10... Semi-insulating GaAs crystal substrate, 1
2, 14...N+ layer, 13...active layer, 21, 22...s1+ ion implantation, 23.
...S+ or Se+ ion implantation, 24...
... Reactive ion etching, 25 ... Damage layer, 31 ... W5Si3 film, 32 ...
Source electrode, 33...Drain electrode, 41.4
2. Old... S102 film, 51... First ion implantation layer, 52... Second ion implantation layer, 101
・Old・2.5X1013S +/cnt distribution, 10
2--Distribution of 5.5X1013Se/crll, 103
...Distribution of 2.5×1o13sj+/c Tsukasa. Agent Patent Attorney Susumu Uchihara 1/)

Claims (1)

[Claims] A first ion implantation step using a Si element to form an N-type active layer, a second ion implantation step using a group 6 element to form an N^+ layer, and the second ion implantation step Reactive etching process after 800℃~830℃
A method for manufacturing a GaAs field effect transistor, comprising the step of performing heat treatment at .degree.