JPH03175680A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent an N<+> diffusion layer, the source region, from invading right below a gate while suppressing the hole concentration of the channel region on the source side so that it may not to be too high by forming a p-type region, and next implanting the ions of phosphorus in low concentration into the opening at a mask and annealing it, and then implanting the ions of arsenic in high concentration and annealing it. CONSTITUTION:This includes a process of making a gate oxide film 3 at the surface of the N-type epitaxial layer 2 on an N-type silicon substrate 1 and stacking a conductive film 4 and then implanting boron ions and annealing and drive-in-diffusing them so as to form P-type regions 7-9, and a process of implanting ions of phosphorous in low concentration into the opening at a mask and annealing and drive-in-diffusing them and then implanting ions of arsenic in high concentration and annealing them. For example, after the P-type diffusion layers 7-9 are made, phosphorous ions are implanted with a gate electrode 4 and a photoresist 10 as masks so as to form a phosphorous ions implantation layer 11, and then annealing and drive-in diffusion are applied, whereby a P-type diffusion layer 8 is expanded. Next, with the gate electrode 4 and a photoresist 12 as masks, phosphorous ions are implanted and annealed so as to form an N<+> diffusion layer 13 to become a source region.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a channel of a vertical power MO8FET.

[Conventional technology]

A method of forming a channel in a vertical power MOSFET according to the prior art will be described with reference to FIGS. 1(a), (b), and FIGS.

First, as shown in FIG. 1(a), after growing an N- type epitaxial layer 2 on the surface of an N+ type silicon substrate 1, a gate oxide IpA 3 is formed, a gate electrode 4 is formed, and a photoresist 5 is coated with butter. After that, boron is ion-implanted to form a boron ion-implanted layer 6.

Next, as shown in FIG. 1(b), annealing and drive-in diffusion are performed to form a channel region extending directly below the gate electrode.

Next, as shown in FIG. 3(a), using the gate I-electrode 4 and the photoresist 11 as a mask, the silicon oxide film 3 is
Transparent or silicon oxide 11! After etching 3, high-concentration arsenic is ion-implanted, annealed, and drive-in diffusion is performed to form an N+ type scattering layer 13 that will become the source region of the FET.

Alternatively, instead of ion-implanting arsenic, as shown in FIG. 3(b), by ion-implanting high-concentration phosphorus, annealing, and drive-in diffusion, an N++ diffusion N17 that will become the source region of the FET is formed.

[Problem to be solved by the invention]

The conventional method for forming a channel region has the following problems.

1. When forming an N'' diffusion layer with arsenic Figure 3 (a>
Since arsenic is hardly diffused even by annealing and drive-in diffusion, a region 7 with relatively high hole concentration exists in the channel region directly under the gate electrode.
The threshold voltage VT of the FET becomes high.

Since VGSS is limited by the dielectric strength of the gate oxide film, as VT increases, the gate input bias voltage increases, so the amplitude of the input signal voltage must be reduced, resulting in a decrease in output power. If the length (LG) changes, the boron ion implantation amount (dose) for forming the channel region must be changed, and the relatively high hole concentration in the P-type spreading layer 7 changes, resulting in VT and cannot be determined independently.

To give a specific example, when Lo is 3 to 5 μIn, vT becomes around 2 V when boron is implanted ff12 to 8×10”cm −2 , a normal channel region is formed, and stable production becomes possible.

However, when Lo is 1.4 to 2.0 μm, V7 is 4 to 9 when the boron ion implantation amount is 4X1013 cm-2.
As V increases, the variation also increases. This is because the gradient of boron concentration in the gate length direction of the channel region becomes steep.

At this time, if the boron ion implantation amount is 2 x 1013 cm2, the region of P-type diffusion yA9 with a relatively low hole concentration will become wider, the depletion layer will expand, and the influence of the drain voltage will become dominant, so that g, descend.

2. When forming an N'' diffusion layer with phosphorus, as shown in FIG. 3(b), phosphorus is diffused by annealing and drive-in diffusion to substantially eliminate a portion of the channel region with a high hole concentration. I can do it.

However, a portion of the N++ diffused layer that becomes the source region invades directly under the gate and overlaps, so that the gate-source equivalent capacity ft (CO2) increases and the cutoff frequency (ft) decreases.

An object of the present invention is to provide a manufacturing method in which the hole concentration in the channel region on the source side is suppressed from being too high, and the N++ diffused layer in the source region does not penetrate directly under the gate.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes the steps of forming a gate oxide film on the surface of an N-type silicon substrate, depositing a conductive film, and then performing annealing and drive-in diffusion to form a P-type region; After ion-implanting phosphorus at a high concentration and annealing, ion-implanting arsenic at a high concentration, annealing, and drive-in diffusion; The process consists of batch annealing and drive-in diffusion.

〔Example〕

Regarding the first embodiment of the present invention, FIGS. 1(a) to (e)
Explain with reference to.

First, as shown in FIG. 1(a), an N- type epitaxial rCIJ 2 is grown on the surface of an N++ silicon substrate 1, and a gate oxide film 3 is formed by thermal oxidation.

Next, a gate electrode 4 (gate length 2 μm) made of molybdenum is formed as a heat-resistant conductive film, and this gate electrode 4
and photoresist 5 as a mask, boron ions are implanted in an amount of 3 to 6 x 10 I3c +n-2, and P
A type ion implantation layer 6 is formed.

Here, as the material for the gate electrode 4, other high melting point metals such as tungsten, silicide of high melting point metals, polysilicon doped with impurities at a high concentration, etc. can also be used.

Next, as shown in Fig. 1(b), heat treatment is performed at 1100°C for 2 hours in Shiun atmosphere, so that the channel region is exposed to P.
A type diffused layer 8, a P-type diffusion layer 7 with a relatively high hole concentration, and a P-type diffusion layer 9 with a relatively low hole concentration are formed.

Next, as shown in FIG. 1(c), phosphorus ions are implanted in an implantation amount of I.times.10" to I.times.10"cm"2 using the gate electrode 4 and the photoresist I.10 as masks.
A phosphorus ion implantation layer 11 is formed.

Next, as shown in FIG. 1(d), 1000 to 1100
By performing heat treatment (annealing drive-in diffusion) in a hydrogen atmosphere for 1 hour, the effective hole concentration in the channel region with relatively high boron concentration is reduced, and the P-type diffusion layer 8
expand.

Next, as shown in FIG. 1(e), using the gate electrode 4 and the photoresist 10 as a mask, phosphorus ions are implanted at a dose of I.
By implanting X 10I6cm-2 and annealing, an N++ diffused layer 13 which will become a source region is formed.

Next, regarding the second embodiment of the present invention, FIG. 1 (a>,
(+)) and FIGS. 2(a>, (b)).

First, as shown in FIGS. 1(a) and (l'), in the channel region there is a P-type diffusion layer 8, a P-type diffusion layer 7 with a relatively high hole concentration, and a P-type diffusion layer with a relatively low hole concentration. layer 9 is formed.

Next, as shown in FIG. 2(a), using the gate electrode 4 and the photoresist 14 as a mask, phosphorus ions are injected into the
~lXl012 cm-2 is implanted to form a phosphorus and arsenic ion implantation layer 15.

Next, as shown in FIG. 2(b), 1000 to 1050
By heat treatment for 1 hour in a hydrogen atmosphere at °C, part of the part is annealed and drive-in diffused to form the N++ diffused layer 16 that will become the source region, and phosphorus is mainly diffused to form a part with high boron concentration in the channel region. Reduces effective hole concentration.

In this case, a part of the N+ type scattering layer 16, which is the source region, slightly invades directly under the gate electrode 4, but the photolithography process for the ion implantation mask can be reduced by one.

"Effect of the invention" By using phosphorus and arsenic together in the ion implantation process of the source region, phosphorus is diffused into the relatively high boron concentration part of the channel region without penetrating into the channel region directly under the gate electrode. This made it possible to reduce the effective hole concentration in this region.

In this way, by adjusting the ratio of phosphorus and arsenic, Vt and LG can be determined independently on a practical level, and Vt can be controlled without lowering the cut-off frequency. It's now possible.

[Brief explanation of drawings]

1(a) to (e) are cross-sectional views showing a first embodiment of the present invention, FIGS. 2(a) and (b) are cross-sectional views showing a second embodiment of the present invention, and FIG. Figures (a> and (b) are cross-sectional views of the vicinity of the gate electrode of a vertical power MO3FET according to the prior art. 1...N++ silicon substrate, 2...N- type epitaxial layer, 3...・Silicon oxide film, 4... Gate electrode, 5... Photoresist, 6... Boron ion implantation layer, 7... P-type diffusion layer with relatively high hole concentration, 8.
...P type diffusion layer, 9...P type diffusion layer with relatively low hole concentration, 10...photoresist, 11...phosphorus ion implantation layer, 12...photoresist, 13...N+
Type type scattering layer 14... Photoresist, 15... Phosphorus and arsenic ion implantation layer, 16... N+ type scattering layer 1
7...N4 type diffusion layer (the impurity is phosphorus).

Claims (1)

[Claims] 1. A step of forming a gate oxide film on the surface of an N-type silicon substrate, depositing a conductive film, and then performing annealing and drive-in diffusion to form a P-type region; A method for manufacturing a semiconductor device, comprising the steps of ion-implanting phosphorus, annealing, and drive-in diffusion, then ion-implanting high-concentration arsenic, and annealing. 2. The method of manufacturing a semiconductor device according to claim 1, wherein ions of phosphorus at a low concentration are implanted, then ions of arsenic at a high concentration are implanted, and then annealing and drive-in diffusion are performed all at once.