JPH0319239A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To increase breakdown strength by forming a first side wall spacer on the sidewall of a gate electrode, and implanting impurity ions in the surface of a semiconductor substrate under the lower surface of the first side wall spacer and outside the spacer. CONSTITUTION:A nitride film 7 is formed on a gate oxide film 2 and a gate electrode 3; on the sidewall of the electrode 3, a thin side wall spacer 8 composed of a CVD oxide film is formed, whose maximum film thickness is 200nm. By using an electrode 3 as a mask, arsenic ions 9 are implanted into the surface of a semiconductor substrate 1 below and outside the spacer 8, so as to penetrate the spacer 8, the nitride film 7 outside the spacer, and the oxide film 2; by heat treatment, an N-type impurity layer 10 is formed. Thereby inclination can be formed in the horizontal impurity concentration distribution below the spacer 8, so that the electric field intensity below the electrode 3 can be relieved, and the breakdown strength of source drain and the like can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing a semiconductor device that increases source-drain breakdown voltage and hot carrier breakdown voltage in a large-scale integrated circuit.

BACKGROUND OF THE INVENTION In recent years, with the progress in miniaturization of semiconductor devices, reductions in source/drain breakdown voltage and hot carrier breakdown voltage have become a problem. As an effective countermeasure against this problem, a semiconductor device having an LDD structure has conventionally been used.

A method of manufacturing a conventional semiconductor device having an LDD structure will be described below.

FIG. 4 is a cross-sectional view showing a method of manufacturing a conventional semiconductor device having an LDD structure. In FIG. 4, 1 is a semiconductor substrate;
2 is a gate oxide film, and 3 is a gate electrode. 4 is a low concentration impurity layer formed by implanting impurity ions using the gate electrode 3 as a mask. 6 is a sidewall spacer formed on the side wall of the gate electrode fM3, and 6 is a high concentration impurity layer formed by implanting impurity ions using the gate electrode 3 and the sidewall spacer 6 as masks. In the semiconductor device manufactured by the above manufacturing method, the impurity concentration distribution of the low concentration impurity layer 4 below the gate electrode 3 defines the drain aparanche voltage and, in turn, the source/drain breakdown voltage.

Problems to be Solved by the Invention However, in the conventional manufacturing method described above, the low concentration impurity layer 4 is formed using the gate electrode 3 as a mask, and the sidewall spacer 5 serves to block the passage of impurity ions. Therefore, the horizontal impurity concentration distribution of the low concentration impurity layer 4 under the sidewall spacer 5 is constant. The horizontal impurity concentration distribution of the low concentration impurity layer 4 near the bottom of the gate electrode 3 is caused only by thermal diffusion from the low concentration impurity layer 4, which has a uniform impurity concentration distribution under the spacer 6 (sidewall/l/7). Therefore, as semiconductor devices are miniaturized, it has been difficult to obtain necessary and sufficient source/drain breakdown voltage.

The present invention solves the above-described conventional problems by controlling the slope of the horizontal impurity concentration distribution of the low concentration impurity layer 4 near the bottom of the gate electrode 3 at the time of impurity ion implantation to achieve the necessary and sufficient source/drain breakdown voltage. It is an object of the present invention to provide a method for manufacturing a semiconductor device for obtaining the following.

Means for Solving the Problems For this purpose, the method for manufacturing a semiconductor device of the present invention includes the steps of: forming a first sidewall spacer thinner than the thickness of the gate electrode on the side wall of the gate electrode; and implanting impurity ions into the lower surface of the first sidewall/I/7-spacer through the first sidewall spacer using a mask.

Effect: Due to this structure, the amount of impurity ions that can be implanted into the semiconductor substrate surface on the lower surface of the first side-all spacer changes according to the thickness of the first side-all spacer. By tilting the horizontal impurity concentration distribution, the electric field strength under the gate electrode can be relaxed, and as a result, the source/drain breakdown voltage and the hot carrier breakdown voltage can be increased.

EXAMPLE An example of the present invention will be described below with reference to the drawings.

(Example 1) FIG. 1 is a sectional view showing a method for manufacturing a semiconductor device according to an example of the present invention. In FIG. 1, 1 is a semiconductor substrate made of P-type silicon, 2 is a gate oxide film, and 3 is a gate electrode, which are the same as the conventional structure. Reference numeral 7 denotes a nitride film formed on the gate oxide film 2 and the gate electrode 3. Reference numeral 8 designates a first sidewall spacer made of a CVD oxide film on the sidewall of the gate electrode 3. 9 is an arsenic ion. 10 uses the gate electrode 3 as a mask, and the first
sidewall spacer 8 and the nitride film 7 outside thereof
This is an N-type impurity layer formed by implanting arsenic ions 9 into the lower surface of the first sidewall spacer 8 and the surface 1 of the semiconductor substrate outside thereof through the gate oxide film 2 and performing heat treatment.

FIG. 2 is a cross-sectional view showing a method of manufacturing the thin first sidewall spacer 8. As shown in FIG. In FIG. 2, 1 is a semiconductor substrate, 2 is a gate oxide film, and 3 is a gate electrode, which are the same as the conventional structure. Further, 7 is a nitride film. 1
1 is a first CVD oxide film, and 12 is a 20th CVD oxide film.

A method for manufacturing a semiconductor device with the above precautions will be described in detail below.

A method of manufacturing the thin first sidewall spacer 8 will now be described. In FIG. 2, the thickness of gate electrode 3 is 400 nm, and the thickness of gate oxide film 2 is 20 nm. As shown in FIG. 2a, a nitride film 7 with a thickness of 6 nm is formed on the gate oxide film 2 and the gate electrode 3, and a film thickness of about 200 nm is formed at a distance of about 300 nm from the gate electrode 3.
A tenth CVD oxide film 11 having a thickness of 10 nm is formed. Next, as shown in FIG. 2b, a second CVD oxide film 12 is deposited.

Then, as shown in FIG. 2C, the gate electrode 3 and the first
The 20th CVD oxide film 12 on the 0th CVD oxide film 11 is missing.
Continue etching until it is complete. Furthermore, as shown in d of FIG. 2, the first CvD oxide film 11,
When the second CVD oxide film 12 is etched, a thin first sidewall aperture 8 having a maximum thickness of about 200 nm is formed on the sidewall of the gate electrode 3. In this way, the maximum thickness of the first sidewall spacer 8 can be controlled by the difference between the thickness of the gate electrode 3 and the thickness of the first CVD oxide film 11, and the width of the first sidewall spacer 8 can be controlled by the difference between the thickness of the gate electrode 3 and the thickness of the first CVD oxide film 11. It can be controlled by the distance between the gate electrode 3 and the first CVD oxide film 11.

Next, a method of manufacturing a semiconductor device using the thin first sidewall spacer 8 manufactured by the above-described manufacturing method will be described. In FIG. 1, the impurity concentration of the semiconductor substrate 1 is approximately 1×10 16 cIII-3, the thickness of the gate oxide film 2 is 20 nm, and the thickness of the gate electrode Wi 3 is 400 nm.
It is nm. The first Saiduo! The maximum film thickness of the spacer 8 is approximately 100 nm, which is also thinner than the gate electrode 3, including the thicknesses of the gate oxide film 2 and the nitride film 7. Using the gate electrode 3 as a mask, the first sidewall μ spacer 8 and the gate oxide film 2 and nitride film 7 outside thereof are transmitted.
Arsenic ions 9 are implanted into the lower surface of the sidewall spacer 8 and the semiconductor substrate surface 1 outside thereof under conditions of 50 keV, 4
Inject at X10 Cllg. 9oO℃, 100
After heat treatment for minutes, the surface impurity concentration of the N-type impurity layer 1o is
When the thickness of the first sidewall spacer 8 is 10 onm, approximately 1. When IX10cII150nm, it becomes about 1,3XIQ20-6.

As described above, according to the present embodiment, the first sidewall spacer 8 is formed on the side wall of the gate electrode 3, and the arsenic ions 9 are implanted through the first sidewall spacer 8, so that the first sidewall spacer 8 is implanted. The impurity concentration distribution in the horizontal direction can be sloped at the bottom of the sidewall spacer 8, and as a result, the electric field strength at the bottom of the gate electrode 3 can be relaxed, and the source/drain breakdown voltage and hot carrier breakdown voltage can be increased. I can do it. Here, when the arsenic ions 9 are implanted, the gate oxide film 2 and the nitride film 7 are present on the outside of the first sidewall spacer 8.
A drain diffusion layer can be created. Further, this manufacturing method has the advantage that the impurity layer under the first sidewall spacer 8 and the source/drain diffusion layer outside the first sidewall spacer 8 can be formed by forming the sidewall spacer and implanting impurity ions once.

(Embodiment 2) FIG. 3 is a sectional view showing a method for manufacturing a semiconductor device according to another embodiment of the present invention. Referring to FIG. 3, 1 is a semiconductor substrate made of P-type silicon, 2 is a gate oxide film, 3 is a gate electrode, and 8 is a first sidewall spacer, which is the same as the structure of Example 1. be. 13 is phosphorus ion, 1
4. Using the gate electrode 3 as a mask, the first sidewall spacer 8 is transmitted through the first sidewall IL/7.
．． This is an N-type low-concentration impurity layer formed by implanting phosphorus ions 13 into the lower surface of the spacer 8 and the surface 1 of the semiconductor substrate outside the spacer 8 and heat-treating it. Reference numeral 16 denotes a second side wall spacer formed above the first side wall spacer 8. 1st. The maximum film thickness including the second sidewall spacer 8.15 is about 400 nm. 16 is an arsenic ion, and 17 is an N-type high concentration impurity layer formed by implanting the arsenic ion 16 using the gate electrode 3 and the first and second sidewall spacers 8.15 as masks, and performing heat treatment.

A method of manufacturing the semiconductor device constructed as described above will be described in detail below.

In FIG. 3, the impurity concentration of the semiconductor substrate 1 is approximately 1×1.
016-3 The thickness of the gate oxide film 2 is 2 onm, and the thickness of the gate electrode 3 is 400 nm.

The maximum film thickness of the first sidewall spacer 8, including the thicknesses of the gate oxide film 2 and the nitride film 7, is about 200 nm, which is thinner than the gate electrode 3. As shown in FIG. 3a, using the gate electrode 3 as a mask, the first sidewall spacer 8 and the gate oxide film 2 and nitride film 7 outside thereof are removed.
The phosphorus ions 13 are implanted into the lower surface of the first sidewall spacer 8 and the surface 1 of the semiconductor substrate outside the first sidewall spacer 8 under implantation conditions of 10OkeV, 2×1013as−2. After heat treatment at 900° C. for ioo minutes, the surface impurity concentration of the N-type low concentration impurity layer 14 is approximately 6.2×1o1 when the thickness of the first sidewall spacer 8 is 200 nm.
Approximately 8.6cIr5, 15Qnm. I X10 6
1. At 100nm, it is approximately 1.9×1018K3
becomes. In this way, when impurity ions are implanted, the impurity distribution can be sloped in the horizontal direction under the first sidewall spacer 8.

Next, as shown in FIG. 3b, a second sidewall spacer 16 is formed on the first sidewall spacer 8, and the gate electrodes [3 and the first . Even if arsenic ions 16 are implanted using the second sidewall spacer 8.16 as a mask and an N-type high concentration impurity layer 1 is formed, the film thickness of the first and second sidewall spacers 8, 16 is These first and second side wall spacers8.16 are sufficiently thick.
No arsenic ions 16 are injected into the lower semiconductor substrate.

As described above, according to this embodiment, by forming the first side wall spacer 8 on the side wall of the gate electrode 3 and implanting impurity ions from above, the lower part of the first side wall spacer 8 is formed. The impurity concentration distribution in the horizontal direction can be sloped, and as a result, the electric field strength under the gate electrode 3 can be relaxed. By optimizing the implantation conditions for the phosphorus ions 13 and the thickness of the first sidewall spacer 8, the highest source/drain breakdown voltage and hot carrier breakdown voltage can be obtained.

In this embodiment, the semiconductor substrate 1 is of P type, but the semiconductor substrate 1 may be of N type, in which case the phosphorus ions 13
, impurities such as boron ions are implanted in place of the arsenic ions.

Effects of the Invention As described above, the present invention forms a first sidewall spacer on the sidewall of a gate electrode, and extends from above the gate electrode and the first sidewall spacer to the bottom surface of the first sidewall spacer and the outer side thereof. By implanting impurity ions into the surface of the semiconductor substrate, the horizontal impurity concentration distribution on the bottom surface of the first sidewall spacer can be sloped during impurity ion implantation, increasing source-drain breakdown voltage and hot carrier breakdown voltage. This makes it possible to realize an excellent method of manufacturing a semiconductor device.

[Brief explanation of the drawing]

1 and 3 are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing a method for manufacturing a thin first sidewall spacer, and FIG. 4 is a cross-sectional view showing a method for manufacturing a thin first sidewall spacer. FIG. 3 is a cross-sectional view showing a method of manufacturing a semiconductor device having an LDD structure. 1... Semiconductor substrate, 2... Gate oxide film, 3... Gate electrode, 4... N-type low concentration impurity layer, 5... ...Side wall spacer, 6...N-type high concentration impurity layer, 7...
Nitride film, 8...First sidewall spacer, 9...Arsenic ion, 10...N-type impurity layer, 11...First CVD Oxide film, 12.
... Second CVD oxide film, 13 ... Phosphorus ion, 14 ... N-type low concentration impurity layer, 16.
...Second side wall spacer, 16...
...Arsenic ion, 17...N-type high concentration impurity layer.

Claims (3)

[Claims] (1) forming a gate oxide film on the semiconductor substrate;
forming a gate electrode on the gate oxide film; forming a nitride film on the gate oxide film and the gate electrode; and forming a first sidewall spacer thinner than the thickness of the gate electrode on the sidewall of the gate electrode. a step of forming;
Implanting impurity ions into the lower surface of the first sidewall spacer and the surface of the semiconductor substrate outside thereof through the first sidewall spacer and the nitride film and gate oxide film outside the first sidewall spacer using the gate electrode as a mask. A method for manufacturing a semiconductor device, comprising: (2) Using the gate electrode as a mask, impurity ions are implanted into the lower surface of the first sidewall spacer and the surface of the semiconductor substrate outside thereof through the first sidewall spacer and the nitride film and gate oxide film outside the first sidewall spacer. After the process, a second sidewall spacer is placed on the first sidewall spacer.
forming a sidewall spacer, using the gate electrode and the first and second sidewall spacers as a mask, and transmitting a nitride film and a gate oxide film outside the first and second sidewall spacers. The first
2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of implanting impurity ions into the surface of the semiconductor substrate outside the second sidewall spacer. (3) forming a first oxide film on the nitride film away from the gate electrode; forming a second oxide film on the gate electrode and the first oxide film; 3. The method of manufacturing a semiconductor device according to claim 1, wherein the first sidewall spacer is formed from the step of etching the film and the first oxide film.