JPH06350086A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To realize an exact source-drain distance of a MOS transistor and to realize shallower implantation for a source and a drain. CONSTITUTION:After a gate oxide film 2 and a polysilicon gate electrode 3 are formed on the main surface of a silicon substrate 1, silicon ion implantation is executed with the polysilicon gate electrode 3 used as a mask, so that an amorphous silicon layer 10 is formed on the silicon substrate. After a side wall 5 of a CVD oxide film is formed on the lateral side of the polysilicon gate electrode 3, subsequently, arsenic ion implantation is executed in the amorphous silicon layer 10 formed previously, with the side wall 5 used as a mask, and thereby an N-type region of high concentration is formed. By utilizing that the speed of impurity diffusion in the amorphous silicon layer 10 is higher than that in a single-crystal layer of the silicon substrate 1, thereafter, an N-type region of low concentration is formed by diffusion in the amorphous silicon layer 10 under the side wall 5 by heat treatment.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, which is an integrated circuit element of fine dimensions, which uses a MOS transistor.

[0002]

2. Description of the Related Art As semiconductor elements are highly integrated and miniaturized,
The distance between the source and drain of a MOS transistor is also in the submicron range. However, as the source-drain distance becomes smaller, the electric field strength of the channel portion becomes larger, and the hot carrier effect and the short channel effect become remarkable. Therefore, there is a structure called a low concentration drain (LDD) in which a low concentration n-type region is provided in the vicinity of the drain having the highest electric field in order to suppress the electric field strength of the channel portion.

A conventional method for manufacturing an LDD structure of an N-type transistor will be described with reference to FIG. First, FIG. 3 (a)
As shown in FIG. 3, a gate oxide film 2 is formed on the main surface of a silicon substrate 1, and a polysilicon gate electrode 3 is formed on the gate oxide film 2. Phosphorus ions are implanted using the polysilicon gate electrode 3 as a mask to form a low concentration n-type region 4.

Next, as shown in FIG. 3 (b), CVD
An oxide film is deposited on the entire surface, and the side wall 5 of the CVD oxide film is formed on the side surface of the polysilicon gate electrode 3 by using anisotropic etching.
To form. Arsenic ion implantation is performed using the side wall 5 as a mask to form a high concentration n-type region 6. After that, FIG.
As shown in (c), heat treatment (annealing) is performed to diffuse the impurities.

Next, referring to FIG. 4, a conventional CMOS
A method of manufacturing the LDD structure of the transistor will be described. First, as shown in FIG. 4A, an N-type transistor (see FIG.
Transistor on the left side of) and a P-type transistor (see FIG. 4).
(The transistor on the right side of FIG. 2), the gate oxide film 2 and the polysilicon gate electrode 3 are formed on the main surface of the silicon substrate 1.

Next, the P-type transistor side (right side in FIG. 4) is masked with the entire surface resist layer 7A, and the N-type transistor side (left side in FIG. 4) is subjected to phosphorus ion implantation using the polysilicon gate electrode 3 as a mask. Then, the low concentration n-type region 4 is formed on the N-type transistor side. Next, as shown in FIG. 4B, the N-type transistor side (left side in FIG. 4) is masked by the entire surface resist layer 7B, and the P-type transistor side (right side in FIG. 4) is covered with a polysilicon gate electrode. Boron ion implantation is performed using 3 as a mask to form a low concentration p-type region 8 on the P-type transistor side.

Next, as shown in FIG. 4C, CVD
The side wall 5 is formed on the side surface of the polysilicon gate electrode 3 by the oxide film.
To form. Then, on the P-type transistor side,
Masked by strike layer 7C, N-type transistor side
Is a high-concentration n-type with arsenic ion implantation using the sidewall 5 as a mask.
Region 6 is formed. Next, as shown in FIG.
After that, on the N-type transistor side, the entire surface resist layer 7D is formed.
Mask, and the side wall 5 is masked on the P-type transistor side.
BF to school ₂ Ion implantation is performed to form high-concentration p-type region 6
To do.

After that, heat treatment is performed to form a CMOS transistor having an LDD structure.

[0009]

However, in the above conventional manufacturing method, the heat treatment is performed after the formation of the high-concentration n-type region and the high-concentration p-type region in order to further miniaturize the semiconductor element. There is a problem that the type region and the low-concentration p-type region are diffused laterally to shorten the effective length of the source-drain distance of the MOS transistor. In order to perform shallower source / drain implantation, the conventional implantation method has a problem that it is difficult to control in the depth direction by channeling (a phenomenon in which ions pass through between silicon crystal lattices).

In addition, there is a problem that the ion implantation process as many as four times is required when manufacturing the CMOS transistor. This invention realizes a more accurate source-drain distance, realizes a shallower source-drain injection,
Further, the present invention provides a method for manufacturing a semiconductor device that can reduce the number of ion implantation steps.

[0011]

According to the method of manufacturing a semiconductor device of the present invention, a step of forming a gate oxide film and a gate electrode on a main surface of a silicon substrate, and a silicon ion implantation using the gate electrode as a mask are performed on the silicon substrate. A step of forming a silicon non-crystalline layer on the gate electrode, a step of forming a side wall of the insulating film on the side surface of the gate electrode, and a step of performing impurity ion implantation into the silicon non-crystalline layer using the gate electrode and the side wall as a mask to form a shallow high impurity concentration region. And a step of diffusing and forming a low impurity concentration region in the silicon amorphous layer below the side wall by heat treatment.

[0012]

According to the method of manufacturing a semiconductor device of the present invention, silicon ions are implanted using the gate electrode as a mask to prevent channeling in the silicon substrate compared to a crystalline layer, thereby enabling implantation in a shallower region, and thus a diffusion rate. Of the silicon amorphous layer is formed, the side wall is formed on the gate electrode, the high-concentration region is formed in the silicon amorphous layer using the gate electrode and the side wall as a mask, and then the silicon amorphous layer under the barrier is heat-treated. Since the low-concentration region is formed by diffusion, it becomes easy to stop the diffusion at the boundary between the silicon amorphous layer and the crystalline layer, and the distance between the source and drain of the MOS transistor does not have to be shorter than the target length. Further, the high-concentration region and the low-concentration region can be formed by one-time ion implantation, and in the case of a CMOS transistor, the ion implantation has been conventionally performed. Those were requires only three times.

[0013]

FIG. 1 shows a manufacturing process of an LDD structure of an N-type transistor which is an embodiment of the present invention. First, as shown in FIG. 1A, after a gate oxide film 2 and a polysilicon gate electrode 3 are formed on the main surface of a silicon substrate 1, silicon ion implantation is performed using the polysilicon gate electrode 3 as a mask to remove silicon. A silicon amorphous layer 10 is formed on the substrate 1.

Next, as shown in FIG. 1B, after the side wall 5 of the CVD oxide film is formed on the side surface of the polysilicon gate electrode 3, the side wall 5 is used as a mask to form the silicon amorphous layer previously formed. Arsenic ions are implanted into the inside of 10,
A high concentration n-type region 6 is formed. Thereafter, as shown in FIG. 1C, heat treatment is performed by utilizing the fact that the impurity diffusion rate of the silicon non-crystalline layer 10 is higher than that of the single crystal layer of the silicon substrate 1, and the silicon non-crystalline under the side wall 5 is performed. A low concentration n-type region 4 is formed in the layer 10. If the heat treatment time and temperature are sufficiently taken into consideration, it is apparent that impurity diffusion due to heat is suppressed inside the silicon amorphous layer 10 and the source-drain distance of the MOS transistor is not shortened more than necessary. .

FIG. 2 is a CM showing another embodiment of the present invention.
7 shows a process for manufacturing an LDD structure of an OS transistor. First, as shown in FIG. 2A, the same silicon substrate 1 is used for both the N-type transistor and the P-type transistor.
After the gate oxide film 2 and the polysilicon gate electrode 3 are formed thereon, silicon ions are implanted using the polysilicon gate electrode 3 as a mask to form a silicon amorphous layer 10.

Next, as shown in FIG. 2 (b), after forming the side wall 5 of the CVD oxide film on the side surface of the polysilicon gate electrode 3, the entire surface of the P-type transistor (right side) is masked by the resist layer 7A. Then, on the N-type transistor side (left side), arsenic ion implantation is performed using the side wall 5 of the CVD oxide film as a mask to form a high concentration n-type region 6. Next, as shown in FIG. 2C, a mask of the entire surface resist layer 7B is applied to the N-type transistor side, and BF ₂ ion implantation is performed on the P-type transistor side using the sidewall 5 as a mask to perform high-concentration p-type region 9 To form.

After that, as shown in FIG. 2D, a low concentration n-type region 4 and a low concentration p-type region 8 are diffused by heat treatment. As described above, the ion implantation process, which has been performed four times in the conventional CMOS / LDD structure manufacturing process, can be performed three times. Table 1 shows an example of each ion implantation condition used in these examples.

[0018]

[Table 1]

The heat treatment conditions used in these examples are temperature: 900 ° C. and time: 30 minutes.

[0020]

According to the method of manufacturing a semiconductor device of the present invention, since the low concentration region is formed by utilizing the fast impurity diffusion of the amorphous layer of silicon after the high concentration source / drain implantation, the accurate source / drain is formed. It is possible to realize an inter-distance, and it is possible to reduce the number of ion implantation steps when manufacturing a CMOS transistor.

[Brief description of drawings]

1A to 1C are sectional views for explaining an embodiment of a method for manufacturing a semiconductor device of the present invention.

2A to 2D are cross-sectional views for explaining another embodiment of the method for manufacturing a semiconductor device according to the present invention.

3A to 3C are sectional views for explaining an example of a conventional method for manufacturing a semiconductor device.

4A to 4D are cross-sectional views for explaining another example of the conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 1 Silicon substrate 2 Gate oxide film 3 Polysilicon gate electrode 4 Low concentration n-type region 5 CVD oxide film side wall 6 High concentration n type region 7A, 7B Resist layer 8 Low concentration p type region 9 High concentration p type region 10 Silicon amorphous layer

Claims (1)

[Claims] 1. A step of forming a gate oxide film and a gate electrode on a main surface of a silicon substrate, and a step of performing silicon ion implantation using the gate electrode as a mask to form a silicon amorphous layer on the silicon substrate. A step of forming a sidewall of an insulating film on a side surface of the gate electrode, a step of implanting impurity ions into the inside of the amorphous silicon layer using the gate electrode and the sidewall as a mask to form a high impurity concentration region, and a heat treatment. Diffusing and forming a low impurity concentration region in the silicon amorphous layer below the side wall.