JP3142614B2 - Method for manufacturing N-channel MOSFET - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an N-channel MOSFE
The present invention relates to a T manufacturing method.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, there are the following.

[0003] Currently used N channel M
It will be described with reference to FIG. 4 a manufacturing method of OSFET.

First, as shown in FIG. 4A, a thick oxide film 2 is formed on a P-type silicon substrate 1 to form a field region,
After forming the active region, a gate oxide film 3 is grown in the active region.

Next, as shown in FIG. 4B, in order to adjust Vt (threshold voltage), in order to increase the impurity concentration in the silicon substrate below the gate, a gate oxide film 3 is formed.
Through the Vt control ion implantation, ¹¹ B ⁺
Ions are implanted into a silicon substrate.

Thereafter, as shown in FIG. 4C, a polysilicon film 4 is formed, and a gate is formed by photolithographic etching. Further, the source / drain 5 and 6 are formed by ion implantation and appropriate heat treatment.

[0007] Next, as shown in FIG.
Is formed, a contact hole is opened, and a wiring layer 8 is formed of aluminum or the like.

[0008] As a known technique in such a field,
For example, Japanese Patent Application Laid-Open No. 61-292318 and Japanese Patent Application Laid-Open
No. 195,928.

[0009]

An N-channel MOSFET formed by the above-described manufacturing method.
FIG. 5 shows an example of the impurity profile of FIG.

Vt control ion-implanted ¹¹ B ⁺
The ion profile has a peak at a depth according to the acceleration energy at the time of ion implantation, and the ion implantation has a distribution of implanted impurities centered on the peak. I will. Therefore, the driving force decreases.

[0011] The reduction in driving force prevents high-speed operation of the MOSFET. However, omitting Vt control ion implantation not only makes it impossible to adjust Vt, but also increases the depletion layer width of the gate.
In the SFET, a short channel effect occurs. Therefore, Vt control ion implantation cannot be omitted in order to achieve high integration.

[0012] For the above reasons, the high impurity concentration on the substrate surface due to Vt control ion implantation greatly hinders the speeding up of the integrated circuit.

According to the present invention, in order to eliminate the above-mentioned problem of a decrease in driving force caused by the high impurity concentration on the silicon substrate surface, the impurity concentration on the substrate surface is reduced as much as possible.
In addition, the adjustment of Vt and the generation of the short-channel effect can be performed by forming an N-channel MOSFET equivalent to that of the prior art, and an N-channel MO capable of high speed and high integration can be obtained.
An object of the present invention is to provide a method for manufacturing an SFET.

[0014]

According to the present invention, there is provided a method of manufacturing an N-channel MOSFET, comprising the steps of: providing a P-type silicon substrate having a field region and an active region defined on a surface thereof; When, P and forming a first oxide film on the active region at the silicon substrate and the first interface range distance was set so that the peak of the P-type impurity concentration profile of the oxide film Implanting impurities of a mold type , removing the first oxide film, and then epitaxially growing silicon in the active region so that the impurity concentration in the active region near the surface of the silicon substrate is reduced. And forming a second in the active region.
Gate oxide film, gate electrode, source / drain
And a step of forming each of the in-layers .

[0015]

According to the present invention, as described above, in the manufacture of an N-channel MOSFET, after forming an active region, an oxide film is formed, and a range distance is set so that a peak of a profile comes to the Si-SiO ₂ interface. Then, Vt control ion implantation is performed. After that, remove the oxide film,
Silicon is formed in the active region by low-temperature epitaxial growth. By taking this step, it is possible to form a profile in which the impurity concentration in the shallow portion below the gate is very low and the impurity concentration in the deeper portion is high.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows an N-channel M according to an embodiment of the present invention.
FIG. 2 is a sectional view of a main part manufacturing process of an OSFET, and FIG.

First, as shown in FIG. 1A, a field region and an active region are formed on a P-type silicon substrate 11 by a thick oxide film 12 of about 6000.degree.

Next, as shown in FIG. 1B, an oxide film 13 having a thickness of about 500 ° is formed in the active region.

Next, as shown in FIG. 1 (c), as a Vt control ion implantation, the range is set to Si-SiO _2.
70 Kev according to the interface, dose amount 4.0 × 1
Ion implantation of ⁴⁹ BF ₂ ⁺ is performed at 0 ¹² / cm ² .

Next, as shown in FIG.
The oxide film 13 in the active region generated in (b) is removed with hydrofluoric acid.

Next, as shown in FIG. 1 (e), in disilane Si ₂ H ₆ atmosphere under conditions of 700 ° C., the silicon was 500~1000Å about epitaxially grown Akuteibu region, an epitaxial layer 14 I do. Since this step is performed at a low temperature of 700 ° C., FIG.
The diffusion of B ⁺ implanted in (c) is small, and there is almost no influence on the impurity profile. Further, since silicon is formed by epitaxial growth, silicon is not generated on the oxide film of the field, but is selectively generated only on the active region.

Next, as shown in FIG.
Gate oxide film 1 in a wet O ₂ atmosphere at a low temperature
5 is generated.

Next, as shown in FIG. 2B, a polysilicon film 16 is formed, and a gate is formed by photolithographic etching. Further, the source / drain 17 and 18 are formed by ion implantation and heat treatment at an appropriate low temperature (for example, 850 ° C. or lower).

Next, as shown in FIG.
9, a contact hole is opened, and a wiring layer 20 is formed of aluminum or the like.

As described above, since it is constituted by the step of heat treatment at a low temperature of 850 ° C. or less, B ⁺ ions do not diffuse into silicon produced by epitaxial growth.

FIG. 3 shows a concentration profile formed by the above-described steps. In this figure, the horizontal axis is depth,
The vertical axis indicates the impurity concentration (ions / cm ³ ).

Compared with the profile of the prior art shown in FIG. 5, B ⁺
A portion shallower than a peak portion of a profile formed by ions has a very low impurity concentration.

As a result, a decrease in driving force caused by an increase in impurity concentration due to Vt control ion implantation is reduced. The portion deeper than the peak portion is almost the same as that according to the related art. Therefore, the occurrence of the short channel effect is not much different from that of the related art.

It should be noted that the present invention is not limited to the above embodiment, but various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

[0031]

As described above in detail, according to the manufacturing process of the present invention, as shown in FIG. 3, the impurity concentration near the substrate surface is very low, and the impurity concentration is deeper in the portion deeper than that. And an ideal profile that is favorable for both the driving force and the short channel effect can be formed.

Therefore, it is possible to manufacture an N-channel MOSFET capable of high speed and high integration.

[Brief description of the drawings]

FIG. 1 is an N-channel MOSFET showing an embodiment of the present invention.
3 is a cross-sectional view of a main part manufacturing process.

FIG. 2 shows a second half N-channel MOS showing an embodiment of the present invention.
FIG. 4 is a cross-sectional view of a manufacturing process of the FET.

FIG. 3 is a diagram showing an impurity profile of an N-channel MOSFET of the present invention.

FIG. 4 is a sectional view showing a manufacturing process of a conventional N-channel MOSFET.

FIG. 5 is a diagram showing an impurity profile of a conventional N-channel MOSFET.

[Explanation of symbols]

 Reference Signs List 11 P-type silicon substrate 12, 13 oxide film 14 epitaxial layer 15 gate oxide film 16 polysilicon film 17, 18 source / drain 19 insulating film 20 wiring layer

Continuation of the front page (56) References JP-A-59-151464 (JP, A) JP-A-1-17757 (JP, A) JP-A-2-82576 (JP, A) JP-A-63-177470 (JP) , A) JP-A-3-46373 (JP, A) JP-A-63-94684 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/78

Claims (2)

(57) [Claims] A step of preparing a P-type silicon substrate having a field region and an active region defined on a surface thereof; a step of forming a first oxide film in the active region; and performing ion implantation of P-type impurity at flight as the distance that the peak not <br/> pure concentration profile interface P-type oxide film was set to come in, the first oxide film removing, then, the so impurity concentration near the silicon substrate surface of the active region is lowered, forming a silicon by epitaxial growth on the active region, is the second oxide film on the active region Gate oxidation
Film, gate electrode, source / drain layer
And a step of manufacturing the N-channel MOSFET. 2. The method according to claim 1, wherein the formation of silicon by the epitaxial growth is performed in a di-silane atmosphere.