JPH05251695A - Manufacture of n-channel mosfet - Google Patents

Abstract

PURPOSE:To obtain the manufacture of N-channel MOSFET capable of reducing as much as possible the concentration of impurities on the surface of a substrate, capable of adjusting threshold voltage and creating short-channel effect by the formation of N-channel MOSFET equivalent to the conventional technique and also capable of creating a higher speed and a higher integration. CONSTITUTION:After forming an active region, an oxide film 13 is formed, a range distance is set in such a manner that the peak of profile will come to the interface of Si-SiO2, and then BF+ threshold voltage control ions are implanted. Thereafter, the oxide film 13 is removed, and silicon is formed in the active region by low temperature epitaxial growth. By taking this process, a profile formed will have an extremely low concentration of impurities at the shallow portion below the gate and a high concentration of impurities at a further deeper portion.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an N channel MOSFE.
The present invention relates to a T manufacturing method.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, there were the following. A method of manufacturing an N-channel MOSFET which is generally used at present will be described with reference to FIG.

First, as shown in FIG. 4A, a thick oxide film 2 is formed on a P-type silicon substrate 1 to form a field region,
After forming the active region, the gate oxide film 3 is grown in the active region. Next, as shown in FIG. 4B, in order to adjust Vt (threshold voltage), Vt control ion implantation is performed through the gate oxide film 3 in order to increase the impurity concentration in the silicon substrate under the gate. Then, ¹¹ B ⁺ ions are implanted into the silicon substrate.

Thereafter, as shown in FIG. 4C, a polysilicon film 4 is formed and a gate is formed by photolithography. Further, the source / drain 5 and 6 are formed by ion implantation and appropriate heat treatment. Next, FIG.
As shown in (d), an insulating film 7 is formed, contact holes are opened, and a wiring layer 8 is formed of aluminum or the like.

As a known technique in such a field,
For example, JP-A-61-292318 and JP-A-60-
-195928 can be mentioned.

[0006]

The N-channel MOSFET formed by the above manufacturing method is used.
An example of the impurity profile of is shown in FIG. The profile of ¹¹ B ⁺ ions implanted with Vt control has a peak at a depth according to the acceleration energy at the time of ion implantation. In ion implantation, the implanted impurities have a distribution around the peak, which is unavoidable. This increases the impurity concentration on the surface of the silicon substrate. Therefore, the driving force is reduced.

The reduction in driving force hinders the high speed operation of the MOSFET. However, omitting the Vt control ion implantation makes it impossible to adjust the Vt and increases the depletion layer width of the gate.
A short channel effect occurs in the SFET. Therefore, Vt control ion implantation cannot be omitted in order to achieve high integration.

For the above reasons, the high impurity concentration on the substrate surface due to the Vt control ion implantation greatly hinders the speedup of the integrated circuit. The present invention eliminates the above-mentioned problem of the reduction in driving force caused by the high impurity concentration on the surface of the silicon substrate, and thus minimizes the impurity concentration on the substrate surface, adjusts Vt, and shortens the short channel effect. Generation and N-channel MOS equivalent to conventional technology
It is an object of the present invention to provide a method for manufacturing an N-channel MOSFET that can be performed by forming an FET and that can achieve high speed and high integration.

[0009]

In order to achieve the above object, the present invention provides a method for manufacturing an N-channel MOSFET in which a field region and an active region are formed, an oxide film is formed in the active region, and a threshold voltage is formed. Control ion implantation is performed by adjusting the range distance thereof to the film thickness of the oxide film, the oxide film is removed, silicon is epitaxially grown at a low temperature, and a gate oxide film is formed in a wet O ₂ atmosphere at a low temperature. A silicon film is formed, a gate is formed by photolithography, source / drain ion implantation is performed, and a source / drain layer is formed by a low-temperature heat treatment.

[0010]

According to the present invention, as described above, in the manufacture of the N-channel MOSFET, after forming the active region, the oxide film is formed and the range distance is set so that the profile peak appears at the Si-SiO ₂ interface. Then, Vt control ion implantation is performed. After that, the oxide film is removed,
Silicon is formed in the active region by low temperature epitaxial growth. By taking this step, it is possible to form a profile in which the impurity concentration in the shallow portion under the gate is extremely low and the impurity concentration in the deep portion is high.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows an embodiment of the present invention N
FIG. 2 is a sectional view of the manufacturing process of the latter half of the N-channel MOSFET showing the embodiment of the present invention.

First, as shown in FIG. 1A, a field region and an active region are formed on a P-type silicon substrate 11 with a thick oxide film 12 of about 6000 Å as in the prior art. Next, as shown in FIG. 1B, an oxide film 13 having a film thickness of about 500Å is formed in the active region.

Next, as shown in FIG. 1 (c), the range distance is changed to Si-SiO ₂ for Vt control ion implantation.
According to the interface, 70Kev, dose 4.0x1
Ion implantation of ⁴⁹ BF ₂ ⁺ is performed at 0 ¹² / cm ² . Next, as shown in FIG. 1D, the oxide film 13 in the active region generated in FIG. 1B is removed by hydrofluoric acid.

Then, as shown in FIG. 1 (e), silicon is epitaxially grown to about 500 to 1000 Å in the active region in an atmosphere of disilane Si ₂ H ₆ at 700 ° C. to form an epitaxial layer 14. To do. Since this process is performed at a low temperature of 700 ° C., the process shown in FIG.
The diffusion of ion-implanted B ⁺ in (c) is small, and there is almost no influence on the impurity profile. Further, since silicon is formed by epitaxial growth, silicon is not generated on the field oxide film, but is selectively generated only on the active region.

Next, as shown in FIG. 2 (a), 850 ° C.
Gate oxide film 1 in wet O ₂ atmosphere at low temperature
5 is generated. Next, as shown in FIG. 2B, a polysilicon film 16 is formed and a gate is formed by photolithography. Further, the source / drain 17 and 18 are formed by ion implantation and heat treatment at an appropriate low temperature (for example, 850 ° C. or lower).

Next, as shown in FIG. 2C, the insulating film 1
9 is formed, the contact hole is opened, and the wiring layer 20 is formed of aluminum or the like. With this configuration, B
^{The +} ions do not diffuse into the silicon produced by epitaxial growth. FIG. 3 shows the concentration profile formed by the above steps. In this figure, the horizontal axis is the depth and the vertical axis is the impurity concentration (ions / c
m ³ ) is shown.

Compared to the profile in the prior art shown in FIG. 5, B ⁺ by Vt control ion implantation is compared.
The impurity concentration is extremely low in the portion shallower than the peak portion of the profile formed by the ions. This gives V
The decrease in driving force caused by the increase in impurity concentration due to the t control ion implantation is reduced. Further, the portion deeper than the peak portion is almost the same as that of the conventional technique. Therefore, the occurrence of the short channel effect is not so different from that of the prior art.

The present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and these modifications are not excluded from the scope of the present invention.

[0019]

As described above in detail, according to the manufacturing process of the present invention, as shown in FIG. 3, the impurity concentration in the vicinity of the substrate surface is very small, and the impurity concentration is deeper than that. It is possible to form an ideal profile which is preferable for both the driving force and the short channel effect.

Therefore, it is possible to manufacture an N-channel MOSFET which can be operated at high speed and can be highly integrated.

[Brief description of drawings]

FIG. 1 is an N-channel MOSFET showing an embodiment of the present invention.
FIG. 6 is a cross-sectional view of the main part manufacturing process of FIG.

FIG. 2 is a second half N-channel MOS showing an embodiment of the present invention.
It is a manufacturing process sectional view of FET.

FIG. 3 is a diagram showing an impurity profile of an N-channel MOSFET of the present invention.

FIG. 4 is a cross-sectional view of manufacturing steps of a conventional N-channel MOSFET.

FIG. 5 is a diagram showing an impurity profile of a conventional N-channel MOSFET.

[Explanation of symbols]

 11 P-type silicon substrate 12, 13 Oxide film 14 Epitaxial layer 15 Gate oxide film 16 Polysilicon film 17, 18 Source / drain 19 Insulating film 20 Wiring layer

Claims (4)

[Claims] 1. A field region and an active region are formed, (b) An oxide film is formed in the active region, (c) Threshold voltage control ion implantation is performed, and the range is set to the film thickness of the oxide film. (D) removal of the oxide film, (e) low temperature epitaxial growth of silicon, (f) generation of a gate oxide film in a wet O ₂ atmosphere at low temperature, and (g) removal of the polysilicon film. A method for manufacturing an N-channel MOSFET, characterized in that a gate is formed by photolithography etching, (h) source / drain ion implantation is performed, and a source / drain layer is formed by low-temperature heat treatment. 2. The N-channel MOSFET according to claim 1.
In the manufacturing method, the thickness of the oxide film formed in the active region is 500 to 1000Å, the threshold voltage control ion implantation conditions are BF ₂ ions, 70 to 150 Kev, and the oxide film thickness and the ion range are A method for manufacturing an N-channel MOSFET, which is characterized in that the same. 3. The N-channel MOS according to claim 1 or 2.
In the method of manufacturing the FET, the silicon is heated to about 700 ° C.
A method for manufacturing an N-channel MOSFET, which comprises epitaxially growing about 500 to 1000Å in a disilane atmosphere at a low temperature. 4. The N-channel MOS according to claim 1 or 2.
In the method of manufacturing an FET, the low-temperature heat treatment of the source / drain layers is performed at 850 ° C. or lower, and the method of manufacturing an N-channel MOSFET.