JPH05211328A - Mos transistor and manufacturing method thereof - Google Patents
Mos transistor and manufacturing method thereofInfo
- Publication number
- JPH05211328A JPH05211328A JP4007025A JP702592A JPH05211328A JP H05211328 A JPH05211328 A JP H05211328A JP 4007025 A JP4007025 A JP 4007025A JP 702592 A JP702592 A JP 702592A JP H05211328 A JPH05211328 A JP H05211328A
- Authority
- JP
- Japan
- Prior art keywords
- region
- drain
- source
- impurity concentration
- channel region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000012535 impurity Substances 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 150000002500 ions Chemical class 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims description 11
- 238000009792 diffusion process Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 229910052785 arsenic Inorganic materials 0.000 abstract description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052721 tungsten Inorganic materials 0.000 abstract description 3
- 239000010937 tungsten Substances 0.000 abstract description 3
- -1 arsenic ions Chemical class 0.000 abstract description 2
- 230000007423 decrease Effects 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000000137 annealing Methods 0.000 description 5
- 238000009826 distribution Methods 0.000 description 5
- 230000001133 acceleration Effects 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
- H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はＤＳＡ（ｄｉｆｆｕｓｉ
ｏｎ ｓｅｌｆ−ａｌｉｇｎｍｅｎｔ）型ＭＯＳ電界効
果トランジスタとその製造方法に関するものである。BACKGROUND OF THE INVENTION The present invention relates to DSA (diffusi).
on self-alignment) type MOS field effect transistor and its manufacturing method.
【０００２】[0002]
【従来の技術】ＭＯＳデバイスの高速化・高集積化にと
もない、ドレイン飽和電流を増大させることと、ドレイ
ン近傍の高電界で発生したアバランシェホットエレクト
ロンによるデバイス特性劣化の抑制とが重要な課題とな
っている。2. Description of the Related Art With the increase in speed and integration of MOS devices, it is important to increase drain saturation current and to suppress deterioration of device characteristics due to avalanche hot electrons generated in a high electric field near the drain. ing.
【０００３】このためチャネル領域の不純物濃度をソー
ス側で高く、ドレイン側に向って低くした構造が提案さ
れている。Therefore, a structure has been proposed in which the impurity concentration of the channel region is high on the source side and low on the drain side.
【０００４】さらにＤＭＯＳ（ＤＳＡ型）構造において
劣っていたしきい値電圧の制御性を向上させるため、チ
ャネル領域のソース近傍にドレイン側に向って不純物濃
度の変化が小さい局所チャネル領域が形成されているも
のがある。Further, in order to improve the controllability of the threshold voltage, which was inferior to the DMOS (DSA type) structure, a local channel region having a small change in impurity concentration toward the drain side is formed near the source of the channel region. There is something.
【０００５】図２に示すように、真性（π型）シリコン
基板１にフィールド酸化膜２、ゲート絶縁膜３およびゲ
ート電極４が形成され、ソース９端からドレインに向っ
てＤＳＡ領域５が形成されている。さらに層間絶縁膜１
１のコンタクト開口を通して金属配線１２が形成されて
いる。As shown in FIG. 2, a field oxide film 2, a gate insulating film 3 and a gate electrode 4 are formed on an intrinsic (π-type) silicon substrate 1, and a DSA region 5 is formed from a source 9 end to a drain. ing. Furthermore, the interlayer insulating film 1
The metal wiring 12 is formed through one contact opening.
【０００６】[0006]
【発明が解決しようとする課題】しきい値電圧はチャネ
ル領域のソース端の不純物濃度でほぼ決まるので、しき
い値電圧の制御性はかなり向上している。Since the threshold voltage is almost determined by the impurity concentration at the source end of the channel region, the controllability of the threshold voltage is considerably improved.
【０００７】ところが、例えばイオン注入によってチャ
ネル領域の不純物分布を形成したのち、熱処理によるア
ニール工程を避けることはできない。アニール工程にお
いて半導体基板とゲート絶縁膜との間で不純物が偏析し
たり、ドレイン方向に不純物が拡散する。そのためしき
い値電圧が変動したり、しきい値電圧のばらつきが大き
くなってしまう。However, after forming the impurity distribution in the channel region by, for example, ion implantation, the annealing process by heat treatment cannot be avoided. In the annealing process, impurities are segregated between the semiconductor substrate and the gate insulating film, or impurities are diffused in the drain direction. Therefore, the threshold voltage fluctuates or the threshold voltage varies greatly.
【０００８】本発明の目的は、しきい値電圧の制御性を
改善したＤＳＡ型ＭＯＳトランジスタの構造およびその
製造方法を提供することにある。An object of the present invention is to provide a structure of a DSA type MOS transistor with improved controllability of threshold voltage and a manufacturing method thereof.
【０００９】[0009]
【課題を解決するための手段】本発明のＤＳＡ型ＭＯＳ
トランジスタは、半導体基板表面にソース・ドレイン拡
散層、ゲート絶縁膜、、ゲート電極が形成され、チャネ
ル領域の不純物濃度がソース側で高く、ドレイン側に向
って低くなっていて、さらに前記チャネル領域のソース
近傍に不純物濃度がドレイン側に向って一定で、かつ前
記半導体基板表面から深さ方向に不純物濃度が次第に高
くなっている局所チャネル領域が形成されたものであ
る。Means for Solving the Problems The DSA type MOS of the present invention
In a transistor, a source / drain diffusion layer, a gate insulating film, and a gate electrode are formed on the surface of a semiconductor substrate, and the impurity concentration of the channel region is high on the source side and low on the drain side. A local channel region is formed near the source in which the impurity concentration is constant toward the drain side, and the impurity concentration gradually increases from the surface of the semiconductor substrate in the depth direction.
【００１０】本発明のＤＳＡ型ＭＯＳトランジスタの製
造方法は、半導体基板表面に形成されたゲート電極のソ
ース側にストッピングパワーの大きいマスク材からなる
側壁を形成する工程と、ソース拡散層直上からチャネル
領域に向って前記半導体前記半導体基板表面に斜めにイ
オン注入する工程とを含むものである。The method of manufacturing a DSA type MOS transistor of the present invention comprises a step of forming a side wall made of a mask material having a large stopping power on the source side of a gate electrode formed on the surface of a semiconductor substrate, and a channel immediately above the source diffusion layer. And ion-implanting the semiconductor obliquely into the surface of the semiconductor substrate toward the region.
【００１１】[0011]
【作用】ショックレーによるｇｒａｄｕａｌ ｃｈａｎ
ｎｅｌ近似によると、しきい値電圧はソース端の不純物
分布で決まる。チャネル領域のソース近傍において、ド
レインに向って不純物濃度が一定にしても、アニールな
どの熱処理工程の拡散によって、しきい値電圧が変動し
たり、ばらつきが大きくなることは避けられない。[Action] Gradual chan with Shockley
According to the nel approximation, the threshold voltage is determined by the impurity distribution at the source end. Even if the impurity concentration is constant toward the drain in the vicinity of the source in the channel region, it is unavoidable that the threshold voltage fluctuates or becomes large due to diffusion in a heat treatment step such as annealing.
【００１２】ＤＳＡＭＯＳのチャネル領域の不純物濃度
はソース側で高く、ドレイン側に向って低くなってい
る。そこでチャネル領域のソース近傍に不純物濃度がド
レイン側に向って一定で、しかも不純物濃度が基板表面
から深さ方向に次第に高くなったＶT 制御領域を設け
る。The impurity concentration of the channel region of the DSAMOS is high on the source side and low on the drain side. Therefore, in the vicinity of the source of the channel region, a V T control region is provided in which the impurity concentration is constant toward the drain side and the impurity concentration gradually increases from the substrate surface in the depth direction.
【００１３】ＶT 制御領域においては、熱処理工程で不
純物が横方向に拡散しても、より深い領域からチャネル
表面に不純物が拡散して、補償することができる。深さ
方向の濃度勾配を制御することにより、横方向の減少量
と深さ方向の補充量とを均衡させることができる。In the V T control region, even if the impurities diffuse laterally in the heat treatment process, the impurities can be diffused from the deeper region to the channel surface to compensate. By controlling the concentration gradient in the depth direction, the reduction amount in the lateral direction and the replenishment amount in the depth direction can be balanced.
【００１４】ゲート電極のソース側にストッピングパワ
ーの大きいマスク材を用いて斜めイオン注入することに
より、ＶT 制御領域を形成することができる。ＶT 制御
領域では、基板表面から深さ方向に向かって次第に不純
物濃度が高くなっている。By obliquely implanting ions on the source side of the gate electrode using a mask material having a large stopping power, the V T control region can be formed. In the V T control region, the impurity concentration gradually increases from the substrate surface in the depth direction.
【００１５】不純物濃度は、ソースからドレインに向っ
て一定で、イオンの入射方向の飛程に相当する深さでピ
ークとなるガウス分布となる。この不純物分布はチャネ
ル領域のソース端において、横方向に一定で縦方向に次
第に高くなる。The impurity concentration is constant from the source to the drain, and has a Gaussian distribution which has a peak at a depth corresponding to the range of ions in the incident direction. This impurity distribution is constant in the horizontal direction and gradually increases in the vertical direction at the source end of the channel region.
【００１６】[0016]
【実施例】本発明の一実施例について、図１（ａ）〜
（ｃ）を参照して説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to (c).
【００１７】はじめに図１（ａ）に示すように、真性
（π型）シリコン基板１にＬＯＣＯＳ選択酸化法により
フィールド酸化膜２を形成したのち、熱酸化して厚さ１
０ｎｍのゲート絶縁膜３を形成する。つぎにＣＶＤ法に
より厚さ５００ｎｍのポリシリコンを堆積したのち、フ
ォトレジスト（図示せず）をマスクとして選択エッチン
グして、ゲート長０．４μｍのゲート電極４を形成す
る。First, as shown in FIG. 1A, a field oxide film 2 is formed on an intrinsic (π-type) silicon substrate 1 by a LOCOS selective oxidation method and then thermally oxidized to a thickness of 1.
A gate insulating film 3 having a thickness of 0 nm is formed. Next, after depositing polysilicon having a thickness of 500 nm by the CVD method, selective etching is performed using a photoresist (not shown) as a mask to form a gate electrode 4 having a gate length of 0.4 μm.
【００１８】つぎにドレイン領域をフォトレジスト（図
示せず）で覆ったのち、ボロンを加速エネルギー３０ｋ
ｅＶ、注入量（ドース）２×１０13ｃｍー2イオン注入す
る。つぎにフォトレジストを除去したのち、１０００℃
の窒素雰囲気で１２０分間アニールして、ＤＳＡ領域５
を形成する。Next, after covering the drain region with a photoresist (not shown), boron is accelerated with an acceleration energy of 30 k.
eV, implantation amount (dose) 2 × 10 13 cm −2 ion implantation. Next, after removing the photoresist, 1000 ° C.
Annealing for 120 minutes in the nitrogen atmosphere of DSA region 5
To form.
【００１９】つぎに図１（ｂ）に示すように、イオン注
入のマスクとなる厚さ０．１μｍのタングステンからな
るサイドウォール６を形成したのち、フォトレジスト７
をパターニングする。つぎにソース予定領域直上からチ
ャネル領域に向って基板１表面に４５゜の角度で斜めイ
オン注入する。このときボロンを加速エネルギー６０ｋ
ｅＶ、注入量（ドース）２×１０13ｃｍー2イオン注入し
て、チャネル領域のソース端に不純物濃度がドレイン側
に向って高くなるＶT 制御領域８を形成する。Next, as shown in FIG. 1B, a sidewall 6 made of tungsten having a thickness of 0.1 μm to serve as a mask for ion implantation is formed, and then a photoresist 7 is formed.
Pattern. Next, oblique ion implantation is performed from directly above the planned source region toward the channel region on the surface of the substrate 1 at an angle of 45 °. At this time, the acceleration energy of boron is 60k.
eV, implantation dose (dose) 2 × 10 13 cm −2, and ion implantation is performed to form a V T control region 8 in which the impurity concentration increases toward the drain side at the source end of the channel region.
【００２０】つぎに図１（ｃ）に示すように、フォトレ
ジスト７を除去したのち、タングステンからなるサイド
ウォール６を硝酸溶液でエッチングする。つぎに砒素を
加速エネルギー７０ｋｅＶ、注入量（ドース）５．０×
１０15ｃｍ-2イオン注入してソース９、ドレイン１０を
形成すると同時に、ゲート電極４のポリシリコンに砒素
をドープする。つぎに９００℃の窒素雰囲気で２０分間
アニールして注入イオンを活性化する。Next, as shown in FIG. 1C, after removing the photoresist 7, the sidewalls 6 made of tungsten are etched with a nitric acid solution. Next, arsenic is accelerated at an acceleration energy of 70 keV and an implantation amount (dose) of 5.0 ×
At the same time as forming the source 9 and the drain 10 by ion implantation of 10 15 cm -2, the polysilicon of the gate electrode 4 is doped with arsenic. Next, the implanted ions are activated by annealing in a nitrogen atmosphere at 900 ° C. for 20 minutes.
【００２１】そのあと層間絶縁膜１１を堆積したのち、
コンタクトホールを開口し、金属配線１２を形成して素
子部が完成する。Then, after depositing the interlayer insulating film 11,
The contact hole is opened, the metal wiring 12 is formed, and the element portion is completed.
【００２２】本実施例において、チャネル領域の不純物
分布がソース側からドレイン側に向って次第に低くな
る。さらに、チャネル領域の不純物濃度がドレイン方向
に一定で、深さ方向に高くなるＶT 制御領域７が形成さ
れている。In this embodiment, the impurity distribution in the channel region gradually decreases from the source side toward the drain side. Further, a V T control region 7 is formed in which the impurity concentration of the channel region is constant in the drain direction and increases in the depth direction.
【００２３】そのため、熱処理工程によってソース端チ
ャネル領域の不純物が横方向に拡散しても、ＶT 制御領
域７のより深い領域から表面方向に不純物が拡散して補
償することができる。深さ方向の濃度勾配を調整するこ
とにより、横方向の減少量と深さ方向の補充量とを均衡
させることができる。Therefore, even if the impurities in the source end channel region are laterally diffused by the heat treatment process, the impurities can be diffused and compensated in the surface direction from the deeper region of the V T control region 7. By adjusting the concentration gradient in the depth direction, the reduction amount in the lateral direction and the replenishment amount in the depth direction can be balanced.
【００２４】本発明は、本実施例で述べたＮチャネルＭ
ＯＳトランジスタのほか、ＰチャネルＭＯＳトランジス
タを含む一般のＭＯＳデバイスに適用することができ
る。The present invention is based on the N channel M described in this embodiment.
It can be applied to general MOS devices including P-channel MOS transistors in addition to OS transistors.
【００２５】[0025]
【発明の効果】ＤＭＯＳにおいては、チャネル領域の不
純物濃度がソース側で高く、ドレイン側に向って低くな
っている。本発明では、さらにチャネル領域のソース近
傍に不純物濃度がドレイン側に向って一定で、しかも不
純物濃度が基板表面から深さ方向に次第に高くなったＶ
T 制御領域が形成されている。In the DMOS, the impurity concentration of the channel region is high on the source side and low on the drain side. In the present invention, the impurity concentration near the source in the channel region is constant toward the drain side, and the impurity concentration gradually increases from the substrate surface in the depth direction.
A T control region is formed.
【００２６】その結果、熱処理工程で不純物が横方向に
拡散しても、より深い領域からチャネル表面に不純物が
拡散して、補償することができる。深さ方向の濃度勾配
を制御することにより、横方向の減少量と深さ方向の補
充量とを均衡させることができる。As a result, even if the impurities diffuse laterally in the heat treatment step, the impurities can be diffused from the deeper region to the channel surface and compensated. By controlling the concentration gradient in the depth direction, the reduction amount in the lateral direction and the replenishment amount in the depth direction can be balanced.
【００２７】したがって、チャネル領域のソース端不純
物濃度によって決まるしきい値電圧が、熱処理工程に対
して安定になり、ばらつきも小さくなった。しきい値電
圧の制御性が飛躍的に向上した。Therefore, the threshold voltage determined by the impurity concentration at the source end of the channel region is stable with respect to the heat treatment process and the variation is small. The controllability of the threshold voltage is dramatically improved.
【図１】本発明の一実施例を工程順に示す断面図であ
る。FIG. 1 is a sectional view showing an embodiment of the present invention in the order of steps.
【図２】従来のＤＳＡ型ＭＯＳトランジスタを示す断面
図である。FIG. 2 is a sectional view showing a conventional DSA MOS transistor.
１ 真性シリコン基板 ２ フィールド酸化膜 ３ ゲート酸化膜 ４ ゲート電極 ５ ＤＳＡ領域 ６ サイドウォール ７ フォトレジスト ８ ＶT 制御領域 ９ ソース １０ ドレイン １１ 層間絶縁膜 １２ 金属配線11 Ｂ+ ボロンイオン1 Intrinsic Silicon Substrate 2 Field Oxide Film 3 Gate Oxide Film 4 Gate Electrode 5 DSA Region 6 Sidewall 7 Photoresist 8 VT Control Region 9 Source 10 Drain 11 Interlayer Insulation Film 12 Metal Wiring 11 B + Boron Ion
Claims (2)
層、ゲート絶縁膜、、ゲート電極が形成され、チャネル
領域の不純物濃度がソース側で高く、ドレイン側に向っ
て低くなっていて、さらに前記チャネル領域のソース近
傍に不純物濃度がドレイン側に向って一定で、かつ前記
半導体基板表面から深さ方向に不純物濃度が次第に高く
なっている局所チャネル領域が形成されたＤＳＡ型のＭ
ＯＳトランジスタ。1. A source / drain diffusion layer, a gate insulating film, and a gate electrode are formed on the surface of a semiconductor substrate, and an impurity concentration of a channel region is high on the source side and low on the drain side, and the channel is further formed. A DSA type M in which a local channel region is formed in the vicinity of the source of the region where the impurity concentration is constant toward the drain side and the impurity concentration is gradually increased in the depth direction from the surface of the semiconductor substrate.
OS transistor.
のソース側にストッピングパワーの大きいマスク材から
なる側壁を形成する工程と、ソース拡散層直上からチャ
ネル領域に向って前記半導体前記半導体基板表面に斜め
にイオン注入する工程とを含むＤＳＡ型のＭＯＳトラン
ジスタの製造方法。2. A step of forming a sidewall made of a mask material having a large stopping power on the source side of a gate electrode formed on the surface of the semiconductor substrate, and the semiconductor surface of the semiconductor substrate from directly above the source diffusion layer toward the channel region. A method of manufacturing a DSA type MOS transistor including the step of obliquely implanting ions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4007025A JPH05211328A (en) | 1992-01-20 | 1992-01-20 | Mos transistor and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4007025A JPH05211328A (en) | 1992-01-20 | 1992-01-20 | Mos transistor and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05211328A true JPH05211328A (en) | 1993-08-20 |
Family
ID=11654505
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4007025A Withdrawn JPH05211328A (en) | 1992-01-20 | 1992-01-20 | Mos transistor and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05211328A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0653795A2 (en) * | 1993-11-15 | 1995-05-17 | Motorola, Inc. | Double implanted laterally diffused MOS device and method thereof |
| US6071781A (en) * | 1996-07-15 | 2000-06-06 | Nec Corporation | Method of fabricating lateral MOS transistor |
| FR2796204A1 (en) * | 1999-07-07 | 2001-01-12 | St Microelectronics Sa | NMOS or PMOS, MOSFET transistor includes smaller third and fourth dopant pockets implanted in the channel, close to drain and source regions |
-
1992
- 1992-01-20 JP JP4007025A patent/JPH05211328A/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0653795A2 (en) * | 1993-11-15 | 1995-05-17 | Motorola, Inc. | Double implanted laterally diffused MOS device and method thereof |
| EP0653795A3 (en) * | 1993-11-15 | 1996-01-31 | Motorola Inc | Double implanted laterally diffused MOS device and method thereof. |
| US6071781A (en) * | 1996-07-15 | 2000-06-06 | Nec Corporation | Method of fabricating lateral MOS transistor |
| FR2796204A1 (en) * | 1999-07-07 | 2001-01-12 | St Microelectronics Sa | NMOS or PMOS, MOSFET transistor includes smaller third and fourth dopant pockets implanted in the channel, close to drain and source regions |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
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