JPH05335564A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To maintain impurities on retrograde by implanting ions of the same conductivity type as that of a substrate into the inside of the substrate after formation of a gate oxide film and a gate, and performing channel doping, and performing annealing for activation limitedly at low temperature and in a short time. CONSTITUTION:A polysilicon film 4 is grown as an electrode film all over the surface of a substrate. A high-concentration p-type layer 5 is formed by implanting B<+> ions into the surface of the polysilicon substrate 1. The polysilicon film 4 is patterned into a gate, and with the gate as a mask, a source 6 and a drain 7 are formed by implanting As<+> ions, and also the gate is doped with arsenic. A PSG film 8 is grown as a layer insulating film on the substrate. Next, by the RTA by lamp heating, the heat treatment at 900 deg.C and in a short time of 20 sec is performed on the substrate. In this case, since the heat treatment time is very short, the impurities having ions implanted are electrically activated, but rediffusion hardly occurs.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, and more particularly to a MOS FET manufacturing method. MOS FE in recent years
Although T has been miniaturized and the channel length has become shorter, the FET is required to have high current drive capability without punch-through breakdown due to this.

[0002]

2. Description of the Related Art Conventionally, semiconductor devices have been made faster and highly integrated by reducing the size of the elements mounted therein. However, when the channel length is reduced when the mounted element is a MOS FET, so-called short channel effects such as a decrease in threshold voltage V _{th and} a decrease in punch-through breakdown voltage occur, which hinders miniaturization of semiconductor devices. It was an obstacle.

The short channel effect is such that as the channel length is shortened, the ratio of the region occupied by the depletion layer extending from the source / drain to the entire channel region is increased, and the potential is mainly controlled not by the gate but by the drain. It is caused by becoming.

Therefore, when it is attempted to reduce the channel length while suppressing the short channel effect, the impurity concentration of the substrate, that is, the channel region is increased to suppress the extension of the depletion layer from the source / drain to be small. At that time, if the gate insulating film is thinned at a rate equal to the dimension reduction ratio of the normal channel length or at a ratio of -1/2 power, the short channel effect can be suppressed without increasing the threshold voltage.

However, if the impurities in the channel region are increased uniformly, the vertical electric field applied to the carriers in the channel increases. As a result, the carrier mobility decreases, the current does not increase to the extent that the size is reduced, and it is difficult to accelerate the speedup.

In addition, the channel length is 0.5 to 0.6 μm due to the demand for suppressing the decrease in reliability due to the hot carrier effect.
Power supply voltage V _DD is 5 V
It has come to be reduced to about 3.3 V. For this reason, the operating region above the threshold voltage, that is, V _DD −
In order to secure a current driving force by increasing V _th , a lower threshold voltage is required, and this tendency continues as device miniaturization progresses.

As described above, in order to solve the problem when the device is reduced in size by uniformly increasing the impurities in the channel region, the retrograde concentration distribution, that is, the source-drain junction which is apt to cause punch-through By forming an impurity distribution with a higher concentration near the same depth as above, the short channel effect is suppressed and the carrier mobility is kept high. Figure 2 shows a cross-sectional view of an FET with such a punch-through suppression structure.

In FIG. 2, 1 is a p-type semiconductor substrate, 2 is a field oxide film, 3 is a gate oxide film, 4 is a gate, and 5 is a gate oxide film.
Is a high concentration p-type layer. In this structure, the high-concentration p-type layer 5 is formed below the channel region.

[0009]

However, even if a retrograde concentration distribution is formed, in the conventional manufacturing method of channel doping by ion implantation and then forming the gate insulating film, the gate insulating film is formed. Since the oxidation process of film formation is generally at a high temperature, the impurity distribution immediately after implantation is destroyed by thermal diffusion, resulting in a uniform concentration distribution.

FIG. 3 is a diagram for explaining how the impurity distribution in the depth direction of the channel region changes due to gate oxidation. In the figure, (1) shows the concentration profile immediately after implantation, and (2) shows the concentration profile after gate oxidation.

Here, the high temperature of gate oxidation means that
This is mainly due to the requirement of reliability. This is
This is a serious problem in an n-channel MOS FET using boron having a large diffusion coefficient for channel doping, as compared with a p-channel MOS FET.

Furthermore, the use of a partial pressure oxidation method in which oxygen is diluted with an inert gas and oxidized at a higher temperature than normal thermal oxidation is more serious in gate oxidation. The oxide film formed by this partial pressure oxidation method has excellent insulating properties even when it is thinned, and is therefore becoming an important technology in the miniaturization of MOS FETs.

The present invention provides a manufacturing process for preserving a channel profile having a retrograde impurity distribution even if a high temperature gate oxidation process is included, suppressing the short channel effect of a MOS FET, and miniaturizing a semiconductor device. The purpose is to contribute to.

[0014]

[Means for Solving the Problems] 1)
A first step of forming a gate insulating film 3 on one conductivity type semiconductor substrate 1 and depositing a gate electrode film 4 on the entire surface of the gate insulating film, and then passing through the gate electrode film and the gate insulating film to form the semiconductor The second step of implanting one conductivity type impurity ions with energy such that an average projection range exists inside the substrate, and then, the distribution of the one conductivity type impurities in the depth direction has a maximum value inside the semiconductor substrate. And a second step of heat treating the semiconductor substrate at a temperature and for a time selected so that the concentration of the semiconductor substrate is kept lower than that, or 2) the second method This is achieved by the method for manufacturing a semiconductor device according to 1), which has a step of depositing a second gate electrode film on the entire surface of the gate electrode film after the step.

[0015]

According to the present invention, after the gate oxide film and the gate are formed, ions of the same conductivity type as the substrate are implanted with energy having an average projected range inside the substrate to perform channel doping, and impurities after the ion implantation are performed. The activation anneal is performed at a low temperature for a short time to maintain the retrograde impurity distribution.

Therefore, the ion-implanted impurities, which are deeply located to function as the punch-through stopper, are not redistributed.

[0017]

1 (A) to 1 (D) are sectional views for explaining an embodiment of the present invention. In FIG. 1 (A), a silicon dioxide (SiO ₂ ) film 2 is formed as a field oxide film that defines and exposes an element formation region on a silicon (Si) substrate 1 by a selective oxidation (LOCOS) method.
To form.

Next, for example, the substrate is thermally oxidized in a dry oxygen atmosphere at 850 ° C. to form a gate oxide film with a thickness of 5 nm.
The SiO ₂ film 3 is formed. Then, a 100 nm-thickness polysilicon film 4 is grown as a gate electrode film on the entire surface of the substrate by a vapor phase growth (CVD) method.

In FIG. 1B, boron ions (B ⁺ ) are implanted from the surface of the substrate under the conditions of an energy of 60 KeV and a dose amount of 5E12 cm ⁻² to form a high concentration p-type layer 5. When ion implantation is performed under these conditions, the high-concentration p-type layer 5 is almost zero from the substrate surface.
It has a peak at 1 μm and gradually becomes low concentration toward the surface.

In FIG. 1C, the polysilicon film 4 is patterned to form a gate, and the gate is used as a mask for arsenic ions (As ⁺ ) with an energy of 20 KeV and a dose of 4E15 cm ^-2.
Then, the source 6 and the drain 7 are formed and the gate is also doped with arsenic.

In FIG. 1 (D), a 300 nm-thick phosphosilicate glass (PSG) film is formed as an interlayer insulating film on the substrate by the CVD method.
The film 8 is grown. Next, rapid thermal annealing (RTA) using lamp heating, etc.
Heat treatment at ℃ for 20 seconds. In this case, since the heat treatment time is very short, the ion-implanted impurities are electrically activated, but re-diffusion hardly occurs.

Next, a contact hole 9 is formed in the PSG film 8, an aluminum (Al) wiring 10 is formed, and finally, a cover PSG film 11 is deposited thereon as a protective film to complete the process. In this embodiment, the case where the gate electrode film 4 is deposited in one step has been described. However, when it is desired to form the high-concentration p-type layer 5 into a steeper profile or deeper, the gate electrode film 4 is formed into two layers. Deposition is performed in batches. An example of this case is shown below.

A gate oxide film 3 is formed in the same manner as in the above embodiment, a first-layer gate electrode film is deposited to a film thickness of 20 nm, and boron ions are implanted under the conditions of an energy of 35 KeV and a dose amount of 5E12 cm ^-2 to obtain a high voltage. The concentration p-type layer 5 is formed. Then, a second-layer gate electrode film is deposited with a film thickness of 20 nm to form a gate with a total thickness of 100 nm.

In this case, since the gate electrode film can be formed at the same depth with a lower energy as compared with the case where the gate electrode film is formed once, the high-concentration p-type layer 5 is suppressed to have a small spread and has a steep impurity distribution. .

In the above embodiments, the case where the n-channel element is formed on the p-type substrate has been described, but the present invention can be applied to the case where the p-channel element is formed.

[0026]

According to the present invention, there is provided a manufacturing process for preserving a channel profile having a retrograde impurity distribution even if a high temperature gate oxidation process is included.
The purpose is to suppress the short channel effect of FET and contribute to miniaturization of semiconductor devices.

[Brief description of drawings]

FIG. 1 is a sectional view illustrating an embodiment of the present invention.

[Figure 2] Cross-sectional view of FET with punch-through suppression structure

FIG. 3 is a diagram for explaining how the impurity distribution in the depth direction of the channel region changes due to gate oxidation.

[Explanation of symbols]

1 Semiconductor substrate is Si substrate 2 Field oxide film is SiO ₂ film 3 Gate oxide film is SiO ₂ film 4 Gate electrode film is polysilicon film 5 High concentration p-type layer 6 Source 7 Drain 8 Interlayer insulation film is PSG film 9 Contact hole 10 Metal wiring and Al wiring 11 Cover PSG film

Claims (2)

[Claims] 1. A first step of forming a gate insulating film 3 on a one-conductivity-type semiconductor substrate 1 and depositing a gate electrode film 4 on the entire surface of the gate insulating film, and then the gate electrode film and the gate. A second step of implanting one conductivity type impurity ions at an energy such that an average projected range exists inside the semiconductor substrate through an insulating film; and And a third step of heat-treating the semiconductor substrate at a temperature and for a time selected so as to keep the concentration at the maximum value on the surface of the semiconductor substrate lower than that of the semiconductor substrate. Manufacturing method. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of depositing a second gate electrode film on the entire surface of the gate electrode film after the second step.