JPS6318346B2 - - Google Patents

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Publication number
JPS6318346B2
JPS6318346B2 JP53158092A JP15809278A JPS6318346B2 JP S6318346 B2 JPS6318346 B2 JP S6318346B2 JP 53158092 A JP53158092 A JP 53158092A JP 15809278 A JP15809278 A JP 15809278A JP S6318346 B2 JPS6318346 B2 JP S6318346B2
Authority
JP
Japan
Prior art keywords
layer
region
wafer
forming
oxide layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53158092A
Other languages
Japanese (ja)
Other versions
JPS5491187A (en
Inventor
Satoo Shuuichi
Yamaguchi Tadanori
Dagurasu Ritsuchii Aasaa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tektronix Inc
Original Assignee
Tektronix Inc
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Filing date
Publication date
Application filed by Tektronix Inc filed Critical Tektronix Inc
Publication of JPS5491187A publication Critical patent/JPS5491187A/en
Publication of JPS6318346B2 publication Critical patent/JPS6318346B2/ja
Granted legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
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    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66696—Lateral DMOS transistors, i.e. LDMOS transistors with a step of recessing the source electrode
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66704—Lateral DMOS transistors, i.e. LDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

Description

【発明の詳細な説明】 本発明は特に短チヤンネルの絶縁ゲート型電界
効果トランジスタを半導体基板上に超高密度で形
成する超LSIに適用して好適な半導体装置の製造
方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention particularly relates to a method of manufacturing a semiconductor device suitable for application to a super LSI in which short channel insulated gate field effect transistors are formed on a semiconductor substrate at an ultra high density.

例えば、MOS（金属−酸化物−半導体）電界効
果素子即ち、絶縁ゲート型電界効果トランジスタ
は、従来シリコンウエハ上面に形成しチヤンネル
領域で結合したソース及びドレイン領域を含んで
いる。ゲート電極をこのチヤンネル領域上に、酸
化物又はその他所望誘電体薄膜により絶縁して設
けている。ソース及びドレイン間の電流は、ゲー
ト電極に加える電圧により制御する。 For example, a MOS (metal-oxide-semiconductor) field effect device, or insulated gate field effect transistor, conventionally includes source and drain regions formed on the top surface of a silicon wafer and joined by a channel region. A gate electrode is provided over the channel region and insulated by a thin film of oxide or other desired dielectric. The current between the source and drain is controlled by the voltage applied to the gate electrode.

斯る素子の動作、即ち周波数応答又はスイツチ
ング速度等は、その素子の物理的寸法、特にチヤ
ンネル長に依存する。普通、MOS素子のチヤン
ネル長は、ソース及びドレイン領域の形成に使用
する写真製版及び不純物拡散工程により決まる。
従来技法では最高動作に要する充分短かいチヤン
ネルが形成できない。 The operation of such a device, ie frequency response or switching speed, etc., depends on the physical dimensions of the device, especially the channel length. Typically, the channel length of a MOS device is determined by the photolithography and impurity diffusion processes used to form the source and drain regions.
Conventional techniques cannot create channels short enough for maximum performance.

最近になつて、より高度動作用のMOS技法が
いくつか開発された。それらは、提案者によりＨ
−MOS（High Performance MOS：参考文献、
日経エレクトロニクス 1978年２月６日号58頁〜
59頁）と呼ばれている寸法を短縮したシリコンゲ
ートMOS工程、Ｖ−MOS（垂直MOS：参考文
献、日経エレクトロニクス1976年９月20日号）と
呼ばれているシリコンウエハに異方性エツチング
を用いてＶ字形溝を形成する二重拡散工程、及び
Ｄ−MOS若しくはDSA−MOS（Diffusion Self
−Aligned MOS：参考文献、日経エレクトロニ
クス1977年12月26日号）と呼ばれているプレーナ
構造の二重拡散工程である。これら各技法による
MOS素子はいずれもバイポーラ素子に近いスイ
ツチング速度を達成するが、いずれも種々の欠点
を有する。即ち、Ｈ−MOSは従来のプレーナ型
MOS素子の寸法とパラメータを縮尺したにすぎ
ないので、極めて微細なパターンを正確且つ再現
性を持つて製造できるか否かという製造メーカー
の能力に全面的に依存する。またＶ−MOS素子
の製造にはエピタキシヤル形成と異方性エツチン
グとの２つの相当高価な工程が必要である。更
に、Ｄ−MOSは同じマスクを介して行なうＮ型
及びＰ型不純物の一連の拡散によりチヤンネルが
決まるので、短チヤンネル長を再現的に製造する
為に精密な拡散源と優れた工程制御が不可欠であ
る。更にまた、Ｈ−MOS及びＤ−MOSは共にプ
レーナ処理である為に非プレーナ構造のＶ−
MOSの如き素子よりも広いウエハ面積を必要と
するので、高集積密度を必要とする場合には不適
当である。 Recently, several MOS techniques have been developed for more advanced operation. They are H
-MOS (High Performance MOS: References,
Nikkei Electronics February 6, 1978 issue page 58~
A silicon gate MOS process with reduced dimensions called V-MOS (vertical MOS: References, Nikkei Electronics September 20, 1976 issue) is an anisotropic etching process for silicon wafers. A double diffusion process is used to form a V-shaped groove, and a D-MOS or DSA-MOS (Diffusion Self
-Aligned MOS: This is a planar structure double diffusion process called Aligned MOS (Reference, Nikkei Electronics December 26, 1977 issue). With each of these techniques
Both MOS devices achieve switching speeds close to bipolar devices, but each has various drawbacks. In other words, H-MOS is a conventional planar type
Since it is merely a scaled version of the dimensions and parameters of the MOS device, it is entirely dependent on the manufacturer's ability to produce extremely fine patterns accurately and reproducibly. Additionally, the fabrication of V-MOS devices requires two fairly expensive steps: epitaxial formation and anisotropic etching. Furthermore, since the channel of D-MOS is determined by a series of diffusions of N-type and P-type impurities through the same mask, a precise diffusion source and excellent process control are essential to reproducibly manufacture short channel lengths. It is. Furthermore, since both H-MOS and D-MOS are planar processed, V-MOS with a non-planar structure
Since it requires a larger wafer area than devices such as MOS, it is unsuitable when high integration density is required.

従つて、本発明の目的は高周波及び高速動作特
性が得られる半導体装置、特に絶縁ゲート型電界
効果トランジスタの製造方法を提供することであ
る。 SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device, particularly an insulated gate field effect transistor, which provides high frequency and high speed operation characteristics.

本発明の他の目的は高密度集積に好適な絶縁ゲ
ート型電界効果トランジスタを有する半導体集積
回路の如き半導体装置及びその製法を提供するこ
とである。 Another object of the present invention is to provide a semiconductor device such as a semiconductor integrated circuit having an insulated gate field effect transistor suitable for high-density integration, and a method for manufacturing the same.

本発明の更に他の目的は従来の設備を用いて安
価且つ再現的に行なえる絶縁ゲート型電界効果ト
ンジスタ、或いはこれを有する半導体装置の製造
方法を提供することである。 Still another object of the present invention is to provide a method for manufacturing an insulated gate field effect transistor or a semiconductor device having the same, which can be performed inexpensively and reproducibly using conventional equipment.

本発明の着想は、就中イオン打込みにより半導
体基板を選択ドーピングするとき、イオン到達深
さが半導体基板表面の酸化物被膜の厚さにより変
化できることに基づくものである。従つて、連続
的に厚さが増加する酸化物層を設けると、同様に
深さが減少する薄い不純物層を打込むことができ
る。更に、このような基板面中に酸化物層を設け
ることにより、半導体面の傾斜部（斜面）で端部
が終了する上向きの埋込み不純物層が形成でき
る。この技法はチヤンネル長が打込んだ不純物層
の厚さにより決まるMOS素子の如き絶縁ゲート
型電界効果トランジスタの製造に使用できる。周
知のように、イオン打込みによると極めて薄い層
ができるので、従来のMOS素子よりも著るしく
短いチヤンネルを有する素子が作れる。 The idea of the present invention is based on the fact that when selectively doping a semiconductor substrate by ion implantation, the ion depth can be varied depending on the thickness of the oxide film on the surface of the semiconductor substrate. Thus, by providing an oxide layer of successively increasing thickness, a thin impurity layer of decreasing depth can be implanted as well. Further, by providing an oxide layer in the surface of such a substrate, an upwardly directed buried impurity layer can be formed whose end ends at the slope of the semiconductor surface. This technique can be used to fabricate insulated gate field effect transistors, such as MOS devices, where the channel length is determined by the thickness of the implanted impurity layer. As is well known, ion implantation produces extremely thin layers, which allows the creation of devices with significantly shorter channels than conventional MOS devices.

本発明の方法によると、酸素不透過膜より成る
マスクを半導体基板表面の選択した第１領域に形
成し、次いで選択的に酸化してマスクされなかつ
た部分に固着した酸化物層を形成する。この酸化
物層は対称的に傾斜した連続した端部、即ち「ピ
ーク」（鳥の口ばし状部分）が酸素不透過膜の端
縁とその下のマスクされた半導体基板間に延長形
成される。この酸素不透過膜を除去した後、第１
不純物の薄い領域を選択した第１表面領域の下の
基板に植込む。既に述べた通り、この植込み領域
は酸化工程で形成した基板表面の傾斜部で終了す
る上向きの端部を含んでいる。 According to the method of the present invention, a mask comprising an oxygen-impermeable film is formed on a selected first region of the surface of a semiconductor substrate and then selectively oxidized to form a layer of oxide that adheres to the unmasked portions. This oxide layer has a symmetrically sloped continuous edge or "peak" extending between the edge of the oxygen-impermeable film and the underlying masked semiconductor substrate. Ru. After removing this oxygen-impermeable film, the first
A thin region of impurity is implanted into the substrate below the selected first surface area. As already mentioned, this implanted region includes an upwardly directed end that terminates in the slope of the substrate surface formed by the oxidation process.

第１不純物領域の植込みにて素子のチヤンネル
を構成する上向きの端部を形成した後、反対導電
型の第２不純物を第１表面領域の半導体基板に設
ける。この反対導電型の表面領域をチヤンネル形
成領域に接して形成して素子のソース領域とす
る。絶縁酸化物層を除去し、チヤンネルを含む基
板表面部分の上にゲート絶縁被膜を形成する。こ
の反対導電型の不純物の他の表面領域を基板上に
形成して素子のドレイン領域となす。好ましく
は、このドレイン領域はチヤンネル領域から離間
して両者間にドリフト領域即ち低不純物濃度領域
を作る。最後に、ゲート絶縁被膜上にソース及び
ドレイン領域と接して所望電極を形成する。好適
な構成によると、ゲート電極はソース領域と僅か
に重なるが、ドレイン領域は覆わないので、ゲー
ト・ドレイン間静電容量を最少にする。チヤンネ
ル及びドレイン領域間の低不純物濃度領域によ
り、従来のプレーナ型MOS素子の場合より充分
に高い動作電圧で動作させることが可能になる。
更に、素子一部をマスクした基板表面の酸化期間
中に作られる傾斜部に設けることにより、使用す
る基板表面積が少なくなるので、大規模集積回路
（LSI）に適用する場合に極めて好適である。 After implanting the first impurity region to form an upward end forming a channel of the device, a second impurity of an opposite conductivity type is provided in the semiconductor substrate in the first surface region. This surface region of the opposite conductivity type is formed in contact with the channel forming region to serve as the source region of the device. The insulating oxide layer is removed and a gate insulating coating is formed over the portion of the substrate surface that includes the channel. Another surface region of the impurity of the opposite conductivity type is formed on the substrate to form the drain region of the device. Preferably, the drain region is spaced apart from the channel region to create a drift region or lightly doped region therebetween. Finally, desired electrodes are formed on the gate insulating film in contact with the source and drain regions. In a preferred configuration, the gate electrode slightly overlaps the source region but does not cover the drain region, thereby minimizing gate-to-drain capacitance. The low impurity concentration region between the channel and drain regions allows operation at a significantly higher operating voltage than in conventional planar MOS devices.
Furthermore, by providing a portion of the device on the slope formed during oxidation of the masked substrate surface, the surface area of the substrate used can be reduced, making it extremely suitable for application to large-scale integrated circuits (LSI).

以下、本発明の好適実施例を図面を参照して詳
細に説明する。先づ、第１ａ乃至ｆ図は本発明に
よるエンハンスメント型ｎ−MOSトランジスタ
を製造する各工程を経時的に示している。酸化物
膜１２と、窒化シリコン（Si3N4）が好ましい酸
素不透過膜１４とを、P-型不純物をドープした
約10Ω・cmの単結晶シリコンウエハ１０の上面に
形成する。この被膜１２及び１４は、従来周知の
技法により製造する。酸化物膜１２は約300乃至
600Åの厚さであり、典型的には約400Åである。
窒化膜は約0.1乃至0.2μｍであり、典型的には約
0.13μｍである。 Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. First, FIGS. 1a to 1f sequentially show each step of manufacturing an enhancement type n-MOS transistor according to the present invention. An oxide film 12 and an oxygen-impermeable film 14, preferably silicon nitride (Si 3 N 4 ), are formed on the top surface of a single crystal silicon wafer 10 doped with P - type impurities and having a thickness of about 10 Ω·cm. The coatings 12 and 14 are manufactured by techniques well known in the art. The oxide film 12 has a thickness of about 300 to
600 Å thick, typically around 400 Å.
The nitride film is approximately 0.1 to 0.2 μm thick, typically approximately
It is 0.13 μm.

次に、ウエハ１０の第１領域に窒化膜１４及び
酸化物膜１２を選択的にエツチング除去してマス
ク１６を形成する。ウエハ１０のマスクしなかつ
た部分は局部的に酸化し、ウエハ１０の平坦面上
に固着した厚い酸化膜１８を形成する（第１ｂ図
参照）。周知の通り、酸化物と窒化物でマスクし
たシリコン表面の局部酸化によると、酸素不透過
膜の縁部から、酸素不透膜下のウエハ上面に延び
て酸化物の「ビーク」２０ができる。このビーク
の形成については、フイリツプス・リサーチ・レ
ポート第26巻第３号157乃至165頁にわたり「シリ
コンの局部酸化」と題してＪ・Ｓ・アペル等によ
り説明されている。今まで酸化物ビークの形成は
邪魔物であると考えられて来た（例えばハヤサカ
等の発明に係る米国特許第4008107号参照）が、
本発明にあつてはこれらビークを積極的に活用
し、植込んだ不純物層の深さを変化させている。
膜１８は約1.5乃至3.0μｍの最大厚であるのが好
ましく、典型的には約2.0μｍであり、そのビーク
は滑らかにマスク１６の下の酸化膜１２の厚さに
なる傾斜を有するビーク２０となる。 Next, a mask 16 is formed by selectively etching away the nitride film 14 and oxide film 12 in the first region of the wafer 10. The unmasked portions of the wafer 10 are locally oxidized, forming a thick oxide film 18 that adheres to the flat surface of the wafer 10 (see FIG. 1b). As is well known, local oxidation of a silicon surface masked with oxides and nitrides creates oxide "beaks" 20 extending from the edge of the oxygen-impermeable film to the top surface of the wafer beneath the oxygen-impermeable film. The formation of this peak is explained by J.S. Appel et al. in Philips Research Report, Vol. 26, No. 3, pages 157 to 165, entitled "Local Oxidation of Silicon." Until now, the formation of oxide peaks has been considered to be a nuisance (see, for example, U.S. Pat. No. 4,008,107 to Hayasaka et al.);
In the present invention, these peaks are actively utilized to vary the depth of the implanted impurity layer.
The film 18 preferably has a maximum thickness of about 1.5 to 3.0 μm, typically about 2.0 μm, and has a beak 20 that slopes smoothly to the thickness of the oxide film 12 below the mask 16. becomes.

局部酸化工程に続いて、窒化膜１６を除去し、
フオトレジスト・マスク２２を第１表面領域の中
心部上に設ける。硼素が好ましいＰ型不純物の厚
さの薄い層２４を第１ｃ図に示す如くイオン打込
みによりウエハ１０内に植込む。周知の通り、シ
リコンと二酸化シリコン（SiO2）とのイオン透
過度は略同じであるので、植込層の上面はフオト
レジスト・マスク２２のある領域を除いてウエハ
の酸化物被膜の上面と略同一である。周知手法で
硼素イオンの透過を制御することにより、層２４
が局部酸化工程によりウエハ表面に形成された傾
斜部２８と交差するような深さにする。酸化層１
８の最大厚が約2μｍの場合には、約130キロ電子
ボルト（KeV）に加速した硼素イオンを使用す
ると約0.5μｍの深さに達し、図示の如く基板１０
の表面に略平行で傾斜部２８の約中間で略直交し
て交差する約0.13μｍの厚さの不純物層打ち込み
層２４ができる。硼素のドーズ量は、約２乃至８
×1012原子／cm2が好ましい。 Following the local oxidation process, the nitride film 16 is removed,
A photoresist mask 22 is provided over the center of the first surface area. A thin layer 24 of a P-type impurity, preferably boron, is implanted into the wafer 10 by ion implantation as shown in FIG. 1c. As is well known, silicon and silicon dioxide (SiO 2 ) have approximately the same ion permeability, so the top surface of the implanted layer is approximately the same as the top surface of the wafer's oxide film, except for the area where the photoresist mask 22 is located. are the same. layer 24 by controlling the permeation of boron ions using well-known techniques.
The depth is such that it intersects the sloped portion 28 formed on the wafer surface by the local oxidation process. Oxide layer 1
When the maximum thickness of the substrate 10 is about 2 μm, using boron ions accelerated to about 130 kiloelectron volts (KeV) will reach a depth of about 0.5 μm, as shown in the figure.
An impurity implantation layer 24 with a thickness of about 0.13 μm is formed, which is substantially parallel to the surface of the slanted portion 28 and intersects it substantially orthogonally at about the middle of the inclined portion 28 . The boron dose is approximately 2 to 8
×10 12 atoms/cm 2 is preferred.

シリコンウエハ１０内の層２４の部分は、ビー
ク２０の下部の傾斜部２８のまわりで途切れる
P+領域を形成する。この領域は、トランジスタ
のチヤンネル領域となり、イオン打込み工程の後
典型には約0.1乃至0.15μｍとなる。周知のよう
に、イオン打込みはシリコン結晶格子を破壊する
ので、その回復の為に層２４の打込み後、ウエハ
１０をアニール（焼きなまし）する。約900〜
1100℃、例えば約1000℃の如き適当な温度でアニ
ールすると、領域３０が僅かに拡散する。更に温
度を上昇すると、拡散によりチヤンネル形成領域
の厚さを増加するので必要に応じてこのアニール
時間及び温度を制御してチヤンネル幅を変化する
こともできる。このアニール後の領域３０の厚さ
は約0.2〜0.9μｍ典型的には0.4〜0.5μｍとなし得
る。 A portion of layer 24 within silicon wafer 10 breaks off around a slope 28 at the bottom of beak 20.
Form a P + region. This region becomes the channel region of the transistor and is typically about 0.1 to 0.15 μm after the ion implantation step. As is well known, ion implantation destroys the silicon crystal lattice, so wafer 10 is annealed after layer 24 is implanted to restore it. Approximately 900~
When annealing at a suitable temperature, such as 1100°C, for example about 1000°C, region 30 becomes slightly diffused. If the temperature is further increased, the thickness of the channel forming region increases due to diffusion, so the channel width can be changed by controlling the annealing time and temperature as necessary. The thickness of region 30 after this anneal may be about 0.2-0.9 .mu.m, typically 0.4-0.5 .mu.m.

次に、マスク２２を除去し、燐が好ましいｎ型
不純物を前述のウエハ１０の第１表面領域に導入
する。このｎ型不純物は、酸化物被膜にエツチン
グにより窓をあけた後従来手法で拡散できるが、
第１ｄ図に矢印３２で示すようにイオン打込みに
より不純物を打込むのが好ましい。加速電圧の調
整により燐イオンがウエハの台地領域３４上の薄
い酸化物膜１２を透過し、厚い酸化物層１８は透
過しないようにする。約100−200keVのエネルギ
ーでドーズ量約１乃至５×1015原子／cm2の打込み
により台地領域３４の表面に接して浅いn+領域
３６ができる。続いてウエハ１０を約900℃で20
分間アニールすることにより領域３６が拡散し、
平均深さが約0.4μｍのトランジスタのソース領域
となる。 The mask 22 is then removed and an n-type impurity, preferably phosphorous, is introduced into the first surface region of the wafer 10 described above. This n-type impurity can be diffused using conventional methods after etching a window in the oxide film.
Preferably, the impurities are implanted by ion implantation as shown by arrow 32 in FIG. 1d. Adjustment of the accelerating voltage allows phosphorus ions to pass through the thin oxide film 12 on the plateau region 34 of the wafer, but not through the thick oxide layer 18. A shallow n + region 36 is formed in contact with the surface of the plateau region 34 by implanting at an energy of about 100-200 keV and a dose of about 1 to 5.times.10.sup.15 atoms/ cm.sup.2 . Subsequently, wafer 10 was heated at approximately 900℃ for 20 minutes.
The region 36 is diffused by annealing for a minute;
This becomes the source region of the transistor with an average depth of about 0.4 μm.

膜１２及び層１８により形成した可変厚酸化物
層を完全に除去し、頂面３４及び底面４４よりな
る段状部を得る。次いで従来手段によりウエハ１
０の露出面上に二酸化シリコンを配し厚さ約1μ
ｍの酸化物層３８を形成する。層３８の選択した
部分４０をフオトエツチングにより除去して、傾
斜部２８上のこの部分４０にゲート構体を作る。
酸化物層のうちドレイン領域を形成するウエハ表
面の平坦部分４４上の選択した部分４２を同様に
除去する。このウエハの露出部分を酸化して部分
４０にゲート絶縁層としての薄いゲート酸化膜４
６を形成し、部分４２に酸化膜４８を形成する。
膜４６及び４８の厚さは約1000Åであるのが好ま
しい。この工程により得られた構成を第１ｅ図に
示している。 The variable thickness oxide layer formed by membrane 12 and layer 18 is completely removed, resulting in a step consisting of top surface 34 and bottom surface 44. Wafer 1 is then processed by conventional means.
Silicon dioxide is placed on the exposed surface of 0 to a thickness of approximately 1μ.
Form an oxide layer 38 of m. A selected portion 40 of layer 38 is photoetched away to create a gate structure at this portion 40 on ramp 28.
Selected portions 42 of the oxide layer on a flat portion 44 of the wafer surface that will form the drain region are similarly removed. The exposed portion of this wafer is oxidized to form a thin gate oxide film 4 as a gate insulating layer.
6 is formed, and an oxide film 48 is formed on the portion 42.
Preferably, the thickness of membranes 46 and 48 is about 1000 Å. The structure obtained by this step is shown in FIG. 1e.

次に、ウエハ上に窓４２を有するフオトレジス
トマスク層５０を形成する。n+ドレイン領域５
２を、第１ｆ図の矢印５１で示す如く酸化物被膜
を介してn-型の不純物を打込むことにより被膜
４８の下部のウエハ内に形成する。一例として、
約200keVのエネルギ及び約５×1015原子／cm2の
ドーズ量の燐を打込んでもよい。或いは、酸化物
被膜４８を除去してウエハ表面を露出させた後、
従来方法により拡散してドレイン領域５２を形成
してもよい。 Next, a photoresist mask layer 50 having windows 42 is formed over the wafer. n + drain region 5
2 is formed in the wafer below coating 48 by implanting n - type impurities through the oxide coating as shown by arrow 51 in FIG. 1f. As an example,
Phosphorus may be implanted at an energy of about 200 keV and a dose of about 5×10 15 atoms/cm 2 . Alternatively, after removing the oxide film 48 to expose the wafer surface,
Drain region 52 may be formed by diffusion using conventional methods.

フオトレジスト層５０を除去し、ウエハを約
1000℃で約20分間アニールし、イオン打込みによ
り生じた傷を回復させると共にドレイン領域を更
に深く拡散する。アニールした後、酸化物層３８
及び酸化物被膜４８をエツチングして開口を設
け、夫々ソース領域３６及びドレイン領域５２の
部分を露出させる。アルミニウムが好ましい金属
層をウエハの上面に真空蒸着させ、選択的にフオ
トエツチングによりソース電極５４、ゲート電極
５６及びドレイン電極５８を形成する。最後に、
好ましくは窒化シリコンの不活性化層６０を設け
て汚れを防止する。 The photoresist layer 50 is removed and the wafer is approximately
Annealing is performed at 1000°C for about 20 minutes to repair the scratches caused by ion implantation and to further diffuse the drain region. After annealing, the oxide layer 38
Then, oxide film 48 is etched to provide openings to expose portions of source region 36 and drain region 52, respectively. A metal layer, preferably aluminum, is vacuum deposited on the top surface of the wafer and selectively photoetched to form source electrode 54, gate electrode 56, and drain electrode 58. lastly,
A passivation layer 60, preferably silicon nitride, is provided to prevent contamination.

第１ｇ図に示す完成した半導体素子構造は、ウ
エハ１０の上面の台地上に形成したn+型のソー
ス領域３６を共用する一対のトランジスタ６２及
び６４を含んでいる。各トランジスタの薄く打込
んだP+チヤンネル領域３０はソース領域３６と
接し、台地（頂面）３４とウエハ表面の平坦部４
４とを結合する傾斜部２８と境界を接する端部を
有する。 The completed semiconductor device structure shown in FIG. 1g includes a pair of transistors 62 and 64 sharing an n + type source region 36 formed on a pedestal on the top surface of wafer 10. The thinly implanted P + channel region 30 of each transistor contacts the source region 36 and the plateau (top surface) 34 and the flat portion 4 of the wafer surface.
4 and has an end bounded by a sloped portion 28 joining 4.

本発明の要点は、このチヤンネル領域３０の端
部の厚さがトランジスタ６２，６４のチヤンネル
長を決定するということである。イオン打込み技
法により、非常に薄いチヤンネル領域３０が形成
できる。また、MOSトランジスタの周波数特性
はチヤンネル長に反比例するので、非常に高性能
なMOSトランジスタが形成できる。この傾斜部
表面の各領域３０の端部上に絶縁酸化物被膜４６
及びゲート電極５６より構成されたゲート構体を
設ける。 The gist of the invention is that the thickness of this end of channel region 30 determines the channel length of transistors 62,64. The ion implantation technique allows for the formation of very thin channel regions 30. Furthermore, since the frequency characteristics of a MOS transistor are inversely proportional to the channel length, a MOS transistor with very high performance can be formed. An insulating oxide coating 46 is formed on the end of each region 30 of this inclined surface.
A gate structure including a gate electrode 56 and a gate electrode 56 is provided.

更に、トランジスタ６２，６４はウエハ１０の
平坦表面上に設けたn+のドレイン領域５２を有
する。明らかな如く、ドレイン領域はチヤンネル
領域から離間しており、両者間に低不純物濃度の
ドリフト領域が存在する。このドリフフト領域に
より、ドレイン領域５２のチヤンネルと対向する
側の端縁に掛る電界を弱めることができ、此処に
おける耐圧の破壊を回避できると共に、ソース及
びドレイン間のパンチスルーを生じにくくするこ
とができて動作電圧が上昇でき且つソース・ドレ
イン間の静電容量を最小となす。更に、この低不
純物濃度領域（ドリフト領域）に設けた間隔によ
り、ゲート電極が充分長くできるので、ドレイン
領域と重なることなく充分に拡大できる。よつ
て、この構成はゲート・ドレイン間の望ましくな
い浮遊静電容量を最小となす。 Additionally, transistors 62 and 64 have n + drain regions 52 located on the planar surface of wafer 10. As is clear, the drain region is separated from the channel region, and a low impurity concentration drift region exists between the two. This drift region can weaken the electric field applied to the edge of the drain region 52 on the side opposite to the channel, making it possible to avoid breakdown of the withstand voltage here and making it difficult for punch-through to occur between the source and drain. This increases the operating voltage and minimizes the source-drain capacitance. Furthermore, the spacing provided in this low impurity concentration region (drift region) allows the gate electrode to be sufficiently long, so that it can be sufficiently expanded without overlapping with the drain region. This configuration thus minimizes undesirable stray capacitance between the gate and drain.

第２ａ−ｆ図は本発明の第２実施例によるｎ−
MOSトランジスタの製法を示す。n-型をドープ
したシリコンウエハ７０の上面に厚さ約1μｍの
SiO2層７２を形成する。この層７２をエツチン
グして拡散窓７４を形成し、この窓７４を通じて
ウエハ７０に硼素が好ましいＰ型不純物を選択的
に拡散してウエハ７０に高濃度のP+領域７６を
形成する。第２ａ図に示す如く、拡散期間中にウ
エハ７０の窓７４による露出表面に酸化物被膜が
出来る。この酸化物層及び被膜をウエハ７０から
完全に除去し、第１ａ図について説明した通り、
シリコンウエハの上面に二重のシリコン酸化膜−
窒化膜を形成する。次に、酸素不透過マスク７８
をこの二重層の選択除去により形成し、その後ウ
エハ７０のマスクしなかつた領域を局部的に酸化
して可変厚さの酸化層８０を形成する。第２ｂ図
に示す如く、層８０をウエハの上面に固着され、
マスク７８の縁部下に伸びる対称的に傾斜した酸
化物のビーク８２を有する。局部酸化期間中に領
域７６から硼素が深く拡散し、深いP+領域、即
ち井戸８４が図示の如くウエハ７０中に形成され
る。 Figures 2a-f show n- according to a second embodiment of the invention.
The manufacturing method of MOS transistor is shown. On the upper surface of the n - type doped silicon wafer 70, a layer with a thickness of about 1 μm is coated.
A SiO 2 layer 72 is formed. This layer 72 is etched to form a diffusion window 74 through which a P-type impurity, preferably boron, is selectively diffused into the wafer 70 to form a heavily doped P + region 76 in the wafer 70. As shown in FIG. 2a, an oxide film forms on the surface of wafer 70 exposed by window 74 during the diffusion period. This oxide layer and coating is completely removed from the wafer 70 and as described with respect to FIG. 1a.
Double silicon oxide film on top of silicon wafer
Form a nitride film. Next, the oxygen-impermeable mask 78
is formed by selective removal of this bilayer, and then the unmasked areas of wafer 70 are locally oxidized to form a variable thickness oxide layer 80. As shown in Figure 2b, a layer 80 is affixed to the top surface of the wafer;
Mask 78 has a symmetrically sloped oxide beak 82 extending below the edge. During the local oxidation, boron diffuses deeply from region 76 and deep P + regions, or wells 84, are formed in wafer 70 as shown.

次に、マスク７８を除去し、硼素の如きP-型
不純物の薄い層８６を、第２ｃ図に示す如く酸化
物ビーク８２の下部のウエハ表面の傾斜部で交差
るような深さで打込む。 Mask 78 is then removed and a thin layer 86 of P - type impurity, such as boron, is implanted to a depth that intersects the slope of the wafer surface below the oxide beak 82, as shown in FIG. 2c. .

第２ｄ図を参照し、次にフオトレジストマスク
９０を井戸８４を覆う酸化物層８０上に設ける。
このマスク９０の主な機能は井戸８４の導電度が
後続のn+ソース領域９２の形成期間中に基板表
面部分において減少するのを阻止することにあ
る。このソース領域は図中矢印９３で示す、燐の
如きn-型の不純物によるイオン衝撃により形成
するのが好ましい。 Referring to FIG. 2d, a photoresist mask 90 is then provided over the oxide layer 80 covering the wells 84.
The primary function of this mask 90 is to prevent the conductivity of the well 84 from decreasing at the surface of the substrate during the subsequent formation of the n + source region 92. This source region is preferably formed by ion bombardment with an n - type impurity such as phosphorus, as indicated by arrow 93 in the figure.

酸化物層８０をウエハ７０から除去し、厚さ約
1μｍのSiO2層９４をウエハ上面に設ける。この
層９４のうち傾斜８８上の部分を選択的にフオト
エツチングにより除去して絶縁ゲート形成部とな
す。この露出したウエハ７０の領域に約1000Åの
薄いゲート絶縁層としての酸化物被膜９６を成長
させる。酸化物層９４の他の部分は選択的に除去
して、ドレイン領域が形成される部分９８及び続
いてソース電極が形成される部分１００のウエハ
表面を露出する。部分９８に開口を有するフオト
レジスト層１０２をウエハに設け、その後燐が好
ましいｎ型の不純物を露出したウエハ表面に接し
て打込んでn+のドレイン領域１０４を形成する。
これにより得られる構成を第２ｅ図に示す。 Oxide layer 80 is removed from wafer 70 to a thickness of approximately
A 1 μm SiO 2 layer 94 is provided on the top surface of the wafer. A portion of layer 94 on slope 88 is selectively removed by photoetching to form an insulated gate formation portion. A thin gate insulating oxide film 96 of about 1000 Å is grown on the exposed area of wafer 70. Other portions of oxide layer 94 are selectively removed to expose the wafer surface at portion 98 where the drain region will be formed and subsequently at portion 100 where the source electrode will be formed. A photoresist layer 102 having an opening in portion 98 is provided on the wafer, and then an n-type impurity, preferably phosphorous, is implanted onto the exposed wafer surface to form an n + drain region 104.
The resulting configuration is shown in FIG. 2e.

フオトレジスト層１０２を除去し、ウエハをア
ニールした後、夫々ソース、ゲート及びドレイン
電極１０６，１０８及び１１０を従来手法で形成
する。最後に、SiO2又はSi3N4の不活性化層１１
２を設ける。第２ｆ図に示す完成したトランジス
タ構体は、高速スタテイツク ランダム アクセ
スメモリ（RAM）の構成として特に有効であ
る。又、このトランジスタ構体においては、低比
抵抗の井戸８４がチヤンネル領域８６と電極１０
６との間に設けられるので両者間の分布抵抗を小
さくできる利益がある。 After removing photoresist layer 102 and annealing the wafer, source, gate, and drain electrodes 106, 108, and 110, respectively, are formed using conventional techniques. Finally, a passivation layer 11 of SiO 2 or Si 3 N 4
2 will be provided. The completed transistor structure shown in Figure 2f is particularly useful as a high speed static random access memory (RAM) configuration. Also, in this transistor structure, a low resistivity well 84 connects the channel region 86 and the electrode 10.
6, there is an advantage that the distributed resistance between the two can be reduced.

本発明の第３の実施例によるシリコンゲート
MOSトランジスタの製造工程を第３ａ−ｃ図に
示す。このシリコンゲート素子の製法は最初第２
ａ〜ｃ図の説明と同様に行なう。よつて、第２ｃ
図の構成から始め、同様要素には同一参照符号を
附している。酸化物層８０をウエハ７０から除去
し、ウエハの非平坦面に薄い酸化物被膜１２０を
形成する。被膜１２０は約1000Åであるのが好ま
しい。好適厚さ約0.5μｍの単結晶シリコン層１２
２を従来手法で酸化物被膜１２０上に設け、第３
ａ図の構成を得る。 Silicon gate according to the third embodiment of the invention
The manufacturing process of the MOS transistor is shown in Figures 3a-c. The manufacturing method for this silicon gate device was initially
The procedure is similar to that described in figures a to c. Therefore, the second c.
Starting with the structure of the figures, similar elements are provided with the same reference numerals. Oxide layer 80 is removed from wafer 70 and a thin oxide coating 120 is formed on the non-planar surface of the wafer. Coating 120 is preferably about 1000 Å thick. Single crystal silicon layer 12 with a preferred thickness of about 0.5 μm
2 on the oxide film 120 by a conventional method, and the third
Obtain the configuration shown in figure a.

多結晶シリコンゲート電極１２４を層１２２の
選択フオトエツチングにより酸化物被膜１２０の
傾斜部に形成する。次に、フオトレジストマスク
層１２６を設ける。この層１２６はゲート電極及
び続いてn+のソース及びドレイン領域を形成す
るウエハ表面の酸化物被膜で覆われた領域が露出
する開口を有する。ソース領域１２８及びドレイ
ン領域１３０は第３ｂ図中に矢印１３２で示す如
く、燐又はその他のＰ型不純物のイオン打込みに
より形成する。マスクされない多結晶シリコンゲ
ート電極１２４の導電度は燐の打込みにより同時
に増加する。マスク層１２６を除去しウエハ７０
をアニールした後SiO2層１３４をウエハ全表面
に形成する。好ましくは厚さ約0.5μｍの酸化物層
１３４の部分、井戸８４上の酸化物被膜１２０の
対応部分、ソース領域１２８及びドレイン領域１
３０をフオトエツチングにより除去する。金属の
ソース及びドレイン電極１３６，１３８を夫々従
来手法で形成し、その後不活性被覆１４０を設け
る。最終的なシリコンゲートのMOSトランジス
タを第３ｃ図に示す。図から明らかなように、ゲ
ート構成以外は第２ｆ図のトランジスタ構成と本
質的に類似している。第１ｇ図の構造のシリコン
ゲート版も同様に製造できる 以上、本発明による半導体装置の製造方法を好
適実施例に基づき添付図を参照して説明した。し
かし、本発明は何ら斯る実施例のみに限定すべき
ではなく、本発明の要旨を逸脱することなく種々
の変形変更が可能であること当業者には容易に理
解できよう。 A polysilicon gate electrode 124 is formed on the slope of oxide film 120 by selective photoetching of layer 122. Next, a photoresist mask layer 126 is provided. This layer 126 has an opening exposing the oxide-covered areas of the wafer surface that will form the gate electrode and subsequently the n + source and drain regions. Source region 128 and drain region 130 are formed by ion implantation of phosphorous or other P-type impurities, as shown by arrows 132 in FIG. 3b. The conductivity of the unmasked polysilicon gate electrode 124 is simultaneously increased by the phosphorous implant. Mask layer 126 is removed and wafer 70 is removed.
After annealing, a SiO 2 layer 134 is formed on the entire surface of the wafer. A portion of oxide layer 134, preferably about 0.5 μm thick, a corresponding portion of oxide film 120 over well 84, source region 128 and drain region 1
30 is removed by photoetching. Metal source and drain electrodes 136, 138, respectively, are formed in a conventional manner, followed by an inert coating 140. The final silicon gate MOS transistor is shown in Figure 3c. As can be seen, the transistor configuration is essentially similar to that of FIG. 2f except for the gate configuration. A silicon gate version of the structure shown in FIG. 1g can be manufactured in a similar manner.The method for manufacturing a semiconductor device according to the present invention has been described above based on a preferred embodiment with reference to the accompanying drawings. However, the present invention should not be limited to these embodiments in any way, and those skilled in the art will easily understand that various modifications and changes can be made without departing from the gist of the present invention.

以上の説明から理解される如く、本発明の半導
体装置の製造方法によると、半導体基板の選択さ
れた部分に酸素不透過膜を被着して半導体基板の
選択酸化を行い、次に酸素不透過膜を除去して不
純物イオンを所定深さに打込むことを最大の特徴
としている。従つて、半導体装置の製造工程が極
めて簡単であり、しかも既存のMOSデバイスの
製造設備が使用でき、しかもチヤンネル長等が正
確に制御できるので、製品の歩留りが高いという
長所を有する。換言すれば、従来の製造工程は全
く邪魔ものと考えられていた局部酸化によるバー
ドビークを意図的且つ積極的に活用している。こ
れにより、チヤンネル幅を1μｍ以下と極めて短
くし、遅延時間を0.8〜1.3ns、相互コンダクタン
スgmを従来MOSデバイスの2.5〜３倍に高める
高性能半導体装置が得られるという著しい効果が
ある。 As can be understood from the above description, according to the method of manufacturing a semiconductor device of the present invention, selective oxidation of the semiconductor substrate is performed by depositing an oxygen-impermeable film on a selected portion of the semiconductor substrate, and then The main feature is that the film is removed and impurity ions are implanted to a predetermined depth. Therefore, the semiconductor device manufacturing process is extremely simple, existing MOS device manufacturing equipment can be used, and the channel length etc. can be accurately controlled, so the product yield is high. In other words, the bird's beak caused by local oxidation, which was considered to be a complete nuisance in the conventional manufacturing process, is intentionally and actively utilized. This has the remarkable effect of providing a high-performance semiconductor device with an extremely short channel width of 1 μm or less, a delay time of 0.8 to 1.3 ns, and a mutual conductance gm 2.5 to 3 times that of conventional MOS devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第１ａ−ｇ図は本発明の第１実施例による
MOS半導体素子の一連の製造工程を示す断面図、
第２ａ−ｆ図は本発明の第２実施例によるMOS
装置の一連の製造工程を示す断面図、第３ａ−ｃ
図は本発明の第３実施例によるシリコンゲート
MOS装置の製造工程を示す図である。 図中、１０，７０は半導体基板（ウエハ）、１
６は酸素不透過被膜のマスク、３４，４４は段状
部を形成し前者が頂面後者が底面をなす、２８，
８８は斜面、２０，８０は酸化層、３０，８６は
チヤンネル、４６，９６は絶縁層、５６，１０
８，１２４はゲート電極、３６，９２，１２８は
ソース電極、５２，１０４，１３０はドレイン電
極を夫々示す。 Figures 1a-g are according to a first embodiment of the invention.
A cross-sectional view showing a series of manufacturing steps for a MOS semiconductor device,
Figures 2a-f are MOS transistors according to a second embodiment of the present invention.
Cross-sectional views showing a series of manufacturing steps of the device, 3rd a-c
The figure shows a silicon gate according to a third embodiment of the present invention.
FIG. 3 is a diagram showing a manufacturing process of a MOS device. In the figure, 10 and 70 are semiconductor substrates (wafers), 1
6 is a mask with an oxygen-impermeable film, 34 and 44 form stepped portions, the former being the top and the latter being the bottom, 28,
88 is a slope, 20, 80 is an oxide layer, 30, 86 is a channel, 46, 96 is an insulating layer, 56, 10
8 and 124 are gate electrodes, 36, 92 and 128 are source electrodes, and 52, 104 and 130 are drain electrodes, respectively.

Claims (1)

【特許請求の範囲】[Claims] １ 半導体基板の表面の比較的薄い酸化物層上に
酸素不透過マスクを選択的に形成して上記酸化物
層の酸化を成長させ、上記マスク部において非平
坦となると共に上記マスクの端部の下部に一部食
い込み上記半導体基板表面に滑らかな斜面をなす
段状部を有する比較的厚い局部酸化層を形成する
工程と、上記マスクを除いた後上記酸化物層を介
して上記段状部の上記斜面と交差する深さに第１
導電形の不純物イオンを打込みチヤンネル領域を
形成する工程と、上記酸化物層を除去する工程
と、上記斜面の外側に絶縁層を介してゲートを形
成する工程と、上記段状部の上記斜面部の両端部
に第２導電形のソース及びドレイン各領域を形成
する工程とより成ることを特徴とする半導体装置
の製造方法。1. An oxygen-impermeable mask is selectively formed on a relatively thin oxide layer on the surface of a semiconductor substrate, and oxidation of the oxide layer is grown so that the mask portion becomes non-flat and the edges of the mask become uneven. forming a relatively thick local oxidation layer having a stepped portion that partially bites into the lower part and forming a smooth slope on the surface of the semiconductor substrate; and after removing the mask, forming a relatively thick local oxide layer through the oxide layer to The first at the depth intersecting the slope above.
forming a channel region by implanting conductive type impurity ions; removing the oxide layer; forming a gate on the outside of the slope via an insulating layer; and forming the slope of the stepped portion. 1. A method of manufacturing a semiconductor device, comprising the step of forming source and drain regions of a second conductivity type at both ends of the semiconductor device.
JP15809278A 1977-12-21 1978-12-18 Semiconductor and method of fabricating same Granted JPS5491187A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/862,715 US4217599A (en) 1977-12-21 1977-12-21 Narrow channel MOS devices and method of manufacturing

Publications (2)

Publication Number Publication Date
JPS5491187A JPS5491187A (en) 1979-07-19
JPS6318346B2 true JPS6318346B2 (en) 1988-04-18

Family

ID=25339135

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15809278A Granted JPS5491187A (en) 1977-12-21 1978-12-18 Semiconductor and method of fabricating same

Country Status (7)

Country Link
US (1) US4217599A (en)
JP (1) JPS5491187A (en)
CA (1) CA1119733A (en)
DE (1) DE2854073A1 (en)
FR (1) FR2412942A1 (en)
GB (1) GB2011170B (en)
NL (1) NL7811920A (en)

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US6603173B1 (en) 1991-07-26 2003-08-05 Denso Corporation Vertical type MOSFET
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Also Published As

Publication number Publication date
DE2854073A1 (en) 1979-07-12
NL7811920A (en) 1979-06-25
US4217599A (en) 1980-08-12
GB2011170B (en) 1982-06-30
JPS5491187A (en) 1979-07-19
GB2011170A (en) 1979-07-04
CA1119733A (en) 1982-03-09
FR2412942A1 (en) 1979-07-20

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