JP3254868B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device and, more particularly, to a structure and a method of manufacturing a semiconductor device which achieves both suppression of a short channel effect and improvement of operation speed in a fine insulated gate type semiconductor device. About.

[0002]

2. Description of the Related Art In an insulated gate semiconductor device, suppression of a short channel effect becomes a more important problem as the device becomes finer. In order to solve such a problem, various element structures have been proposed. Among them, a structure provided with an embedded punch-through stopper is considered promising as a structure capable of effectively suppressing the short channel effect, and has been partially put to practical use. However, by forming a buried type punch-through stopper layer, P
The impurity concentration near the junction depth of the ⁺ layer or the N ⁺ layer increases,
There is a disadvantage that the junction capacitance increases. In view of this, a method has been proposed in which a punch-through stopper layer is formed only immediately below a channel using a resist mask. (1993 S
ymposium on VLSI Technology Digest of Technical Pa
pers p.89) FIG. 9 shows a manufacturing process of a conventional semiconductor device. In FIG. 9, FIG. 9A shows an N-well in a semiconductor substrate 901.
After forming the L902 and the P-well 903, the device isolation region 904 is formed.
Is a step of forming FIG. 9B shows that the embedded punch-through stopper layers 905 and 906 are formed by N-well and P-well.
In this step, a gate oxide film 907 and a gate electrode 908 are formed in the respective wells. The buried type punch-through stopper layer is formed by ion-implanting an impurity having the same polarity as the well only in the vicinity immediately below the channel using a resist mask. FIG. 9C shows a step of forming a source / drain region, in which a P ⁻ layer 909 and an N ⁻ layer 910 are formed, a sidewall 911 is formed, and a P ⁺ layer 912 and an N ⁺ layer 913 are formed. It is.

[0003]

However, in the prior art, the impurity concentration near the junction depth of the P ⁺ layer or the N ⁺ layer forming the source / drain region increases due to the punch-through stopper layer, and the junction capacitance increases. Although the problem described above can be reduced to some extent, as the device becomes finer, the overlap between the source / drain region and the punch-through stopper layer caused by the problem of alignment accuracy cannot be ignored, and the punch-through stopper layer is formed only under the channel by self-alignment. There is a long-awaited need for such technology. 10 and 11 show an example of a characteristic diagram of a conventional semiconductor device. In FIG. 10, the horizontal axis represents the distance (unit: μm) from the gate end of the mask in the step of forming the buried punch-through stopper layer only directly below the channel with the resist mask. FIG. 3 is a diagram plotted in a direction from the gate end to the inside of the gate electrode. The vertical axis is ΔVth
Lmin (unit: μm) defined by L (gate length) where / な る L = 0.1 V / 0.1 μm. FIG.
In FIG. 1, the horizontal axis indicates the distance (unit: μm) from the gate end of the mask forming the buried punch-through stopper layer as in FIG. 10, and the vertical axis indicates the case where a ring oscillator is formed by these transistors. Shows the delay time per gate (unit: ps). It is to be noted that the gate length of the transistor is 0.25 μm for both pMOS and nMOS. 10 and 11, the distance X from the gate end of the mask for forming the buried type punch-through stopper layer is determined from the viewpoint of suppressing the short channel effect.
X> −0.06 μm, and from the viewpoint of reducing the gate delay time, X <+0.02 μm. (X <+0.02 μm is a necessary accuracy in consideration of the lateral spread at the time of ion implantation and the lateral diffusion due to heat treatment in a later step.) As a result, −0.0.
It is necessary that the accuracy of 06 μm <X <+0.02 μm be realized with good reproducibility over the entire surface of the wafer. Further, when the gate length is made finer than 0.25 μm, -0.06 μm
Accuracy higher than <X <+0.02 μm is required. Such an accuracy is a value that is almost impossible to realize by mask alignment.

Accordingly, the present invention is to solve such a problem and provides an element structure for forming a punch-through stopper layer only directly below a channel in a self-alignment manner, and a method of manufacturing the same.

[0005]

According to the present invention, there is provided a semiconductor device comprising: (1) a semiconductor substrate, a well of a first conductivity type formed in a predetermined region of the semiconductor substrate, and a source of an insulated gate semiconductor element. In a semiconductor device in which a second conductivity type impurity region forming a drain region is provided in the well, a region of a predetermined depth in the well immediately below the gate of the insulated gate semiconductor element has an impurity concentration lower than that of the well. A high-concentration first-conductivity-type impurity region is provided, and a second first-conductivity-type impurity region is formed in the second-conductivity-type impurity region. Impurity region, and the peak value of the impurity concentration is the second impurity region.
The conductive type impurity region and the second region near the junction depth of the well;
Wherein the impurity concentration is higher than the impurity concentration of the first conductivity type impurity region.

(2) The first first conductivity type impurity region provided in a region of a predetermined depth in the well immediately below the gate of the insulated gate semiconductor device is 2 × 10 ¹⁷ to 1 × 10
^It has a peak concentration of ¹⁸ (cm ^-3 ).

(3) A second impurity region of the first conductivity type provided in the impurity region of the second conductivity type has a depth of 5 × near the junction depth between the impurity region of the second conductivity type and the well. 10 ¹⁶ ~
It is characterized by having an impurity concentration of 1 × 10 ¹⁷ (cm ⁻³ ).

(4) The peak concentration of the first first conductivity type impurity region provided in the well immediately below the gate of the insulated gate semiconductor device is 0.02 outside the gate electrode end.
between the region and the gate electrode end of μm region entering 0.06μm inwardly, characterized in that cross the impurity concentration of ^{1 × 10 17 (cm -3)} .

The method of manufacturing a semiconductor device according to the present invention includes: (5) a step of forming a well made of a first conductivity type impurity in a predetermined region of a semiconductor substrate; and forming a gate insulating film of an insulated gate semiconductor element. A step of forming a buried high concentration region of the same conductivity type as the well, a step of forming a gate electrode in a predetermined shape, and introducing a defect using the gate electrode as a mask, and performing a heat treatment. The method is characterized by including at least a step of diffusing an impurity forming the buried high-concentration region and a step of forming a region made of a second conductivity type impurity forming a source / drain region.

(6) Using the gate electrode as a mask,
In the step of introducing a defect and diffusing impurities forming the buried high-concentration region by heat treatment, Si ⁺ or Ar ⁺ is ion-implanted to introduce the defect.

(7) The Si ⁺ is accelerated at an accelerating voltage of 50 to 10
At 0 keV, dose amount 1 × 10 ¹⁴ -5 × 10 ¹⁵ (cm ⁻² )
It is characterized by ion implantation.

(8) Using the gate electrode as a mask,
In the step of introducing defects and diffusing impurities forming the buried high concentration region by heat treatment,
It is characterized in that it is performed in an oxidizing atmosphere at about 800 ° C. to 950 ° C. for about 20 minutes to 1 hour.

(9) The buried high-concentration region contains at least arsenic.

(10) A step of forming a well made of impurities of the first conductivity type in a predetermined region of the semiconductor substrate, a step of forming a gate insulating film of the insulated gate semiconductor element, and a step of forming the same conductivity type as the well. Forming a buried-type high-concentration region, forming a gate electrode in a predetermined shape, performing thermal oxidation in an atmosphere containing water vapor, and diffusing impurities forming the buried-type high-concentration region. And forming at least a step of forming a source / drain region made of a second conductivity type impurity.

(11) In the step of performing the heat treatment to diffuse the impurities forming the buried high concentration region, the heat treatment is performed at 850 ° C. to 9 ° C. in an atmosphere containing water vapor.
It is characterized in that thermal oxidation is performed at about 50 ° C. for about 20 minutes to 1 hour.

(12) The buried high-concentration region contains at least arsenic.

[0017]

FIG. 1 is an example of a sectional view of a semiconductor device according to an embodiment of the present invention.

In FIG. 1, 101 is a semiconductor substrate, and 102 is N
A well 103 is a buried punch-through stopper layer formed only under the channel and made of an N-type impurity such as phosphorus (P) or arsenic (As), and is a region having a higher impurity concentration than the well (hereinafter, referred to as “well”). BN layer). Ten
4 is an N-type impurity layer made of the same element as the buried layer 103 formed near the surface of the P ⁺ layer, and the concentration of the N-type impurity is P ⁺
The surface concentration of boron (B) is set to be at least one digit lower than that of the layer. 105 is a gate insulating film, 106 is a gate electrode,
107 is a P ⁻ layer, 108 is a sidewall, and 109 is a P ⁺ layer.

As shown in FIG. 4 (described later), the peak concentration of the BN layer immediately below the channel is 2 × 10 ¹⁷ to 1 × 10 ^18.
(Cm ^-3 ) (The actual N-type impurity concentration is well
P ⁺
The impurity concentration of the BN layer near the junction depth of the layer should be at least 1
It should be less than about × 10 ¹⁷ (cm ⁻³ ). The area where the peak concentration of the BN layer immediately below the channel is 1 × 10 ¹⁷ (cm ⁻³ ) or less is defined as a 0.02 μm area outside the gate electrode end and the gate electrode for all transistors in the wafer. It is controlled so that it enters a region of 0.06 μm inside from the extreme. FIG. 4C shows this state (described later).

Although FIG. 1 shows a pMOS for simplicity, the present invention is also effective for an nMOS.

FIG. 2 is an example of a sectional view of a semiconductor device according to an embodiment of the present invention.

In FIG. 2, 201 is a semiconductor substrate, and 202 is P
-Well, 203 is formed only under the channel, B
Is a region in which the concentration of the P-type impurity is higher than the well (hereinafter, referred to as a BP layer). Reference numeral 204 denotes a P-type impurity layer formed of the same element as the buried layer 203 formed near the surface of the N ⁺ layer, and the concentration of the P-type impurity is at least one digit lower than the surface concentration of As or P in the N ⁺ layer. It is like. 205
Denotes a gate insulating film, 206 denotes a gate electrode, 207 denotes an N ⁻ layer, 208 denotes a sidewall, and 209 denotes an N ⁺ layer.

FIG. 3 is an example of a manufacturing process diagram of a semiconductor device according to an embodiment of the present invention.

FIG. 3A shows that Nw is embedded in a semiconductor substrate 301.
Cell 302 and P-well 303 are formed, and an element isolation region is formed.
This is a step of forming 304. The impurity concentration of the well is usually set to about 5 × 10 ^{16 to} 5 × 10 ¹⁷ (cm ⁻³ ), but by optimizing the buried type punch-through stopper layer, when the gate length is 0.25 μm, × 10
¹⁷ (cm ⁻³ ) or less, and even 2 × 10 ¹⁷ (cm ⁻³ ) even with a gate length of 0.15 μm. This is important in securing the driving capability of the transistor. FIG.
(B), a BN layer 306 and a BP layer 307 which form a gate insulating film 305 and form a buried punch-through stopper layer
Are formed in the N-well and the P-well, respectively.
After ion implantation for Vth control, the gate electrode 308
Is a step of forming The buried punch-through stopper layer is formed by ion-implanting impurities having the same polarity as the well. One example of the conditions for forming the BN layer is As ⁺
At an acceleration voltage of about 120 to 200 (keV) and a dose of 1
Ion implantation of about × 10 ^{12 to} 6 × 10 ¹² (cm ⁻² )
An N layer is formed. As one example of the conditions for forming the BP layer, BF ₂ ⁺ ions are implanted at an acceleration voltage of about 70 to 120 (keV) and a dose of about 1 × 10 ^{12 to} 6 × 10 ¹² (cm ⁻² ), To form FIG. 3 (c) shows an ion implantation of elements such as Si and Ar using the gate electrode as a mask, and point defects (vacancies, interstitial Si
And the like, followed by annealing in an oxidizing atmosphere or the like. By this annealing, of the BN layer and the BP layer formed over the entire surface in FIG. 3B, the impurity in the region where the defect is introduced is accelerated and diffused, and the peak of the impurity concentration existing immediately after the ion implantation is reduced. Then, a part thereof is piled up near the surface of the source / drain region to form an N-type impurity layer 309 and a P-type impurity layer 310 which are made of the same element as the BN layer 311 and the BP layer 312 left only under the channel. As a result, a well near the junction depth of the source / drain region is formed.
Can be lowered by self-alignment using the gate electrode as a mask. When the as an example the case where the Si ion implantation, Si ⁺ acceleration voltage dose 1 × 10 ¹⁴ ~5 × 10 ¹⁵ in 50~100keV (cm ^{- 2)} degree ion implantation. Subsequently, in an oxidizing atmosphere, 800 ° C. to 950
Anneal at about ° C for about 20 minutes to 1 hour. In the case of dry, an oxidation temperature of 850 ° C. to 950 ° C. is desirable, and in the case of wet, an oxidation temperature of 800 ° C. to 900 ° C. is desirable.
In an oxidizing atmosphere, diffusion of impurities is accelerated in a wet state compared to a dry state, and redistribution occurs more remarkably. FIG. 3 (d)
Is a step of forming source / drain regions, and the P ^- layer 3
After the formation of the 13 and N ⁻ layers 314, sidewalls 315 are formed, and P ⁺ layers 316 and N ⁺ layers 317 are formed. P ^- layer 316 and N
^- the junction depth of the layer 317 to optimize the ion implantation conditions and heat treatment conditions to be less than 0.15～0.20Myuemu.
In the embodiment shown in FIG. 3, after the gate electrode is processed into a predetermined shape, a point defect is introduced by ion implantation, and the impurity forming the punch-through stopper layer is diffused at an increased speed. Is not limited to this. For example, after forming the sidewall, a point defect may be introduced by ion implantation, and the impurity forming the punch-through stopper layer may be diffused at an increased speed. In this case, it is necessary to further diffuse the impurities forming the punch-through stopper layer immediately below the side wall edge to lower the impurity concentration near the junction depth.
It is more important to process with. Further, in the embodiment of FIG. 3, a case where a point defect is introduced by ion implantation and then accelerated diffusion in an oxidizing atmosphere is described as an example. However, such an impurity profile can be realized to some extent without ion implantation. Has also confirmed. For this purpose, after processing the gate electrode into a predetermined shape, the temperature is 850 ° C.
It is necessary to anneal at 950 ° C. for 20 minutes to 1 hour (in a dry atmosphere, particularly, redistribution of As hardly occurs). It can be suppressed to about three times or less.

FIGS. 4, 5 and 6 are examples of impurity profile diagrams in the embodiment of the present invention. FIG.
4 shows an impurity profile in a depth direction of a source / drain region. The impurity profile was analyzed by SIMS. 401 is the profile of As immediately after ion implantation, 402
Shows the profile of As after annealing. Reference numeral 403 denotes the profile of B of the P ⁺ layer forming the source / drain. FIG. 5 shows an impurity profile in the depth direction immediately below the channel. Reference numeral 501 denotes an As profile immediately after ion implantation, and reference numeral 502 denotes an As profile after annealing. As shown in FIG. 4 and FIG.
Although s is hardly redistributed by annealing, As in the source / drain region is largely redistributed due to enhanced diffusion caused by defects introduced by the ion implantation shown in FIG. It can be seen that the peak of the impurity concentration immediately after the implantation becomes broad due to the annealing and segregates near the surface of the Si substrate.
However, the concentration of As segregated in the vicinity of the surface (the impurity concentration of the well is not added) is suppressed to about 5 × 10 ¹⁸ (cm ⁻³ ) or less, which is at least one digit lower than the surface concentration of the P ⁺ layer. Can be controlled as follows. As a result, the peak concentration of the buried layer immediately below the channel is 2 × 10 ¹⁷ to 1 × 10 ¹⁸ (c
m ⁻³ ) and maintain the As ⁺ near the junction depth of the P ⁺ layer.
At least 5 × 10 ¹⁶ to 1 × 10 ¹⁷ (c
m ⁻³ ). As disclosed in the embodiment according to the present invention, elements such as Si and Ar are ion-implanted and defects (vacancies, vacancies,
If the manufacturing method of introducing interstitial Si or the like and subsequently annealing in an oxidizing atmosphere or the like is not used, the above-described A
Almost no redistribution of s occurs, and the As concentration near the junction depth of the P ⁺ layer cannot be reduced. Such control of the impurity profile has been made possible for the first time by the present invention.
According to the present invention, as shown in FIGS. 4 and 5, the peak concentration of the buried layer immediately below the channel is 2 × 10 ¹⁷ to 1 × 1.
While keeping the temperature at about 0 ¹⁸ (cm ⁻³ ), the concentration of the N-type impurity in the vicinity of the junction depth of the P ⁺ layer should be at least 5 × 10 ¹⁶ to 1 ×.
It can be about 10 ¹⁷ (cm ⁻³ ). FIG.
FIG. 9 shows a result of simulating a one-dimensional concentration distribution of As in the channel direction at a depth near the peak concentration of the BN layer. In FIG. 6, the horizontal axis indicates the distance (unit: μm) in the channel direction, and shows the case where the gate length is 0.25 μm with reference to the gate end on the source side of the transistor (0 μm). The vertical axis represents the impurity concentration of As (unit: cm ^-3 ).
Is shown. As a result of reproducing variations in the manufacturing conditions on a simulation, the peak concentration of the buried layer immediately below the channel (the peak concentration at the center of the channel is 2 × 10 ^{17 to} 5 × 1)
0 ¹⁷ (cm ⁻³ )) is 1 × 10 ¹⁷ (cm ⁻³ ) or less, for all transistors within the wafer surface and between the wafers, a region of 0.017 inward from the gate electrode end.
It was confirmed that control could be performed so as to be in the range of 2 to 0.06 μm. The peak concentration of the buried layer immediately below the channel (the peak concentration at the center of the channel is 5 × 10 ¹⁷ to 5 × 10 ¹⁷ ).
1 × 10 ¹⁸ (cm ⁻³ ) is 1 × 10 ¹⁷ (cm ⁻³ )
The following regions are from 0.02 μm outward from the gate electrode end to 0.04 μm inward from the gate electrode end for all transistors in the wafer plane and between the wafers.
It was confirmed that it could be controlled to enter the entered area. This is a value that cannot be obtained by ion implantation using a conventional resist mask, and is possible for the first time by a self-alignment method using a gate electrode as a mask according to the present invention. FIG.
6 shows an example of a BN layer made of As, but the present invention is extremely effective also for a BN layer made of P and a BP layer made of B, and an element such as Si or Ar is ion-implanted. Point defects (vacancies,
By introducing interstitial Si or the like and subsequently annealing in an oxidizing atmosphere or the like, the impurity profile of P or B can be controlled in substantially the same manner as As. Conventionally, a phenomenon in which B is redistributed in the oxidation step of the gate electrode has been reported (IEDM '87, p. 632), but no remarkable redistribution of B as described in the present invention has been reported. Further, there is no report on redistribution of P and As, and according to the present invention, point defects (vacancies, interstitial Si, etc.) are introduced into the Si substrate except immediately below the gate, followed by annealing in an oxidizing atmosphere or the like. It became possible for the first time. As described above, according to the present invention, the peak concentration of the buried punch-through stopper layer immediately below the channel is 2 × 10 ¹⁷ to 1 × 10 ¹⁸ (cm ⁻³ ).
While keeping the impurity concentration of the punch-through stopper layer near the source / drain junction depth at least 5 × 10 ¹⁶
It has become possible to make it about 1 × 10 ¹⁷ (cm ⁻³ ).
Further, the impurity concentration in the lateral direction is set to 2 × 10 5
1 × 10 ¹⁷ (c- ³ ) while maintaining the density at ¹⁷ to 1 × 10 ¹⁸ (cm ⁻³ ).
m ⁻³ ) or less, for all transistors within the wafer surface and between the wafers, a region from 0.02 μm outside the gate electrode end to 0.06 μm inside the gate electrode from the gate end. It became possible to control it.

FIG. 7 shows a characteristic diagram of a semiconductor device in an embodiment according to the present invention. In FIG. 5, the horizontal axis is pMO
S indicates the gate length (unit: μm), and the vertical axis indicates the threshold voltage V
th (unit: V). 701 shows the characteristics of a pMOS having a BN layer formed immediately below a channel according to the present invention;
702 indicates the characteristics of a pMOS without a BN layer, and 703 indicates
Shows the characteristics of a pMOS in which a BN layer is provided on the entire surface. FIG.
As shown in FIG. 7, it can be seen that the short channel effect is greatly improved by providing the BN layer only directly below the channel, as compared with the pMOS without the BN layer. Further, by forming the BN layer only immediately below the channel, the BN layer is formed on the entire surface.
It can also be seen that the effect is almost the same as that of the pMOS having the layer formed. In the pMOS having the BN layer formed on the entire surface, the junction capacitance between the P ⁺ layer and the N-well is 1.
Although it is as large as about 3 to 1.5 (fF / μm ² ), in the pMOS of the present invention, since the impurity concentration near the junction depth can be reduced, the junction capacitance between the P ⁺ layer and the N-well is reduced to 0.1.
It can be reduced to about 5 to 0.8 (fF / μm ² ). As a result, the junction capacitance can be reduced to about 1/2 to 1/3 of the conventional one while the short channel effect is sufficiently suppressed, and the operation speed is greatly increased and stabilized as shown in FIG. Was achieved.

FIG. 8 shows a characteristic diagram of a semiconductor device in an embodiment according to the present invention. In FIG. 8, the vertical axis represents the delay time per gate of the ring oscillator (unit: p).
s). Reference numeral 801 denotes the characteristics of the CMOS semiconductor device according to the present invention, and reference numeral 802 denotes the characteristics of the CMOS semiconductor device in which the punch-through stopper layer is formed only immediately below the channel using the conventional resist mask. Note that the error bar in the figure indicates the variation in the delay time, and the X mark indicates the average value.
According to the present invention, it can be seen that the operation speed of the element is increased and, at the same time, the variation is greatly reduced. Note that the characteristics shown in FIG. 8 exemplify the case where the gate length is 0.25 μm for both pMOS and nMOS.

The present invention is not limited to the embodiment shown in FIGS. 1 to 8, and can be widely applied to insulated gate semiconductor devices in general.

[0029]

According to the present invention, the peak concentration of the buried layer immediately below the channel is 2 × 10 ¹⁷ to 1 × 10 ¹⁸ (c
m ⁻³ ), the impurity concentration near the junction depth of the diffusion layer forming the source / drain region should be at least 5 × 10
It has become possible to reduce it to about ¹⁶ to 1 × 10 ¹⁷ (cm ⁻³ ). If the manufacturing method of ion-implanting elements such as Si and Ar, introducing defects (vacancies, interstitial Si, etc.) into the Si substrate except immediately below the gate, and subsequently annealing in an oxidizing atmosphere or the like is not used, the above-described method is used. The impurity redistribution as described above hardly occurs, and the impurity concentration in the vicinity of the junction depth of the diffusion layer cannot be reduced. Such control of the impurity profile has been made possible for the first time by the present invention. The peak concentration of the buried layer immediately below the channel is 1 × 10 ¹⁷ (cm ⁻³ ).
The following region was set to 0.02 to 0.06 inward from the gate electrode end for all transistors in the wafer.
It can be controlled so as to be in the area of μm. This is a value that cannot be obtained by ion implantation using a conventional resist mask, and is possible for the first time by a self-alignment method using a gate electrode as a mask according to the present invention.

As a result, while the short channel effect is largely suppressed, the junction capacitance between the diffusion layer forming the source / drain and the well is reduced to 1.3 to 1.0.1 when the buried punch-through stopper layer is formed on the entire surface. What was about 5 (fF / μm ² ) can be reduced to about 0.5 to 0.8 (fF / μm ² ), and the junction capacitance can be reduced to about 1/2 to 1/3 of the conventional one. It has become possible.

In the case where a buried type punch-through stopper layer is formed only immediately below a channel by a resist mask, if the element is miniaturized, the overlap between the source / drain region and the punch-through stopper layer cannot be ignored due to the problem of alignment accuracy. However, according to the present invention, since the impurity profile can be controlled by the self-alignment method, the suppression of the short channel effect and the improvement of the operation speed (reduction of the junction capacitance) can be reproducibly compatible, and the operation speed is greatly increased and its variation is improved. Was able to be reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a manufacturing process diagram of the semiconductor device according to the embodiment of the present invention.

FIG. 4 is an impurity profile diagram in the example of the present invention.

FIG. 5 is an impurity profile diagram in the example of the present invention.

FIG. 6 is an impurity profile diagram in the example of the present invention.

FIG. 7 is a characteristic diagram of a semiconductor device in an example according to the present invention.

FIG. 8 is a characteristic diagram of a semiconductor device in an example according to the present invention.

FIG. 9 is a manufacturing process diagram of a conventional semiconductor device.

FIG. 10 is a characteristic diagram of a conventional semiconductor device.

FIG. 11 is a characteristic diagram of a conventional semiconductor device.

[Explanation of symbols]

101,201,301 ... Semiconductor substrate 102,302 ... N-well 202,303 ... P-well 103,203 ... Embedded punch-through stopper layer 306 ... BN layer 307 ... BP layer 104,309 ... N-type impurity layer 204,310 ··· P-type impurity layer 105,205,305 ··· Gate insulating film 106,206,308 ··· Gate electrode 107,311 ··· P ^- layer 109,314 ··· P ⁺ layer 207,312 ··· N ^- layer 209,315 ··· N ⁺ layer

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8238 H01L 21/336 H01L 27/092 H01L 29/78

Claims (12)

(57) [Claims] A semiconductor substrate, a well of a first conductivity type formed in a predetermined region of the semiconductor substrate, and a second conductivity type impurity region forming a source / drain region of an insulated gate semiconductor device. In the semiconductor device provided above, an impurity region of a first first conductivity type having a higher concentration than the impurity concentration of the well is formed in a region of a predetermined depth in the well immediately below the gate of the insulated gate semiconductor element. Provided, and
A second first conductivity type impurity region made of the same element as the impurity region provided immediately below the gate is provided in the second conductivity type impurity region, and the peak value of the impurity concentration is the second conductivity type. A semiconductor device having a higher impurity concentration than the impurity region of the second first conductivity type near the junction depth of the impurity region and the well. 2. The semiconductor device according to claim 1, wherein said first first conductivity type impurity region provided in a region of a predetermined depth in said well immediately below a gate of said insulated gate semiconductor device is 2 × 10 ¹⁷ to 1 × 10 ^18. (C
2. A peak concentration of ^m.sup.-3 ).
13. The semiconductor device according to claim 1. 3. A second conductive type impurity region provided in the second conductivity type impurity region.
Is approximately 5 × 10 ¹⁶ to 1 × 10 5 near the junction depth of the well of the second conductivity type and the well.
3. The semiconductor device according to claim 1, wherein the semiconductor device has an impurity concentration of ¹⁷ (cm ^-3 ). 4. A region in which a peak concentration of a first first conductivity type impurity region provided in the well immediately below a gate of the insulated gate semiconductor device is 0.02 μm outward from an end of a gate electrode, and a gate electrode is formed. 4. The semiconductor device according to claim 1, wherein the impurity concentration crosses an impurity concentration of 1 × 10 ¹⁷ (cm ⁻³ ) in a region of 0.06 μm inside from the extreme. 5. A step of forming a well made of a first conductivity type impurity in a predetermined region of a semiconductor substrate, a step of forming a gate insulating film of an insulated gate semiconductor device, and embedding of the same conductivity type as the well. Forming a high-concentration region of the mold, forming a gate electrode in a predetermined shape, introducing defects using the gate electrode as a mask, and diffusing impurities forming the high-concentration region of the buried type by heat treatment. A method for manufacturing a semiconductor device, comprising at least a step and a step of forming a region made of a second conductivity type impurity that forms a source / drain region. 6. In the step of introducing a defect using the gate electrode as a mask and diffusing impurities forming the high-concentration region of the buried type by heat treatment, ions are implanted with Si.sup. ⁺ Or Ar.sup. ⁺ To introduce the defect. 6. The method for manufacturing a semiconductor device according to claim 5, wherein: 7. The method according to claim 7, wherein said Si ⁺ is supplied with an acceleration voltage of 50 to 100 keV.
7. The method according to claim 6, wherein ions are implanted at a dose of 1 × 10 ^{14 to} 5 × 10 ¹⁵ (cm ⁻² ). 8. In the step of introducing a defect using the gate electrode as a mask and diffusing impurities forming the high-concentration region of the buried type by heat treatment, the heat treatment is performed at about 800 ° C. to 950 ° C. in an oxidizing atmosphere. 8. The method for manufacturing a semiconductor device according to claim 5, wherein said step is performed for about one minute to one hour. 9. The method for manufacturing a semiconductor device according to claim 5, wherein said buried type high concentration region contains at least arsenic. 10. A step of forming a well made of a first conductivity type impurity in a predetermined region of a semiconductor substrate, a step of forming a gate insulating film of an insulated gate semiconductor device, and embedding of the same conductivity type as the well. Forming a high-concentration region of the mold, forming a gate electrode into a predetermined shape, performing thermal oxidation in an atmosphere containing water vapor, and diffusing impurities forming the high-concentration region of the buried type. A method for manufacturing a semiconductor device, comprising at least a step of forming a region made of a second conductivity type impurity that forms a source / drain region. 11. The step of performing the heat treatment to diffuse impurities forming the high concentration region of the buried type, the heat treatment is performed at about 850 ° C. to 950 ° C. for about 20 minutes to 1 hour in an atmosphere containing water vapor. The method for manufacturing a semiconductor device according to claim 10, wherein oxidation is performed. 12. The method for manufacturing a semiconductor device according to claim 10, wherein said buried high-concentration region contains at least arsenic.