JPH07183392A - Semiconductor device and fabrication thereof - Google Patents

Abstract

PURPOSE:To suppress the short channel effect while enhancing the operating speed by providing a first conductivity type impurity region of specified depth immediately below a gate and setting the peak value of impurity concentration thereof higher than that of a first conductivity type impurity region provided in a second conductivity type impurity region. CONSTITUTION:An N-Well 102 is formed on a semiconductor substrate 101 and a punch through stopper layer (BN layer) 103 of N-type impurities, e.g. phosphorus or arsenic, is buried immediately below a channel. The impurity concentration thereof is set higher than that of the N-Well 102. The impurity concentration of an N-type impurity layer 104, composed of same element as the BN layer 103 and formed closely to the surface of a P<+> layer 109, is set lower by one order or more than the concentration of boron on the surface of the P<+> layer 109. The peak value of impurity concentration in the BN layer 103 immediately below the channel is sustained in the range of 2X10<17>-1X10<18> (cm<-3>) and the impurity concentration of the BN layer 103 in the vicinity of junction with the P<+> layer is set at 1X10<17>(cm<-3>) or less.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a structure and manufacturing method of a fine insulated gate type semiconductor element which can both suppress a short channel effect and improve an operating speed. Regarding

[0002]

2. Description of the Related Art In an insulated gate semiconductor device, the miniaturization of the device makes it more important to suppress the short channel effect. Therefore, various element structures have been proposed in order to solve such problems. Among these, the structure provided with the embedded punch-through stopper is promising as a structure capable of effectively suppressing the short channel effect, and is partially put into practical use. However, by forming the buried punch-through stopper layer, the P
The impurity concentration near the junction depth of the ⁺ layer or the N ⁺ layer increases,
There is a drawback that the junction capacitance increases. Therefore, a method has been proposed in which the punch through stopper layer is formed only under the channel using a resist mask. (1993 S
ymposium on VLSI Technology Digest of Technical Pa
pers p.89) FIG. 9 shows a manufacturing process diagram of a conventional semiconductor device. In FIG. 9, FIG. 9A shows an N-wel in a semiconductor substrate 901.
After forming I902 and P-well 903, an element isolation region 904 is formed.
Is a step of forming. In FIG. 9B, the embedded punch-through stopper layers 905 and 906 are formed in N-well and P-type.
This is a step of forming the gate oxide film 907 and the gate electrode 908 on each well. The embedded punch-through stopper layer is formed by ion-implanting an impurity having the same polarity as the well only under the channel with a resist mask. FIG. 9C is a step of forming a source / drain region, which is a step of forming a sidewall 911 after forming a P ⁻ layer 909 and an N ⁻ layer 910, and forming a P ⁺ layer 912 and an N ⁺ layer 913. Is.

[0003]

However, in the conventional technique, the punch-through stopper layer increases the impurity concentration in the vicinity of the junction depth of the P ⁺ layer or the N ⁺ layer forming the source / drain region and increases the junction capacitance. However, as device miniaturization progresses, the overlap between the source / drain region and the punch-through stopper layer, which is caused by the problem of alignment accuracy, cannot be ignored, and the punch-through stopper layer is formed only under the channel by self-alignment. There is a long-awaited technology to do so. 10 and 11 show examples of characteristic diagrams of conventional semiconductor devices. In FIG. 10, the horizontal axis represents the distance (unit: μm) from the gate end of the mask in the step of forming the embedded punch-through stopper layer only under the channel using the resist mask. FIG. 4 is a diagram in which is plotted in the direction from the gate end to the inside of the gate electrode. The vertical axis is ΔVth
/ΔL=0.1V/0.1 μm Lmin (unit: μm) defined by L (gate length) is shown. Also, FIG.
1, the horizontal axis represents the distance (unit: μm) from the gate end of the mask forming the embedded punch-through stopper layer as in FIG. 10, and the vertical axis represents the case where these transistors form a ring oscillator. Shows the delay time per gate (unit: ps). Note that the gate length of the transistor is 0.25 μm for both pMOS and nMOS. From FIG. 10 and FIG. 11, the distance X from the gate end of the mask forming the embedded punch-through stopper layer is from the viewpoint of suppressing the short channel effect.
X> −0.06 μm is necessary, and from the viewpoint of reducing the gate delay time, X <+0.02 μm is necessary. (X <+0.02 μm is an accuracy required in consideration of the lateral spread during ion implantation and the lateral diffusion due to the heat treatment in the subsequent step.) As a result, −0.
The accuracy of 06 μm <X <+0.02 μm needs to be realized with good reproducibility on the entire surface of the wafer. Further, when the gate length is made finer than 0.25 μm, −0.06 μm
Accuracy higher than <X <+0.02 μm is required. Such accuracy is a value that cannot be realized by mask alignment.

Therefore, the present invention solves such a problem, and provides an element structure for forming a punch-through stopper layer only under a channel by self-alignment, and a manufacturing method thereof.

[0005]

A semiconductor device according to the present invention comprises: (1) a semiconductor substrate, a well made of a first conductivity type impurity formed in a predetermined region of the semiconductor substrate, and a source of an insulated gate semiconductor element. In a semiconductor device in which a second conductivity type impurity region forming a drain region is provided in the well, in a region of a predetermined depth of the well immediately below the gate of the insulated gate semiconductor element, the impurity concentration of the well is higher than that of the well. A high-concentration first-conductivity-type impurity region is provided, and a second first-conductivity-type impurity made of the same element as the impurity region provided immediately below the gate is provided in the second-conductivity-type impurity region. Is provided, and the peak value of the impurity concentration is
The second region near the junction depth between the conductivity type impurity region and the well
Is higher than the impurity concentration of the first conductivity type impurity region.

(2) The first conductivity type impurity region provided in a region of a predetermined depth in the well just below the gate of the insulated gate semiconductor element is 2 × 10 ¹⁷ to 1 × 10.
It is characterized by having a peak concentration of ¹⁸ (cm ⁻³ ).

(3) The second impurity region of the first conductivity type provided in the impurity region of the second conductivity type is 5 × in the vicinity of the junction depth between the impurity region of the second conductivity type and the well. 10 ¹⁶ ~
It is characterized by having an impurity concentration of 1 × 10 ¹⁷ (cm ⁻³ ).

(4) The peak concentration of the first conductivity type impurity region provided in the well just below the gate of the insulated gate semiconductor device is 0.02 outward from the end of the gate electrode.
The impurity concentration of 1 × 10 ¹⁷ (cm ⁻³ ) is crossed between the region of μm and the region of 0.06 μm inward from the end of the gate electrode.

Further, the method of manufacturing a semiconductor device according to the present invention comprises: (5) forming a well of a first conductivity type impurity in a predetermined region of a semiconductor substrate; and forming a gate insulating film of an insulated gate semiconductor element. And a step of forming a buried high-concentration region of the same conductivity type as that of the well, a step of forming a gate electrode in a predetermined shape, a defect is introduced using the gate electrode as a mask, and heat treatment is performed. The method is characterized by including at least a step of diffusing an impurity forming the buried high-concentration region and a step of forming a region made of a second conductivity type impurity forming a source / drain region.

(6) With the gate electrode as a mask,
In the step of introducing defects and diffusing the impurities forming the buried high-concentration region by heat treatment, Si ⁺ or Ar ⁺ is ion-implanted to introduce the defects.

(7) Acceleration voltage of 50 to 10 is applied to the Si ^+.
Dose amount 1 × 10 ^{14 to} 5 × 10 ¹⁵ (cm ⁻² ) at 0 keV
The feature is that ion implantation is performed.

(8) With the gate electrode as a mask,
In the step of introducing defects and diffusing the impurities forming the buried high concentration region by heat treatment, the heat treatment is
It is characterized in that it is applied in an oxidizing atmosphere at about 800 ° C. to 950 ° C. for about 20 minutes to 1 hour.

(9) The buried high concentration region contains at least arsenic.

(10) A step of forming a well made of an impurity of the first conductivity type in a predetermined region of a semiconductor substrate, a step of forming a gate insulating film of an insulated gate type semiconductor element, and the same conductivity type as the well. A step of forming an embedded high-concentration region, a step of forming a gate electrode in a predetermined shape, and a step of performing thermal oxidation in an atmosphere containing water vapor to diffuse impurities forming the embedded high-concentration region. The method further includes at least a step of forming a region of the second conductivity type impurity which constitutes a source / drain region.

(11) In the step of performing the heat treatment to diffuse the impurities forming the buried high concentration region, the heat treatment is performed at 850 ° C. to 9 ° C. in an atmosphere containing water vapor.
It is characterized in that thermal oxidation is performed at about 50 ° C. for about 20 minutes to 1 hour.

(12) The buried high-concentration region contains at least arsenic.

[0017]

1 is an example of a sectional view of a semiconductor device according to an embodiment of the present invention.

In FIG. 1, 101 is a semiconductor substrate and 102 is N.
-Well and 103 are embedded punch-through stopper layers formed only under the channel and made of N-type impurities such as phosphorus (P) or arsenic (As), which are regions having a higher impurity concentration than the well (hereinafter, referred to as "well"). BN layer). Ten
Reference ^numeral 4 denotes an N-type impurity layer formed of the same element as the buried layer 103 formed near the surface of the P ⁺ layer, and the concentration of the N-type impurity is P ⁺
The surface concentration of boron (B) in the layer is reduced by one digit or more. 105 is a gate insulating film, 106 is a gate electrode,
107 is a P ⁻ layer, 108 is a sidewall, and 109 is a P ⁺ layer.

As shown in FIG. 4 (described later), the peak concentration of the BN layer directly under the channel is 2 × 10 ¹⁷ to 1 × 10 ^18.
(Cm ^-3 ) (Actual N-type impurity concentration is well
The impurity concentration of P ⁺
The impurity concentration of the BN layer near the junction depth of the layer is at least 1
It is set to about × 10 ¹⁷ (cm ⁻³ ) or less. In addition, the region where the peak concentration of the BN layer directly under the channel is 1 × 10 ¹⁷ (cm ⁻³ ) or less is 0.02 μm outside the gate electrode end and the gate electrode for all the transistors in the wafer. It is controlled so as to enter a region between 0.06 μm inside from the extreme. The state is shown in FIG. 4C (described later).

In FIG. 1, a pMOS is taken as an example for simplicity, but the present invention is also effective for an nMOS.

FIG. 2 is an example of a sectional view of a semiconductor device according to an embodiment of the present invention.

In FIG. 2, 201 is a semiconductor substrate and 202 is P.
-Well, 203 is formed only under the channel, B
It is a buried punch-through stopper layer made of P-type impurities such as, for example, a region in which the concentration of P-type impurities is higher than the well (hereinafter referred to as the BP layer). Reference numeral 204 is a P-type impurity layer formed of the same element as the buried layer 203 formed near the surface of the N ⁺ layer, and the concentration of the P-type impurity is one digit or more lower than the surface concentration of As or P of the N ⁺ layer. It is like that. 205
Is a gate insulating film, 206 is a gate electrode, 207 is an N ⁻ layer, 208 is a sidewall, and 209 is an N ⁺ layer.

FIG. 3 is an example of a manufacturing process diagram of a semiconductor device according to an embodiment of the present invention.

FIG. 3A shows a semiconductor substrate 301 having Nw
well 302 and P-well 303 are formed, and an element isolation region is formed.
This is a step of forming 304. The impurity concentration of the well is usually set to about 5 × 10 ^{16 to} 5 × 10 ¹⁷ (cm ⁻³ ), but by optimizing the embedded punch-through stopper layer, the gate length is set to 1 when the gate length is 0.25 μm. × 10
¹⁷ (cm ^-3) below, also can be below 2 × 10 ^17, even if the gate length 0.15μm (cm ^-3). This is important in ensuring the driving capability of the transistor. Figure 3
(B) shows a BN layer 306 and a BP layer 307 which form a gate insulating film 305 and form an embedded punch through stopper layer.
Are respectively formed on the N-well and the P-well,
After performing ion implantation for Vth control, gate electrode 308
Is a step of forming. The embedded punch-through stopper layer is formed by ion-implanting impurities having the same polarity as the well. As an example of the conditions for forming the BN layer, As ⁺
At an accelerating voltage of 120 to 200 (keV) and a dose of 1
Ion implantation of about × 10 ^{12 to} 6 × 10 ¹² (cm ^-2 )
An N layer is formed. Further, as an example of the formation conditions of the BP layer, BF ₂ ⁺ is ion-implanted at an acceleration voltage of about 70 to 120 (keV) and a dose of about 1 × 10 ^{12 to} 6 × 10 ¹² (cm ⁻² ) to form a BN layer. To form. FIG. 3C shows a point defect (vacancy, interstitial Si) formed on the Si substrate except under the gate by ion-implanting elements such as Si and Ar using the gate electrode as a mask.
Etc.), and subsequently annealing in an oxidizing atmosphere or the like. By this annealing, the impurities in the defect-introduced regions of the BN layer and the BP layer formed over the entire surface in FIG. 3B are diffused more rapidly, and the peak of the impurity concentration existing immediately after the ion implantation is lowered. Then, a part thereof is piled up near the surface of the source / drain region to form an N-type impurity layer 309 and a P-type impurity layer 310 made of the same element as the BN layer 311 and the BP layer 312 which are left just under the channel. As a result, the well near the junction depth of the source / drain region
The impurity concentration of can be lowered by self-alignment using the gate electrode as a mask. When the as an example the case where the Si ion implantation, Si ⁺ acceleration voltage dose 1 × 10 ¹⁴ ~5 × 10 ¹⁵ in 50~100keV (cm ^{- 2)} degree ion implantation. Subsequently, in an oxidizing atmosphere, 800 ° C to 950
Anneal at 20 ° C. for about 20 minutes to 1 hour. An oxidation temperature of 850 ° C. to 950 ° C. is desirable for dry, and an oxidation temperature of 800 ° C. to 900 ° C. is desirable for wet.
When the oxidizing atmosphere is wet rather than dry, the diffusion of impurities is accelerated and redistribution occurs more remarkably. Figure 3 (d)
Is a step of forming a source / drain region, and the P ⁻ layer 3
After the 13 and the N ⁻ layer 314 are formed, the sidewall 315 is formed, and the P ⁺ layer 316 and the N ⁺ layer 317 are formed. P ^- layer 316 and N
^- the junction depth of the layer 317 to optimize the ion implantation conditions and heat treatment conditions to be less than 0.15～0.20Myuemu.
In the embodiment shown in FIG. 3, after the gate electrode is processed into a predetermined shape, point defects are introduced by ion implantation to accelerate diffusion of impurities forming the punch-through stopper layer. Is not limited to this. For example, after forming the sidewalls, point defects may be introduced by ion implantation to accelerate diffusion of impurities forming the punch-through stopper layer. In this case, it is necessary to more rapidly diffuse the impurities forming the punch-through stopper layer just below the sidewall edge to lower the impurity concentration near the junction depth. Therefore, the oxidizing atmosphere is wet at 800 ° C. to 900 ° C.
It becomes more important to process in. In the embodiment of FIG. 3, the point defect is introduced by ion implantation and then the diffusion is accelerated in the oxidizing atmosphere. However, such an impurity profile can be realized to some extent without ion implantation. I have also confirmed. For that purpose, after processing the gate electrode into a predetermined shape, it is performed in a wet atmosphere at 850 ° C.
It is necessary to anneal at 950 ° C. for 20 minutes to 1 hour (redistribution of As hardly occurs especially in a dry atmosphere), and the impurity concentration near the junction depth of the source / drain region when ion implantation is also used. It can be suppressed within about 3 times.

FIG. 4, FIG. 5, and FIG. 6 are examples of impurity profile diagrams in the embodiment of the present invention. Figure 4
The impurity profile of the depth direction of a source drain region is shown. The impurity profile was analyzed by SIMS. 401 is the As profile immediately after ion implantation,
Shows the profile of As after annealing. 403 shows the profile of B of the P ⁺ layer which constitutes the source / drain. Further, FIG. 5 shows an impurity profile in the depth direction immediately below the channel. 501 shows the As profile immediately after ion implantation, and 502 shows the As profile after annealing. As shown in FIG. 4 and FIG.
Although s is hardly redistributed by the annealing, As in the source / drain region is largely redistributed by the enhanced diffusion due to the defects introduced by the ion implantation shown in FIG. It can be seen that the peak of the impurity concentration immediately after the implantation becomes broad due to annealing and segregates near the surface of the Si substrate.
However, the concentration of As segregated near the surface (the impurity concentration of the well is not added) is suppressed to about 5 × 10 ¹⁸ (cm ⁻³ ) or less, which is one digit or more lower than the surface concentration of the P ⁺ layer. Can be controlled. As a result, the peak concentration of the buried layer immediately below the channel is 2 × 10 ¹⁷ to 1 × 10 ¹⁸ (c
As in the vicinity of the junction depth of the P ⁺ layer while maintaining about m ⁻³ ).
The concentration of at least 5 × 10 ¹⁶ to 1 × 10 ¹⁷ (c
It has become possible to make it about m ⁻³ ). Incidentally, as disclosed in the embodiments based on the present invention, an element such as Si or Ar is ion-implanted, and defects (holes, holes,
In the case of not using the manufacturing method in which interstitial Si etc. is introduced and subsequently annealed in an oxidizing atmosphere or the like, A as described above is used.
Redistribution of s hardly occurs, and the As concentration near the junction depth of the P ⁺ layer cannot be lowered. The present invention enables the control of such an impurity profile for the first time.
According to the present invention, as shown in FIGS. 4 and 5, the peak concentration of the buried layer immediately below the channel is 2 × 10 ¹⁷ to 1 × 1.
With the ^temperature kept at about 0 ¹⁸ (cm ⁻³ ), the concentration of N-type impurities near the junction depth of the P ⁺ layer is at least 5 × 10 ¹⁶ to 1 ×.
It can be about 10 ¹⁷ (cm ⁻³ ). In addition, FIG.
The result of simulating the one-dimensional concentration distribution of As in the channel direction at a depth near the peak concentration of the BN layer is shown in FIG. In FIG. 6, the horizontal axis represents the distance in the channel direction (unit: μm), and shows the case where the gate length is 0.25 μm with reference to the source-side gate end of the transistor (0 μm). The vertical axis represents the impurity concentration of As (unit: cm ^-3 ).
Indicates. As a result of reproducing variations in manufacturing conditions on a simulation, the peak concentration of the buried layer immediately below the channel (the peak concentration at the center of the channel is 2 × 10 ^{17 to} 5 × 1
The region where 0 ¹⁷ (cm ⁻³ ) is 1 × 10 ¹⁷ (cm ⁻³ ) or less is 0.0 inward from the gate electrode end with respect to all transistors in the wafer plane and between the wafers.
It was confirmed that the control could be performed so that the area was 2 to 0.06 μm. Further, the peak concentration of the buried layer immediately below the channel (the peak concentration of the central portion of the channel is 5 × 10 ¹⁷ to
1 × 10 ¹⁸ (cm ⁻³ )) is 1 × 10 ¹⁷ (cm ⁻³ ).
The area below is 0.02 μm from the gate electrode edge to the outside and 0.04 μm from the gate electrode edge to the inside for all transistors in the wafer plane and between the wafers.
I confirmed that I could control it as if I were in the entered area. This is a value that cannot be achieved by conventional ion implantation using a resist mask, and is possible for the first time by the self-alignment method using the gate electrode according to the present invention as a mask. Incidentally, FIG.
6 shows the BN layer made of As as an example, but the present invention is also very effective for the BN layer made of P and the BP layer made of B in addition to this, and an element such as Si or Ar is ion-implanted. Then, point defects (holes,
By introducing interstitial Si, etc., and subsequently annealing in an oxidizing atmosphere or the like, the impurity profile of P or B can be controlled almost in the same manner as As. Conventionally, the phenomenon that B is redistributed in the oxidation process of the gate electrode has been reported (IEDM '87 p.632), but the remarkable B redistribution as shown in the present invention has not been reported. Furthermore, there has been no report on the redistribution of P and As, and according to the present invention, point defects (vacancy, interstitial Si, etc.) are introduced into the Si substrate except directly under the gate, and subsequently annealed in an oxidizing atmosphere or the like. It became possible for the first time. As described above, according to the present invention, the peak concentration of the embedded punch-through stopper layer directly below the channel is set to 2 × 10 ¹⁷ to 1 × 10 ¹⁸ (cm ⁻³ ).
While maintaining the above, the impurity concentration of the punch-through stopper layer near the junction depth of the source / drain should be at least 5 × 10 ¹⁶
It has become possible to make it about 1 × 10 ¹⁷ (cm ⁻³ ).
Furthermore, the impurity profile in the lateral direction also has a peak concentration of 2 × 10 3 in the buried layer immediately below the channel (at least in the center).
^While maintaining at ¹⁷ to 1 × 10 ¹⁸ (cm ⁻³ ), 1 × 10 ¹⁷ (c
m ^-3 ) or less, for all the transistors within the wafer surface and between the wafers, the area from 0.02 μm outside the gate electrode end to 0.06 μm inside the gate electrode from the gate end It became possible to control as if it were.

FIG. 7 is a characteristic diagram of the semiconductor device in the embodiment according to the present invention. In FIG. 5, the horizontal axis is pMO.
The gate length of S (unit: μm) is shown, and the vertical axis is the threshold voltage V
Indicates th (unit: V). 701 shows the characteristics of a pMOS in which a BN layer is formed immediately below the channel according to the present invention,
Reference numeral 702 denotes a pMOS characteristic in which the BN layer is not provided.
Shows the characteristics of a pMOS in which a BN layer is provided on the entire surface. Figure 7
As shown in FIG. 5, it is understood that the short channel effect is significantly improved by providing the BN layer only under the channel, as compared with the pMOS in which the BN layer is not provided. Also, by forming the BN layer only directly under the channel, the BN layer is formed on the entire surface.
It can also be seen that it is as effective as the pMOS formed with the layer. In the pMOS in which the BN layer is formed on the entire surface, it is necessary to increase the concentration of the BN layer in order to suppress the short channel effect. Therefore, the junction capacitance between the P ⁺ layer and the N-well is 1.
Although it is as large as about 3 to 1.5 (fF / μm ² ), in the pMOS of the present invention, the impurity concentration near the junction depth can be lowered, so that the junction capacitance between the P ⁺ layer and the N-well can be reduced to 0.
It can be lowered to about 5 to 0.8 (fF / μm ² ). As a result, the junction capacitance can be reduced to about 1/2 to 1/3 of that of the conventional one while sufficiently suppressing the short channel effect, and the operation speed is significantly increased and stabilized as shown in FIG. Was achieved.

FIG. 8 is a characteristic diagram of the semiconductor device in the embodiment according to the present invention. In FIG. 8, the vertical axis represents the delay time per gate of the ring oscillator (unit: p
s) is shown. Reference numeral 801 shows the characteristics of the CMOS semiconductor element based on the present invention, and 802 shows the characteristics of the CMOS semiconductor element in which the punch-through stopper layer is formed only just under the channel using the conventional resist mask. The error bars in the figure show variations in delay time, and the crosses show average values.
It can be seen that according to the present invention, the operating speed of the device is increased, and at the same time, the variation is greatly reduced. It should be noted that the characteristics shown in FIG. 8 exemplify the case where the gate length is 0.25 μm for both pMOS and nMOS.

The present invention is not limited to the embodiments shown in FIGS. 1 to 8 and can be widely applied to all insulated gate type semiconductor devices.

[0029]

According to the present invention, the peak concentration of the buried layer immediately below the channel is 2 × 10 ¹⁷ to 1 × 10 ¹⁸ (c).
The impurity concentration in the vicinity of the junction depth of the diffusion layer forming the source / drain region should be at least 5 × 10 5 while maintaining about m ⁻³ ).
It has become possible to make it about ¹⁶ to 1 × 10 ¹⁷ (cm ⁻³ ). If a manufacturing method in which an element such as Si or Ar is ion-implanted, defects (vacancy, interstitial Si, etc.) are introduced into the Si substrate except directly under the gate, and then annealing is performed in an oxidizing atmosphere or the like, Such redistribution of impurities hardly occurs, and the impurity concentration near the junction depth of the diffusion layer cannot be lowered. The present invention enables the control of such an impurity profile for the first time. The peak concentration of the buried layer directly below the channel is 1 × 10 ¹⁷ (cm ⁻³ ).
The area below is 0.02 to 0.06 inward from the gate electrode end for all transistors in the wafer.
It can be controlled so that it becomes a region containing μm. This is a value that cannot be achieved by conventional ion implantation using a resist mask, and is possible for the first time by the self-alignment method using the gate electrode according to the present invention as a mask.

As a result, the junction capacitance between the diffusion layer forming the source / drain and the well is 1.3 to 1. 1 when the embedded punch-through stopper layer is formed over the entire surface while significantly suppressing the short channel effect. What was about 5 (fF / μm ² ) can be reduced to about 0.5 to 0.8 (fF / μm ² ) and the junction capacitance can be reduced to about 1/2 to 1/3 of the conventional value. It has become possible.

When a buried punch-through stopper layer is formed only under the channel by using a resist mask, if the element is miniaturized, the overlap between the source / drain region and the punch-through stopper layer cannot be ignored due to the problem of alignment accuracy. However, according to the present invention, since the impurity profile can be controlled by the self-alignment method, both the suppression of the short channel effect and the improvement of the operation speed (reduction of the junction capacitance) can be achieved with good reproducibility, and the operation speed is significantly increased and its variation. It was possible to reduce

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a manufacturing process diagram of a semiconductor device according to an embodiment of the invention.

FIG. 4 is an impurity profile diagram in an example of the present invention.

FIG. 5 is an impurity profile diagram in an example of the present invention.

FIG. 6 is an impurity profile diagram in an example of the present invention.

FIG. 7 is a characteristic diagram of a semiconductor device in an example according to the present invention.

FIG. 8 is a characteristic diagram of a semiconductor device in an example according to the present invention.

FIG. 9 is a manufacturing process diagram of a conventional semiconductor device.

FIG. 10 is a characteristic diagram of a conventional semiconductor device.

FIG. 11 is a characteristic diagram of a conventional semiconductor device.

[Explanation of symbols]

101,201,301 ・ ・ ・ Semiconductor substrate 102,302 ・ ・ ・ N-well 202,303 ・ ・ ・ P-well 103,203 ・ ・ ・ Embedded punch through stopper layer 306 ・ ・ ・ BN layer 307 ・ ・ ・ BP layer 104,309 ・ ・ ・ N type impurity layer 204,310 ・ ・ ・ P-type impurity layer 105,205,305 ・ ・ ・ Gate insulating film 106,206,308 ・ ・ ・ Gate electrode 107,311 ・ ・ ・ P ^- layer 109,314 ・ ・ ・ P ⁺ layer 207,312 ・ ・ ・ N ^- layer 209,315 ・ ・ ・ N ⁺ layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/336

Claims (12)

[Claims] 1. A semiconductor substrate, a well made of a first conductivity type impurity formed in a predetermined region of the semiconductor substrate, and a second conductivity type impurity region forming a source / drain region of an insulated gate semiconductor device. In a region of a predetermined depth of the well just below the gate of the insulated gate semiconductor element, a first conductivity type impurity region having a higher concentration than the impurity concentration of the well is provided. Provided,
A second first-conductivity-type impurity region made of an impurity of the same element as that of the impurity region provided immediately below the gate is provided in the second-conductivity-type impurity region, and the peak value of the impurity concentration is the second-conductivity-type impurity region. The impurity concentration of the second conductivity type impurity region near the junction depth between the impurity region and the well is higher than that of the second impurity region. 2. The impurity region of the first conductivity type provided in a region of a predetermined depth in the well just below the gate of the insulated gate semiconductor device has a concentration of 2 × 10 ¹⁷ to 1 × 10 ^18. (C
m ^-3 ) peak concentration.
The semiconductor device described. 3. A second electrode provided in the impurity region of the second conductivity type.
Of the first conductivity type impurity region in the vicinity of the junction depth of the second conductivity type impurity region and the well is 5 × 10 ¹⁶ to 1 × 10 5.
3. The semiconductor device according to claim 1, which has an impurity concentration of ¹⁷ (cm ⁻³ ). 4. A gate electrode of a region having a peak concentration of 0.02 μm outward from an end of a gate electrode provided in an impurity region of a first conductivity type provided in the well just below the gate of the insulated gate semiconductor device. 4. The semiconductor device according to claim 1, 2 or 3, wherein an impurity concentration of 1 × 10 ¹⁷ (cm ⁻³ ) is crossed between regions that are 0.06 μm inward from the extreme. 5. A step of forming a well made of an impurity of the first conductivity type in a predetermined region of a semiconductor substrate, a step of forming a gate insulating film of an insulated gate semiconductor element, and an implantation of the same conductivity type as the well. A step of forming a high-concentration region of the mold, a step of forming a gate electrode in a predetermined shape, a defect is introduced by using the gate electrode as a mask, and an impurity forming the high-concentration region of the buried type is diffused by heat treatment. A method of manufacturing a semiconductor device, which comprises at least a step and a step of forming a region made of an impurity of a second conductivity type which constitutes a source / drain region. 6. In the step of introducing defects using the gate electrode as a mask and diffusing the impurities forming the buried high-concentration region by heat treatment, Si ⁺ or Ar ⁺ is ion-implanted to introduce the defects. The method for manufacturing a semiconductor device according to claim 5, wherein 7. The acceleration voltage of the Si ⁺ is 50 to 100 keV.
7. The method for manufacturing a semiconductor device according to claim 6, wherein the dose is 1 × 10 ^{14 to} 5 × 10 ¹⁵ (cm ⁻² ) ions are implanted. 8. In the step of introducing defects by using the gate electrode as a mask and diffusing the impurities forming the buried high concentration region by heat treatment, the heat treatment is performed in an oxidizing atmosphere at about 800 ° C. to 950 ° C. for 20 minutes. The method for manufacturing a semiconductor device according to claim 5, 6 or 7, wherein the process is performed for about 1 minute to 1 hour. 9. The method for manufacturing a semiconductor device according to claim 5, wherein the buried high-concentration region contains at least arsenic. 10. A step of forming a well made of an impurity of the first conductivity type in a predetermined region of a semiconductor substrate, a step of forming a gate insulating film of an insulated gate semiconductor element, and an implantation of the same conductivity type as the well. A step of forming a high-concentration region of the mold, a step of forming the gate electrode in a predetermined shape, a step of performing thermal oxidation in an atmosphere containing water vapor, and diffusing the impurities forming the high-concentration region of the embedded type, A method of manufacturing a semiconductor device, comprising at least a step of forming a region made of a second conductivity type impurity forming a source / drain region. 11. In the step of performing the heat treatment and diffusing the impurities forming the buried high concentration region, the heat treatment is performed in an atmosphere containing water vapor at about 850 ° C. to 950 ° C. for about 20 minutes to 1 hour. The method for manufacturing a semiconductor device according to claim 10, wherein oxidation is performed. 12. The method of manufacturing a semiconductor device according to claim 10, wherein the buried high-concentration region contains at least arsenic.