JPH0441503B2 - - Google Patents
Info
- Publication number
- JPH0441503B2 JPH0441503B2 JP24970783A JP24970783A JPH0441503B2 JP H0441503 B2 JPH0441503 B2 JP H0441503B2 JP 24970783 A JP24970783 A JP 24970783A JP 24970783 A JP24970783 A JP 24970783A JP H0441503 B2 JPH0441503 B2 JP H0441503B2
- Authority
- JP
- Japan
- Prior art keywords
- bipolar transistor
- mosfet
- offset
- semiconductor device
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 description 11
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- -1 Boron ions Chemical class 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体装置に係り、特にオフセツト領
域を有するMOSFETとバイポーラトランジスタ
とを同一基板上に形成する際に好適な半導体装置
およびその製造方法に関するものである。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a semiconductor device, and particularly to a semiconductor device suitable for forming a MOSFET having an offset region and a bipolar transistor on the same substrate, and a method for manufacturing the same. It is.
横型NPNバイポーラトランジスタとＰチヤン
ネルMOSFETとを同一基板上に形成した従来の
半導体装置の構造の例を第１図に示す。
FIG. 1 shows an example of the structure of a conventional semiconductor device in which a lateral NPN bipolar transistor and a P-channel MOSFET are formed on the same substrate.
Ｐ型基板１の主表面に形成されたＮ型ウエル
３，３′内に、夫々ＰチヤンネルMOSFET１０
１，NPNバイポーラトランジスタ１０２が形成
されている。２は素子分離用の選択酸化膜，４は
ゲート，５はソース，５′はドレイン，６は表面
保護膜，７はベース，８はコレクタ，９はエミツ
タである。第１図のＰチヤンネルMOSFET１０
１のソース５，ドレイン５′は、通常比較的高不
純物濃度（≧1019／cm2）のほう素拡散層で作ら
れ、また、バイポーラトランジスタ１０２のベー
ス７は、不純物濃度1017／cm3〜1018／cm2の濃度を
必要とし、両者を共通化することは困難である。 P-channel MOSFETs 10 are installed in the N-type wells 3 and 3' formed on the main surface of the P-type substrate 1, respectively.
1. An NPN bipolar transistor 102 is formed. 2 is a selective oxide film for element isolation, 4 is a gate, 5 is a source, 5' is a drain, 6 is a surface protection film, 7 is a base, 8 is a collector, and 9 is an emitter. P-channel MOSFET10 in Figure 1
The source 5 and drain 5' of the bipolar transistor 102 are usually made of a boron diffusion layer with a relatively high impurity concentration (≧10 19 /cm 2 ), and the base 7 of the bipolar transistor 102 has an impurity concentration of 10 17 /cm 3 . It requires a concentration of ~10 18 /cm 2 , and it is difficult to make both of them common.
第２図は、短チヤンネル（通常ゲート長2μm以
下）のＰチヤンネルMOSFET２０１の構造を示
す。チヤンネル長が短くなると、短チヤンネル効
果による閾値電圧の低下、ホツトキヤリアによる
閾値電圧の変動を防ぐため、ソース，ドレインに
浅い低不純物濃度領域であるオフセツト領域１
０，１０′を形成し、電界を弱める構造が提案さ
れている（オフセツトゲート構造と呼ばれてい
る）。 FIG. 2 shows the structure of a short channel (usually gate length 2 μm or less) P-channel MOSFET 201. When the channel length becomes short, in order to prevent the threshold voltage from decreasing due to the short channel effect and from changing the threshold voltage due to hot carriers, an offset region 1, which is a shallow low impurity concentration region, is added to the source and drain.
A structure has been proposed in which the electric field is weakened by forming 0,10' (referred to as an offset gate structure).
第３図は、従来技術の組み合わせで、オフセツ
ト領域を有する短チヤンネルのＰチヤンネル
MOSFET２０１とバイポーラトランジスタ１０
２とを同一基板上に形成した例を示す。第１図の
構成に比べ、ソース，ドレインのオフセツト領域
１０，１０′を形成する工程がつけ加わり、工程
数増加を伴なう問題が有る。 Figure 3 shows a short channel P channel with an offset region, which is a combination of conventional techniques.
MOSFET201 and bipolar transistor 10
2 is formed on the same substrate. Compared to the structure shown in FIG. 1, there is an additional step of forming source and drain offset regions 10, 10', resulting in an increase in the number of steps.
本発明は、オフセツト領域を有する短チヤンネ
ルのMOSFETと、バイポーラトランジスタとを
同一基板上に形成する際に、工程数を少くするこ
とを目的としている。
The present invention aims to reduce the number of steps when forming a short channel MOSFET having an offset region and a bipolar transistor on the same substrate.
上記目的を達成する本発明半導体装置の特徴と
するところは、オフセツト領域を有する
MOSFETとバイポーラトランジスタとが混在す
る半導体装置に於いて、MOSFETオフセツト領
域の深さ及び不純物濃度とバイポーラトランジス
タのベース領域の深さ及び不純物濃度とが略等し
いことにある。
The semiconductor device of the present invention that achieves the above object is characterized by having an offset region.
In a semiconductor device in which a MOSFET and a bipolar transistor are mixed, the depth and impurity concentration of the MOSFET offset region and the depth and impurity concentration of the base region of the bipolar transistor are approximately equal.
また、本発明半導体装置の製造方法の特徴とす
るところは、MOSFETのオフセツト領域とバイ
ポーラトランジスタのベース領域とが同一工程で
形成されることにある。 Furthermore, the method for manufacturing a semiconductor device of the present invention is characterized in that the offset region of the MOSFET and the base region of the bipolar transistor are formed in the same step.
以下、図面を用いて本発明を説明する。 Hereinafter, the present invention will be explained using the drawings.
第４図に本発明の一実施例となる半導体装置の
断面構造を示す。オフセツトゲート構造の短チヤ
ンネルのＰチヤンネルMOSFET４０１と横型
NPNバイポーラトランジスタ４０２を同一基板
上に形成した高速のBiCMOS構造の半導体装置
である。ＰチヤンネルMOSFET４００のソー
ス，ドレインの低濃度のオフセツト領域１０，１
０′とバイポーラトランジスタ４０２のベース領
域１０〃との深さ及び不純物濃度を略等しくする
ことを特徴としている。 FIG. 4 shows a cross-sectional structure of a semiconductor device according to an embodiment of the present invention. Short channel P-channel MOSFET401 with offset gate structure and horizontal type
This is a high-speed BiCMOS semiconductor device in which an NPN bipolar transistor 402 is formed on the same substrate. Low concentration offset regions 10 and 1 of source and drain of P channel MOSFET 400
0' and the base region 10 of the bipolar transistor 402 have substantially the same depth and impurity concentration.
第５図に本発明半導体装置の製造方法の一実施
例を示す。 FIG. 5 shows an embodiment of the method for manufacturing a semiconductor device of the present invention.
第５図ａは、Ｐ基板１内にＮウエル領域３，
３′を形成後、素子分離用の選択酸化膜２，ゲー
ト４，コレクタ８を形成し、続いてＰチヤンネル
MOSFETのソース，ドレインの低濃度のオフセ
ツト領域１０，１０′とバイポーラトランジスタ
のベース領域１０〃を、ホトレジスト膜１１をマ
スクとしてイオン打込み法で形成する工程を示し
ている。ボロンイオン１２は、15KeVのエネル
ギーで３×1013／cm2の量を打込む。 FIG. 5a shows an N well region 3 in a P substrate 1,
3', a selective oxide film 2 for element isolation, a gate 4, and a collector 8 are formed, and then a P channel is formed.
This figure shows a step of forming low concentration offset regions 10, 10' of the source and drain of the MOSFET and the base region 10 of the bipolar transistor by ion implantation using the photoresist film 11 as a mask. Boron ions 12 are implanted in an amount of 3×10 13 /cm 2 with an energy of 15 KeV.
第５図ｂは、オフセツト領域１０，１０′、ベ
ース領域１０〃の形成後、全面にCVD法により
SiO2膜１３を4000Ａ・の厚さに形成した状態を示
している。 FIG. 5b shows that after the offset regions 10, 10' and the base region 10 are formed, the entire surface is coated by CVD.
A state in which the SiO 2 film 13 is formed to a thickness of 4000 A is shown.
次に、第５図ｃは、オフセツトゲート構造を形
成するため、反応性イオンエツチング法により、
SiO2膜をエツチングし、ゲート４の側面部分に
SiO2膜１４（サイドウオールSiO2膜と呼ばれて
いる）を残す工程を示している。反応性イオンエ
ツチングは、横方向のエツチングが殆んど生じな
い性質により、ゲート側面の段差部分にSiO2膜
が残る。 Next, FIG. 5c shows that in order to form an offset gate structure, reactive ion etching is performed.
Etch the SiO 2 film and attach it to the side surface of gate 4.
This shows a step in which the SiO 2 film 14 (referred to as a sidewall SiO 2 film) is left. Due to the nature of reactive ion etching, which causes almost no lateral etching, a SiO 2 film remains on the stepped portions of the side surfaces of the gate.
続いて、第５図ｄで再びホトレジスト膜１５を
マスクとして、ＰチヤンネルMOSFETのソー
ス，ドレインの高濃度領域５，５′のイオン打込
みを行なう。ほう素イオン１６は、30KeVのエ
ネルギーで、５×1015／cm2の量の打込みを行な
う。 Subsequently, in FIG. 5D, ions are implanted into the high concentration regions 5 and 5' of the source and drain of the P channel MOSFET using the photoresist film 15 again as a mask. Boron ions 16 are implanted at an energy of 30 KeV and in an amount of 5×10 15 /cm 2 .
第５図ｅは、イオン打込み後、バイポーラトラ
ンジスタのエミツタ９を形成した状態を示してい
る。エミツタの形成は、ホトレジスト膜をマスク
にしてひ素イオンを80KeVで１×1016／cm2打込
み、950℃20分の熱処理を行なつて形成する。 FIG. 5e shows the state in which the emitter 9 of the bipolar transistor is formed after ion implantation. The emitters are formed by implanting arsenic ions at 1×10 16 /cm 2 at 80 KeV using a photoresist film as a mask, and performing heat treatment at 950° C. for 20 minutes.
この段階でＰチヤンネルMOSFETとバイポー
ラトランジスタの構造が形成されるが、Ｐチヤン
ネルMOSFETのソース，ドレインの低濃度オフ
セツト領域１０，１０′と、バイポーラトランジ
スタのベース領域１０″とは、0.3μm、ソース，
ドレインの高濃度領域５，５′は、0.5μmの深さ
になる。 At this stage, the structures of the P-channel MOSFET and the bipolar transistor are formed, and the low concentration offset regions 10 and 10' of the source and drain of the P-channel MOSFET and the base region 10'' of the bipolar transistor are 0.3 μm apart,
The high concentration regions 5, 5' of the drain have a depth of 0.5 μm.
本実施例は、ＰチヤンネルMOSFETのオフセ
ツト領域１０，１０′とバイポーラトランジスタ
のベース領域１０″とを同一の工程で作る方法で
あるが、この工程を、Ｐ型抵抗の形成に用いるこ
とも可能である。 In this example, the offset regions 10, 10' of the P-channel MOSFET and the base region 10'' of the bipolar transistor are formed in the same process, but this process can also be used to form a P-type resistor. be.
以上、述べた様に本発明によれば短チヤンネル
のＰチヤンネルMOSFETのオフセツト領域形成
工程を、バイポーラトランジスタのベース，Ｐ型
抵抗等の形成と共通化することにより、工程増を
少くして各種の素子を同一基板上に形成できる利
点を持つ。
As described above, according to the present invention, the process of forming the offset region of a short-channel P-channel MOSFET is shared with the formation of the base of a bipolar transistor, P-type resistor, etc., thereby reducing the number of additional steps and making it possible to It has the advantage that elements can be formed on the same substrate.
第１図はＰチヤンネルMOSFETとバイポーラ
トランジスタとを同一基板上に形成した半導体装
置の従来構造のBiCMOS素子の断面図、第２図
はオフセツト領域を有するＰチヤンネル
MOSFETの従来構造を示す断面図、第３図はオ
フセツト領域を有するＰチヤンネルMOSFETと
バイポーラトランジスタとを同一基板上に形成し
た従来構造を示す断面図、第４図は本発明半導体
装置の一実施例となるオフセツトゲートのＰチヤ
ンネルMOSFETとバイポーラトランジスタとを
同一基板上に形成した半導体装置の断面構造を示
す図、第５図は本発明半導体装置の製造方法の一
実施例を示す図である。
１０，１０′……オフセツト領域、１０〃……
ベース領域、４０１……オフセツト領域を有する
MOSFET、４０２……バイポーラトランジス
タ。
Figure 1 is a cross-sectional view of a BiCMOS element with a conventional structure of a semiconductor device in which a P-channel MOSFET and a bipolar transistor are formed on the same substrate, and Figure 2 is a P-channel MOSFET with an offset region.
3 is a sectional view showing a conventional structure of a MOSFET, FIG. 3 is a sectional view showing a conventional structure in which a P-channel MOSFET having an offset region and a bipolar transistor are formed on the same substrate, and FIG. 4 is an embodiment of the semiconductor device of the present invention. FIG. 5 is a diagram showing a cross-sectional structure of a semiconductor device in which an offset gate P-channel MOSFET and a bipolar transistor are formed on the same substrate, and FIG. 5 is a diagram showing an embodiment of the method for manufacturing the semiconductor device of the present invention. 10, 10'...Offset area, 10...
base area, 401... has an offset area
MOSFET, 402...Bipolar transistor.
Claims (1)
ーラトランジスタとが混在する半導体装置に於い
て、前記MOSFETのオフセツト領域の深さ及び
不純物濃度と上記バイポーラトランジスタのベー
ス領域の深さ及び不純物濃度とが略等しいことを
特徴とする半導体装置。 ２ オフセツト領域を有するMOSFETとバイポ
ーラトランジスタとが混在する半導体装置の製造
方法に於いて、上記MOSFETのオフセツト領域
と上記バイポーラトランジスタのベース領域とが
同一工程で形成されることを特徴とする半導体装
置の製造方法。[Claims] 1. In a semiconductor device in which a MOSFET having an offset region and a bipolar transistor coexist, the depth and impurity concentration of the offset region of the MOSFET and the depth and impurity concentration of the base region of the bipolar transistor are A semiconductor device characterized in that these are substantially equal. 2. A method for manufacturing a semiconductor device in which a MOSFET having an offset region and a bipolar transistor coexist, wherein the offset region of the MOSFET and the base region of the bipolar transistor are formed in the same process. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24970783A JPS60137055A (en) | 1983-12-26 | 1983-12-26 | Semiconductor device mixed with mosfet and bipolar transistor and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24970783A JPS60137055A (en) | 1983-12-26 | 1983-12-26 | Semiconductor device mixed with mosfet and bipolar transistor and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60137055A JPS60137055A (en) | 1985-07-20 |
| JPH0441503B2 true JPH0441503B2 (en) | 1992-07-08 |
Family
ID=17197001
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24970783A Granted JPS60137055A (en) | 1983-12-26 | 1983-12-26 | Semiconductor device mixed with mosfet and bipolar transistor and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60137055A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4752589A (en) * | 1985-12-17 | 1988-06-21 | Siemens Aktiengesellschaft | Process for the production of bipolar transistors and complementary MOS transistors on a common silicon substrate |
| EP0256315B1 (en) * | 1986-08-13 | 1992-01-29 | Siemens Aktiengesellschaft | Integrated circuit containing bipolar and cmos transistors on a common substrate, and process for its production |
| JPH02103960A (en) * | 1988-10-13 | 1990-04-17 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
-
1983
- 1983-12-26 JP JP24970783A patent/JPS60137055A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60137055A (en) | 1985-07-20 |
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