JPS63273317A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the depth of the impurity diffusion region to a predetermined value by manufacturing a title device, after diffusing an impurity into a predetermined region of a substrate, by the use of a low-temperature selective oxidation process at a predetermined temperature or less, and a process for removing the oxide film having grown in the above process by a wet etching method. CONSTITUTION:With a resist pattern 3 as a mask BF2 ions are implanted into a dose substrate 1 to form a region 4. Then the pattern 3 is removed and an anneal is performed, forming a P-type diffusion layer 5 of, for instance, 2000Angstrom . And with a CVD nitride film 6 as a mask a thermal oxide film 2 immediately above the layer 5 is removed by a wet etching. Then, again with the film 6 as a mask a low-temperature selective oxide Si film 7 is grown at a predetermined temperature. Further, again an oxide film 7 on the whole surface is grown. Moreover, when the film 7 on the whole surface is removed by a wet etching, the layer is reduced and becomes shallow, whereby a very shallow diffusion layer 51 of, for instance, 1500Angstrom is formed. Further, by repetition of the low-temperature selective oxidation process and the wet etching process of the oxide Si film, a shallower P-type diffusion layer can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device in which an extremely shallow layer is formed in a semiconductor substrate.

[Conventional technology]

Conventionally, in order to form a shallow diffusion layer in a semiconductor substrate, a combination of ion implantation to introduce impurities and subsequent activation heat treatment (hereinafter referred to as anneal) with high-temperature short-time annealing or low-temperature long-time annealing is required. It is common to use technology.

FIG. 2 shows an example of the process of forming a P-type shallow diffusion layer on an N-type silicon substrate. First, as shown in FIG. Alternatively, a thermal oxide film 2 of about 200 layers is formed in an area including the planned area. This step is performed to suppress damage to the substrate surface due to subsequent ion implantation and channeling of implanted ions within the substrate. Next, as shown in FIG. 2, the surface of the substrate other than the area where the P-type silicon is to be formed is covered with a resist pattern 3 using a known photolithography technique, and this resist pattern 3 is used as a mask for ion implantation to remove the area where the P-type silicon is to be formed. BF ions, which are P-type impurities, are implanted into the region at an acceleration energy of 30 keV and a dose of 5×10′/ctR to form region 4.

At this point, the depth of BF has already reached around 2,000 people. Here, BF,'' is used as an ion species because compared to single boron B, BF,'' has a much shorter range in silicon at the same acceleration voltage, and is effectively a low-acceleration ion of boron B. This is because injection can be achieved.
This is currently widely used. Also, increase the acceleration voltage to 3
The reason for setting the voltage to 0 kV is due to the limitations of the ion implantation apparatus, since if the acceleration voltage is lower than this, the beam current will be extremely reduced, and the implantation processing time will be increased accordingly, which will cause problems in the processing. Next, as shown in FIG. 2C, BF,
``In order to change the ion-implanted region 4 to P-type silicon and form a P-type diffusion N5, the resist pattern 3 is removed and annealing is performed. ``Annealing for 130 minutes is necessary, and at that time boron is diffused, and the resulting PN junction position is approximately 3,000 minutes from the substrate surface. Even when annealing is performed at 1000° C. for 110 seconds using an apparatus, the bonding position never becomes less than 2000 Å.

As described above, as long as the current ion implantation method and subsequent annealing are combined, the P swelling diffusion layer in the N type substrate is 20
It cannot be made shallower than 00 people. When forming an N-swelled diffusion layer on a P-type substrate, similar problems exist, and it is difficult to form a shallow diffusion layer of 1000 Å or less, although this is not the case with P-swelled diffusion layers.

However, with the recent miniaturization of ICs, it has become necessary to form a shallow diffusion layer of 1000 Å or less, regardless of whether it is P type or N type. Furthermore, in order to increase the photocurrent and sensitivity of photodiodes and the like, it is necessary to introduce more light into the junction position. From that point, set the joining position to 100
It is necessary to set the polarity to 0 Å or less. Conventional bond forming methods for these elements have the above-mentioned limitations.

[Problem that the invention seeks to solve]

It is an object of the present invention to eliminate the above-mentioned drawbacks and provide a method for forming a polar diffusion layer with a thickness of 1000 Å or less.

[Means for solving problems]

According to the present invention, this purpose is achieved by a step of diffusing impurities into a predetermined region of a semiconductor substrate, followed by a low-temperature selective oxidation step of 800°C or less, and a step of removing the oxide film grown by the low-temperature selective oxidation step by wet etching. This is achieved by alternately repeating the above steps to reduce the depth of the impurity diffusion region to a predetermined value.

[Effect]

In the method of the present invention, a depth of 10
By etching a diffusion layer of 00 Å or more from the substrate surface, the depth of the diffusion layer is reduced to 1000 Å or less.The etching method uses low-temperature selective oxidation and wet etching, which causes no damage to the substrate. This method reduces the diffusion depth without changing the bonding position that has already been formed.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

Figure 1 shows an example of forming a P-type photodiode on an N-type silicon substrate.
A thermal oxide film 2 of about 200 layers is formed on the surface of the silicon substrate 1 where the photodiode is to be formed or a region including the area where the photodiode is to be formed. silicon nitride film 6
deposit.

Next, as shown in FIG. 1, the silicon nitride film 6 on the area where the photodiode is to be formed is etched and removed using the resist pattern 3 using a known photoetching technique.

Next, as shown in FIG.
A region 4 is formed by implanting a dose of /C11l.

Next, as shown in FIG. 1d, the resist pattern 3 is removed and annealing is performed for 1000'C for 110 seconds, thereby forming a P-type wave dispersion layer 5 with a depth of about 2000 layers. Note that the process up to this point is almost the same as the conventional technology.

Next, as shown in FIG. 1g, the thermal oxide film 2 directly above the P expansion diffusion layer 5 is removed by known wet etching using the CVD silicon nitride film 6 as a mask.

Next, as shown in FIG. 1f, a low-temperature selective silicon oxide film 7 is grown at 800° C. again using the CVD silicon nitride film 6 as a mask. The conditions at this time are hydrogen 3.5 I! ,
/min, and oxygen for 6 hours at 6.21/min to obtain a silicon oxide film with a thickness of 750 mm.

Furthermore, as shown in FIG.
About 500 people were displaced and became shallower, resulting in 150 people.
A zero polarity P type diffusion layer 51 is formed.

Furthermore, by repeating the low-temperature selective oxidation step shown in FIG. 1f and the wet etching step of the silicon oxide film shown in FIG.
Polar junctions of 0 Å or less are also possible.

Although the above example describes the formation of a P-swelled diffusion layer on an N-type substrate, it is clear that the present invention can also be applied to the formation of an N-swelled diffusion layer on a P-type substrate and the formation of a layer of the same conductivity type as the substrate. be.

〔Effect of the invention〕

According to the present invention, a diffusion layer with a depth of 1000 Å or more, which was formed by the conventional technique of ion implantation and subsequent annealing, is etched using the conventional technique by repeating a low-temperature selective oxidation technique of 800° C. or less and a known wet etching technique. It is now possible to form a polar impurity diffusion layer with a depth of 1000 Å or less, which could not be achieved with etching, and furthermore, it is possible to proceed with etching with almost no redistribution of impurities in the substrate and damage to the substrate surface due to oxidation and etching. .

[Brief explanation of drawings]

FIG. 1g-g is a process sectional view showing an embodiment of the present invention;
FIG. 2 axc is a process sectional view of the conventional method. l...N type silicon substrate, 5...P swelling diffusion layer, 5
1... Shallow P swelling diffusion layer, 6... CVD silicon nitride film, 7... Low temperature selective silicon oxide film. 5'1゜Figure 1

Claims (1)

[Claims] 1) After diffusing impurities into a predetermined region of a semiconductor substrate,
The depth of the impurity diffusion region is reduced to a predetermined value by alternately repeating a low-temperature selective oxidation step at 0° C. or lower and a step of removing the oxide film grown by the low-temperature selective oxidation step by wet etching. A method for manufacturing a featured semiconductor device.