JPS60149125A - Method for impurity doping into semiconductor substrate - Google Patents

Abstract

PURPOSE:To improve the electrical characteristics of a semiconductor element without giving a damage on a substrate by a method wherein a covering layer composed of a polycrystalline semicoiductor, an amorphous semiconductor, a semiconductor oxide, a semiconductor nitride and etc. on the semiconductor substrate is arranged and impurity ions are implanted in a manner the range of ions is located on a boundary of the covering layer and the substrate, followed by heat treatment to diffuse said ions to the predetermined depth. CONSTITUTION:A surface of a P type Si substrate 1 is coated with a covering layer 2 of SiO2 or the like and then the substrate is covered with a resist film 3 of the predetermined shape. By using this as a mask, the whole surface is irradiated with a P-ion beam 4. At this time, a thickness of the film 2 and an acceleration voltage of ion implantation are selected properly so that a peak of the quantity of implanted beam 4 enters in the film 2 only by 0.03mum from a boundary of the substrate 1 and the film 2. Consequently, most of damages due to the implanted impurity 5 are accepted by the film 2 thereby preventing a damage of the substrate 1. After that, heat treatment with 1,000-1,200 deg.C is performed for 10-30min as usually to diffuse the impurity 5 and an N type region 6 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a method of doping impurities into a constant region D1 of a semiconductor substrate using ion implantation technology.

[Prior art and its problems]

Adding impurities to semiconductor substrates by ion implantation has recently become widely applied because, compared to conventional impurity diffusion methods, ions are directly implanted into the substrate, allowing for extremely accurate control of impurity concentration. .

However, when ions are directly implanted into the substrate, crystal defects are generated due to collisions between the ions and lattice atoms of the semiconductor, which causes deterioration of the electrical characteristics of the semiconductor element such as an increase in junction leakage current. Various types of annealing have been attempted to eliminate the defects, but in particular when shallow junctions are required due to high-concentration ion implantation, it is not possible to perform annealing at a hot pot temperature for a long time, resulting in minute defects. Defects often remained.

[Purpose of the invention]

The present invention provides an impurity addition method that eliminates these drawbacks, maintains the advantages of ion implantation technology, does not damage the semiconductor substrate, and can improve the electrical characteristics of the resulting semiconductor device. The purpose is to

[Key points of the invention]

According to the present invention, a coating layer is formed on the surface of a semiconductor substrate, ions of a certain impurity are implanted onto the coating layer so that their range is near the interface between the coating layer and the substrate, and then The above object is achieved by performing a heat treatment to diffuse impurities to a predetermined depth 1 in the substrate. As the covering layer, it is effective to use any one of a polycrystalline semiconductor film, an amorphous semiconductor film, a semiconductor oxide film, and a semiconductor nitride film.

[Embodiments of the invention]

An embodiment of the present invention is shown in FIG. Semiconductor substrate 2 For example, P-type silicon wafer 1 is processed by CVD method! l
llllll Silicon oxide gold film 2 is formed. After depositing a resist 3 with a predetermined pattern by a photoetch process, ion implantation is performed using a thin ion beam 4 (see Fig. 1).
a) ), o At this time, the thickness of the oxide film 2 and the accelerating voltage for ion implantation are appropriately selected. For example, the oxide film thickness is set to 0.15.
If ions are implanted at 100 keV, the range is 0.12 μm. Therefore, as shown in the ion implantation dose distribution in FIG. Ions can be implanted so that the peak of the implantation amount occurs at the point where the ions enter the 03 μm oxide film. If the peak is made to be near the interface between the oxide film 2 and the substrate 1 in this way, most of the damage caused by the implanted impurity 5 will be absorbed by the oxide film 2. For example, usually I X 1016
If high-dose ion implantation is performed on a silicon wafer, the surface becomes amorphous and some damage is caused, but the method according to the present invention causes very little damage to the silicon wafer 1. Then, by heat treatment at 1000 to 1200°C for 10 to 30 minutes, the silicon is diffused to form the N shadow region 6 as shown in FIG. 1(b), forming a shallow junction with a depth of about 1 μm. Can be done.

Thereafter, as shown in FIG. 1C, a portion of the oxide film 2 is removed to expose the surface of the N shadow region 6, and a stain electrode 7 is deposited by metal vapor deposition or the like. The remaining oxide film 2 serves as a protective film for the PN junction 8.

When a crab film is used as the oxide film, it can be similarly used as a sleep retention film. However, it is also possible to provide a film of polycrystalline silicon, amorphous silicon, or another semiconductor film on the substrate and use it as a preliminary ion implantation layer.

FIG. 3 shows another embodiment, in which parts common to those in FIG. 1 are given the same reference numerals. In this embodiment, the thin ion beam 4 is implanted over the entire surface, and its range is made to stop near the interface between the acid ratio film 2 and the silicon wafer 1, as in the case of FIG. 1 (FIG. 3(a)). ), then Figure 3(b)
As shown in FIG. 3(C), the oxide film 2 in areas other than the required areas is removed by a photoetch process, and then heat treatment is performed to diffuse p-5 in the oxide film 2. As shown, N shadow areas 6 similar to those in FIG. 1(e) are formed.

〔Effect of the invention〕

In the present invention, when adding cine fine particles by ion implantation, a coating layer is formed on the substrate in order to prevent damage to the substrate, and the peak of ion implantation is near the interface between the coating layer and the substrate. Then, by adjusting the acceleration energy and implanting the impurity so that it comes to the covering layer side, and performing diffusion using the impurity implanted near this interface as a diffusion source, a defect-free and shallow junction can be created. Further, since this covering layer can be used as a selective diffusion source by leaving only a predetermined region, the effect obtained is extremely large.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view sequentially showing the steps of an embodiment of the present invention, FIG. 2 is a diagram showing the distribution of ion-implanted impurities in the depth direction,
FIG. 3 is a sectional view sequentially showing the steps of another embodiment of the present invention. 1... Silicon wafer, 2... Oxide film, 4... Ion beam, 5... Implanted impurity (thin), 6... ...N-shaped dispersion layer. Figure 1, Figure 2, Figure 3.

Claims (1)

[Claims] 1) A coating layer is formed on a semiconductor substrate, ions of a predetermined impurity are implanted from above the coating layer so that the range thereof is near the interface between the coating layer and the substrate, and then heat treatment is performed. A method for adding impurities to a semiconductor substrate, the method comprising diffusing the impurities to a predetermined depth in the substrate. 2. A method for adding impurities to a semiconductor substrate according to claim 1, wherein the coating layer is made of a polycrystalline semiconductor, an amorphous semiconductor, a semiconductor oxide, or a semiconductor nitride.