JPH03209816A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To easily alleviate a strong electric field generated on the end part of an impurity diffusion layer, and to prevent the deterioration in characteristics of a semiconductor device by a method wherein ions are implanted using a mask on which a tapered aperture is formed. CONSTITUTION:When a P-type base layer 10 is formed, a taper 7A is formed on a silicon nitride film 7 which becomes a mask. Accordingly, the density of boron, to be introduced into the inside of a semiconductor substrate from the part where the taper 7A is formed, changes according to the variation of thickness of the silicon nitride film 7. To be more precise, the more the film thickness of the silicon nitride film 7 become thicker, the more the density of boron introduced into the semiconductor substrate becomes lower, and the boron is not introduced into the semiconductor thick film substrate masked by a polycrystalline silicon film 8. As a result, the concentration distribution of impurities in the P-type base layer 10 becomes gentle, an electric field is not concentrated on the corner edge part of a diffusion layer, and the deterioration in characteristics of the semiconductor device can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming an impurity diffusion layer.

[Conventional technology]

Formation of a diffusion layer in a conventional semiconductor device will be explained using drawings. FIG. 5 is a cross-sectional view of a semiconductor chip for explaining an example of a step of forming a base diffusion layer in an NPN bipolar semiconductor device.

First, as shown in FIG. 5(a), after forming a collector buried layer 2 on a P-type semiconductor substrate 1, an N-type epitaxial layer 5 is grown, and then an island-like isolation region is formed using silicon oxide M3. . The highly concentrated N+ type impurity diffusion layer 4 forms an electrical lead-out region to the semiconductor upper surface of the collector region.

The base diffusion layer is first formed by introducing an impurity such as boron to form a P-type conductive layer at a predetermined position within the island-like isolation region.
Ion implantation methods have come to be widely used. Introducing impurities into a predetermined position in a semiconductor substrate by ion implantation can be done by directly implanting the impurity into the semiconductor substrate using a photoresist as a mask, or by forming a silicon oxide film on the semiconductor substrate and then depositing the impurity on the silicon substrate. By coating the photoresist on the semiconductor substrate and patterning the photoresist so that only the predetermined positions where the impurity diffusion layer will be formed on the semiconductor substrate are removed, the impurities are removed into the silicon substrate through the silicon oxide film using the photoresist as a mask. The method used is to introduce

FIG. 5(b) shows the latter method using a photoresist film 9 on a semiconductor substrate as a mask. At this time the fifth
FIG. 6 shows the concentration of unimplanted boron along the broken line G I H of the P-type base layer 10 in FIG. 6(b). Note that the broken line GIH is parallel to the surface of the semiconductor substrate.

The concentration of boron is constant in the area where the photoresist is not coated, but the concentration decreases rapidly at the edge of the photoresist, and the concentration gradient of boron is sharp at the edge of the photoresist. It shows that the change in This is because the introduction of impurities by ion implantation has a smaller lateral spread within the semiconductor substrate than the introduction of impurities into the semiconductor substrate by thermal diffusion. Finally, by performing annealing, the boron introduced into the semiconductor substrate is activated, and the P-type base layer 10 is activated.
is formed.

[Problem to be solved by the invention]

In the conventional semiconductor device manufacturing method described above, the concentration of the impurity diffusion layer introduced by ion implantation in the direction parallel to the semiconductor substrate rapidly decreases at the edge of the mask, which is opposite to that of the impurity diffusion layer. A sharp carrier distribution gradient occurs at the boundary with the surrounding conductive layer,
Especially at the corner ends of the impurity diffusion layer, electric field concentration occurs during semiconductor device operation, resulting in a decrease in breakdown voltage characteristics between the base and collector in bipolar semiconductor devices, and generation of pot electrons near the train in MOS semiconductor devices. It has the disadvantage that it does not cause any deterioration in the characteristics of the semiconductor device, such as a decrease in breakdown voltage between the source and the train due to this.

[Means to solve the problem]

A method of manufacturing a semiconductor device according to the present invention includes ion-implanting impurities using a mask having an opening formed on a semiconductor substrate to form an impurity diffusion layer. It is something that is formed by Dever.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to (e) are cross-sectional views of a semiconductor chip showing the process of forming a base diffusion layer when the present invention is applied to an NPN type semiconductor device as a first embodiment, and FIG. 1st
P-type base layer 10 along the broken line ACB shown in Figure (e)
FIG. 3 is a concentration distribution diagram of impurities in Note that the broken line ACB is parallel to the surface of the semiconductor substrate.

First, as shown in FIG. 1(a), an island-like isolation region is formed by a silicon oxide film 3 in a predetermined region in a P-type semiconductor substrate 1, and an N-type isolation region is formed by high-concentration phosphorus at a predetermined position within the island-like isolation region. After the collector buried layer 2 is formed by impurity diffusion, an N-type epitaxial layer 5 is formed. Next, after forming the N+ type scattering layer 4 as an electrical lead-out region to the surface, a modified silicon oxide film 6 with a thickness of about 500 layers is grown on the surface of the semiconductor substrate by thermal oxidation or the like. Furthermore, about 1000 silicon nitride films 7 are grown on the silicon oxide film 6 by the CVD method, and about 500 polycrystalline silicon films 8 are grown on the silicon nitride films 7 -T- by the modified VD method.

Next, as shown in FIG. 1(b), a photoresist film 9 is applied onto the polycrystalline silicon film 8, and then developed so that only the region where the base will be formed is removed.

Next, as shown in FIG. 1<c>, polycrystalline silicon film 8 and silicon nitride film 7 are etched by chemical dry etching using CF4-based gas using photoresist film 9 as a mask. At this time, since the etching rates of the polycrystalline silicon film 8 and the silicon nitride film 7 are greatly different, a taper 7A is formed in the silicon nitride film 7.

This is because chemical tri-etching is isotropic etching, and the etching speed of polycrystalline silicon film 8 is higher than that of silicon nitride film 7, so while silicon nitride film 7 is being etched, polycrystalline silicon This is because the etching of the film 8 in the direction parallel to the semiconductor substrate progresses, and the portions of the silicon nitride film 7 from which the polycrystalline silicon film 8 has been removed are successively etched.

Next, as shown in FIG. 1(d), the photoresist film 9 is peeled off, and using the polycrystalline silicon film 8 and silicon nitride film 7 as masks, P-type impurities, such as boron, are implanted into the semiconductor substrate by ion implantation. A P-type base layer 10 is formed by introducing energy at 20 to 30 ke and a dose of 5X] at a dose of O'2 to 5 x 10"cm-2. At this time, a taper 7A is formed on the silicon nitride film 7 that serves as a mask. The thickness of the nitride film increases continuously from the part where the silicon nitride film 7 has been removed toward the outside, and in the part where the silicon nitride film 7 has been removed, boron is formed at a constant concentration in the semiconductor through silicon oxide M6. It is introduced into the inside of the substrate, and that part acts as a base region during the operation of the semiconductor device and becomes a region that controls the electrical characteristics of the semiconductor device. The concentration of introduced boron changes depending on the change in the thickness of the silicon nitride film 7. In other words, the thicker the silicon nitride film 7 becomes, the lower the concentration of boron introduced into the semiconductor substrate becomes. No boron is introduced into the inside of the semiconductor substrate, which has become thicker and is also masked by polycrystalline silicon M8.

Next, as shown in FIG. 1(e), the polycrystalline silicon film 8 and silicon nitride film 7, which served as a mask during boron ion implantation, are removed. Finally, annealing is performed to recover crystal defects generated during ion implantation.

FIG. 2 shows the boron concentration distribution along the broken line ACB of the P-type base layer 10 shown in FIG. 1(e).

In this way, the problem with the first embodiment is that, as shown in FIG. 2, the impurity concentration distribution in the P-type base layer 10 becomes gentle, so that electric field concentration occurs at the corner ends of the diffusion layer. will disappear.

FIGS. 3(a) to 3(f) are cross-sectional views of a semiconductor chip for explaining a second embodiment of the present invention.
A case where the present invention is applied to forming a source and a drain of an O3 semiconductor device is shown.

First, as shown in FIG. 3(a), an isolation region is formed on the P-type semiconductor substrate 1 using a silicon oxide film 3A. Next, a silicon nitride film 7 and a polycrystalline silicon film 8 are formed on the silicon oxide film 6A in the same manner as in the first embodiment.

Next, as shown in FIG. 3(b), the polycrystalline silicon film 8 in the region where the source and drain are to be formed in the isolation region is removed.

Next, as shown in FIG. 3(c), after forming a photoresist film 9A, only the regions where the source and drain will be formed are removed.

Next, as shown in FIG. 3(d), a taper 7A is formed in the silicon nitride film 7 by chemical dry etching using a CF4 gas. The principle and principle are the same as described in the first embodiment.

Next, as shown in FIG. 3(e), after the photoresist film 9A is peeled off, an N-type impurity, for example, arsenic, is ion-implanted to form a source/drain 20. As a result, the arsenic concentration distribution in the source train gate direction changes extremely gradually.

9 Finally, annealing is performed to restore the crystallinity of the semiconductor substrate.

FIG. 4 shows the concentration distribution of arsenic introduced along the broken line EFD of the source/drain 20 shown in FIG. 3(f).

In this way, according to the second embodiment, it is possible to avoid the generation of a strong electric field near the drain and the generation of hot electrons associated with it.

〔Effect of the invention〕

As explained above, the present invention introduces impurities into a semiconductor substrate by ion implantation using a mask with a tapered opening, and by forming a diffusion layer, the impurity concentration is reduced at the edge of the semiconductor substrate. Since it can have an extremely gentle distribution, it has the effect of alleviating the strong electric field that tends to occur at the end of the impurity diffusion layer during operation of the semiconductor device, and preventing deterioration of the characteristics of the semiconductor device.

[Brief explanation of drawings]

0- FIGS. 1(a) to (e) are cross-sectional views of a semiconductor chip for explaining the first embodiment of the present invention, and FIG. 2 is FIG. 1(e).
Figure 3 (a) is a concentration distribution map of impurities along the broken line ACB of
) to (f) are cross-sectional views of the semiconductor chip for explaining the second embodiment, FIG. 4 is an impurity concentration distribution diagram along the broken line DEF in FIG. 3(f), and FIG. 5(a) (b) is a sectional view of a semiconductor chip for explaining a conventional example, and FIG. 6 is an impurity concentration distribution diagram along the broken line GIH in FIG. 5(b). 1...P-type semiconductor substrate, 2...Collector, 3...
Silicon oxide film, 4... N+ type scattered layer 5... N type epitaxial layer, 6, 6A... Silicon oxide film, 7
...Silicon nitride film, 7A...Taper, 8...
Polycrystalline silicon film, 9,9A...photoresist film,
10...P-type base layer, 20...source/drain.

Claims (1)

[Claims] In a method for manufacturing a semiconductor device in which an impurity is ion-implanted using a mask having an opening formed on a semiconductor substrate to form an impurity diffusion layer, the opening of the mask is tapered. A method for manufacturing a featured semiconductor device.