JPS60116164A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60116164A JPS60116164A JP58225893A JP22589383A JPS60116164A JP S60116164 A JPS60116164 A JP S60116164A JP 58225893 A JP58225893 A JP 58225893A JP 22589383 A JP22589383 A JP 22589383A JP S60116164 A JPS60116164 A JP S60116164A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- substrate
- ion implantation
- film
- conductive type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
（ａ） 発明の技術分野
本発明は半導体装置の製造方法に係り、特に相補型ＭＯ
５電界効果半導体装置（以下ＣＭＯ３ＦＥＴと略記する
）の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical field of the invention The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device, and in particular, a method for manufacturing a semiconductor device.
5 Field Effect Semiconductor Device (hereinafter abbreviated as CMO3FET).
（ｂｌ 従来技術と問題点
従来ＣＭＯ８ＦＥＴを製造するに際しては、まず第１図
１８＋に示すように、−導電型例えばｎ型のシリコン（
Ｓｔ）基板１に加熱酸化処理を施して二酸化シリコン（
Ｓ’ｉ０２ ）膜２を形成し、次いでこれの上に所定の
パターンに従ってレジスト膜３を形成したのち、このレ
ジスト膜３をマスクとしてイオン注入法により反対導電
型即ちｐ型の不純物９例えばボロン（Ｂ）を上記Ｓｉ基
板１表面に注入し、更に加熱処理を施して注入した不純
物を活性化して島状の反対導電型即ちｐ型頭域（以下こ
れをｐ−ｗｅｌｌ、ｎ型島状領域の場合はｎ−ｗｅｌｌ
と称する）４を形成する。(bl) Prior Art and Problems When manufacturing a conventional CMO8FET, first, as shown in FIG.
St) Heat oxidation treatment is applied to the substrate 1 to form silicon dioxide (
S'i02 ) film 2 is formed, and then a resist film 3 is formed on this according to a predetermined pattern. Using this resist film 3 as a mask, an impurity 9 of the opposite conductivity type, that is, p-type, is implanted by ion implantation. B) is implanted into the surface of the Si substrate 1, and heat treatment is performed to activate the implanted impurity and form an island-like opposite conductivity type, that is, a p-type head region (hereinafter referred to as p-well, an n-type island region). If n-well
4).
次いで上記マスクとして用いたレジスト膜３及びｓ＋ｏ
２Ｂ＊２を除去したのち、あらためて加熱処理を施すこ
とによりＳｉ基板１表面を酸化してゲート酸化膜５を形
成し、次いでこのゲート酸化膜５上に化学気相成長法（
Ｃ’Ｖ Ｄ法）を用いて多結晶シリコン層を成長させ、
次いでこの多結晶シリコン層を選択的に除去して多結晶
シリコン層よりなるゲート６を形成していた。Next, the resist film 3 used as the mask and s+o
After removing 2B*2, the surface of the Si substrate 1 is oxidized by heat treatment again to form a gate oxide film 5, and then chemical vapor deposition (CVD) is performed on this gate oxide film 5.
Grow a polycrystalline silicon layer using C'VD method),
Next, this polycrystalline silicon layer was selectively removed to form a gate 6 made of the polycrystalline silicon layer.
上述の如〈従来の製造方法においては、ここまでの製造
工程において加熱処理が３回にわたって行うことが必要
であった。そのため製造工程が煩雑であるのみならず、
ゲート酸化工程においてｐ−ｗｅｌ１４表面の不純物の
アウト・ディフュージョンが起こる等の問題がある。As mentioned above, in the conventional manufacturing method, it was necessary to perform the heat treatment three times in the manufacturing process up to this point. Therefore, not only is the manufacturing process complicated,
There are problems such as out-diffusion of impurities on the surface of the p-well 14 in the gate oxidation process.
（Ｃ） 発明の目的
本発明の目的は上記島状の反対導電型領域を形成するま
での加熱処理工程を極力少なくし得る半導体装置の製造
方法を提供することにある。(C) Object of the Invention An object of the present invention is to provide a method for manufacturing a semiconductor device that can minimize the number of heat treatment steps required to form the island-shaped regions of opposite conductivity type.
（ｄｌ 発明の構成
本発明の特徴は、−導電型を有する半導体基板表面に所
定の絶縁膜と該絶縁膜上に多結晶半導体層を形成し、次
いで該多結晶半導体層上に所定の開口を有するイオン注
入阻止層を形成し、次いで該イオン注入阻止調をマスク
として反対導電型の不純物を前記多結晶半導体層及び絶
縁膜を透過して前記半導体載板の前記イオン注入阻止層
の開口直下部表面にイオン注入法により注入する工程を
含むことにある。(dl Structure of the Invention The present invention is characterized by forming a predetermined insulating film on the surface of a semiconductor substrate having a conductivity type and a polycrystalline semiconductor layer on the insulating film, and then forming a predetermined opening on the polycrystalline semiconductor layer. Then, using the ion implantation blocking layer as a mask, an impurity of the opposite conductivity type is transmitted through the polycrystalline semiconductor layer and the insulating film to form an ion implantation blocking layer directly under the opening of the ion implantation blocking layer of the semiconductor mounting board. The method includes a step of implanting into the surface by an ion implantation method.
（ｆｌ） 発明の実施例 以下本発明の一実施例を図面を参照しながら説明する。(fl) Examples of the invention An embodiment of the present invention will be described below with reference to the drawings.
第２図（ａｌ及び（ｂ）は本発明の一実施例を製造工程
の順に示す要部断面図である。FIGS. 2A and 2B are sectional views of essential parts of an embodiment of the present invention showing the manufacturing steps in order.
本実施例においては同図（８）に見られるように、−導
電型を有する半導体基板２例えばｎ型のＳｔ基板ｌを加
熱酸化して凡そ１０００ （人〕の厚さを有するゲート
絶縁膜（本実施例ではゲート酸化膜）５を形成したのち
、これの上にＣＶＤ法により凡そ３０００ （人〕の厚
さの多結晶半導体基板例えば多結晶シリコン層７を被着
せしめる。次いで該多結晶シリコン層７上に、開口８を
有するレジスト膜３を形成する。このレジスト膜３は後
述する如く、このあとのイオン注入工程におけるマスク
として用いるイオン注入阻止層であって、上記開口８を
除く他の部分に照射されるイオンを阻止するのに要する
厚さに形成しておく。この目的から本実施例ではレジス
ト膜３の厚さを凡そ１〜１．５〔μｍ〕とした。In this example, as shown in FIG. 8, a semiconductor substrate 2 having a negative conductivity type, for example an n-type St substrate l, is heated and oxidized to form a gate insulating film ( In this embodiment, after forming a gate oxide film (5), a polycrystalline semiconductor substrate, e.g., a polycrystalline silicon layer 7, having a thickness of approximately 3000 mm is deposited thereon by the CVD method. A resist film 3 having an opening 8 is formed on the layer 7. As will be described later, this resist film 3 is an ion implantation blocking layer used as a mask in the subsequent ion implantation process, and other than the opening 8 is The resist film 3 is formed to have a thickness necessary to block ions irradiated onto the portion.For this purpose, in this embodiment, the thickness of the resist film 3 is approximately 1 to 1.5 [μm].
なおイオン注入工程のマスクとして用いるイオン注入阻
止層としては、上述のレジスト膜３に変えてアルミニウ
ム（ＡＯ）層或いはＣＶＤ法によって形成した二酸化シ
リコン（５ｔ０２）膜等を用いても良い。Note that as the ion implantation blocking layer used as a mask in the ion implantation process, an aluminum (AO) layer, a silicon dioxide (5t02) film formed by CVD method, or the like may be used instead of the above-mentioned resist film 3.
次いでこのように形成したレジスト膜３をマスクとして
イオン注入法を施し、反対導電型即ち本実施例ではｐ型
の不純物１例えばボロン（Ｂ）をＳｉ基板１表面に注入
する。本実施例ではボロン（Ｂ）を多結晶シリコン層７
及びゲート酸化膜５を通してＳｉ基板１表面に注入する
ので、この工程における注入エネルギは凡そ２００ （
ｋ ｅＶ］とした。Next, an ion implantation method is performed using the resist film 3 thus formed as a mask, and an impurity 1 of the opposite conductivity type, that is, a p-type in this embodiment, such as boron (B), is implanted into the surface of the Si substrate 1. In this embodiment, boron (B) is added to the polycrystalline silicon layer 7.
Since the implantation is performed on the surface of the Si substrate 1 through the gate oxide film 5, the implantation energy in this step is approximately 200 (
keV].
こうすることにより上記開口８部では注入イオンは多結
晶シリコン屑７及びゲート酸化膜５を透過して、Ｓｉ基
板１の表面に注入され、伯の部分ではマスクとして用い
たレジスト膜３によりほぼ阻止されて、これの下層には
殆ど注入されない。上記条件によれば、Ｓｉ基板１表面
に注入されたイオンは、分布のピークが多結晶シリコン
層７０表面から凡そ６０００ （人〕の深さとなるよう
な分布となり、その濃度は几そ２ｘ１０３ （ｃｍ−２
）となる。By doing this, the implanted ions pass through the polycrystalline silicon chips 7 and the gate oxide film 5 and are implanted into the surface of the Si substrate 1 in the opening 8, and are almost blocked in the circled portion by the resist film 3 used as a mask. The layer below this is hardly injected. According to the above conditions, the ions implanted into the surface of the Si substrate 1 have a distribution such that the peak of the distribution is approximately 6,000 cm deep from the surface of the polycrystalline silicon layer 70, and the concentration is approximately 2 x 10 cm. -2
).
次いで上記マスクとして用いたレジスト膜３を除去した
のち、例えば１１５０（”Ｃ３程度の温度において加熱
処理を施すことにより、注入したイオンの活性化を行っ
て島状の反対導電型領域１本実施例ではｐ型領域即ちｐ
−ｗｅｌｌを形成する。但しこの活性化のための加熱処
理工程は必ずしもこの段階で実施する必要はなく、この
あとの工程において実施されるアイソレーション或いは
コンタクト領域形成のだめの加熱処理工程において同時
に活性化を行なっても良い。Next, after removing the resist film 3 used as the mask, the implanted ions are activated by heat treatment at a temperature of, for example, 1150 (C3) to form an island-shaped region of the opposite conductivity type. Then, the p-type region, that is, p
- form a well. However, the heat treatment step for activation does not necessarily need to be performed at this stage, and activation may be performed simultaneously in the heat treatment step for isolation or contact region formation performed in a subsequent step.
次いで同図ｔｂｌに見られる如く、上記多結晶シリコン
層７を選択的に除去して、ｐ−ｗｅｌｌ上及びｎ型領域
上の所定の位置にのみ多結晶シリコン層７を残留せしめ
る。この残留せる多結晶シリコン層はケート電極６とな
るものである。Next, as shown in FIG. tbl, the polycrystalline silicon layer 7 is selectively removed, leaving the polycrystalline silicon layer 7 only at predetermined positions on the p-well and n-type region. This remaining polycrystalline silicon layer becomes the gate electrode 6.
以上により本実施例を用いてＳｉ基板１と反対導電型の
島状領域（即ちｐ−ｗｅｌｌまたはｎ−ｗｅｌｌ）が形
成された。As described above, an island-like region (that is, a p-well or an n-well) having a conductivity type opposite to that of the Si substrate 1 was formed using this example.
このあとは通富の製造工程に従って図示はしていないが
、ソース領域、ドレイン領域、及び各部の電極等を形成
して半導体装置が完成する。After this, although not shown in the drawings, a source region, a drain region, electrodes of various parts, etc. are formed according to Tsutomi's manufacturing process, and the semiconductor device is completed.
上述の説明６；より明らかなよ痕３、本実施例ではｐ−
ｗｅｌｌあるいはｎ−ｗｅｌｌを形成するまでの工程に
おいて、加熱処理工程は１回のみ施せば良い。従って製
造工程が非常に簡単化され、しかもアウトディフュージ
ョンを生じないので、製造工程及び特性の制御が容易に
なるという利点もある。Explanation 6 above; more obvious mark 3, in this example p-
In the process up to forming a well or an n-well, the heat treatment process only needs to be performed once. Therefore, the manufacturing process is greatly simplified, and since outdiffusion does not occur, there is an advantage that the manufacturing process and characteristics can be easily controlled.
（ｆｌ 発明の詳細
な説明した如く本発明によれば、ＣＭＯＳＦ Ｅ Ｔの
製造工程が簡単化され、しかも製造工程の制御性が向上
する。(fl) As described in detail, according to the present invention, the manufacturing process of CMOSFET is simplified and the controllability of the manufacturing process is improved.
第１図は従来の半導体装置の製造方法のゲ１を点を説明
するための要部断面図、第２図は本発明の一実施例を製
造工程の順に示す要部断面図である。
図において、ｌは−・導電型を有する半導体基板（シリ
コン基板）、３はイオン注入阻止層（レジスト膜）、４
ば反対導電型を有する島状領域、５はゲート絶縁Ｂ’Ａ
（ゲート酸化膜）、６は多結晶シリコンよりなるゲー
ト電極、７は多結晶半導体層（多結晶シリコン層）、８
は開口を示す。FIG. 1 is a cross-sectional view of a main part for explaining the main points of a conventional method for manufacturing a semiconductor device, and FIG. 2 is a cross-sectional view of a main part showing an embodiment of the present invention in the order of manufacturing steps. In the figure, l is a semiconductor substrate (silicon substrate) having a - conductivity type, 3 is an ion implantation blocking layer (resist film), and 4 is
5 is an island-like region having an opposite conductivity type, and 5 is a gate insulation B'A.
(gate oxide film), 6 is a gate electrode made of polycrystalline silicon, 7 is a polycrystalline semiconductor layer (polycrystalline silicon layer), 8
indicates an opening.
Claims (1)
縁膜上に多結晶半導体層を形成し、次いで該多結晶半導
体層上に所定の開口を有するイオン注入阻止層を形成し
、次いで該イオン注入阻止層をマスクとして反対導電型
の不純物を前記多結晶半導体層及び絶縁膜を透過して前
記半導体基板の前記イオン注入阻止層の開口直下部表面
にイオン注入法により注入する工程を含むことを特徴と
する半導体装置の製造方法。A predetermined insulating film and a polycrystalline semiconductor layer are formed on the surface of a semiconductor substrate having one conductivity type, and then an ion implantation blocking layer having a predetermined opening is formed on the polycrystalline semiconductor layer. The step includes a step of implanting an impurity of the opposite conductivity type through the polycrystalline semiconductor layer and the insulating film into the surface of the semiconductor substrate directly below the opening of the ion implantation blocking layer by an ion implantation method using the ion implantation blocking layer as a mask. A method for manufacturing a semiconductor device, characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58225893A JPS60116164A (en) | 1983-11-29 | 1983-11-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58225893A JPS60116164A (en) | 1983-11-29 | 1983-11-29 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60116164A true JPS60116164A (en) | 1985-06-22 |
Family
ID=16836523
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58225893A Pending JPS60116164A (en) | 1983-11-29 | 1983-11-29 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60116164A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04138029U (en) * | 1991-06-19 | 1992-12-24 | 中井工業株式会社 | Belt conveyor installation structure |
-
1983
- 1983-11-29 JP JP58225893A patent/JPS60116164A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04138029U (en) * | 1991-06-19 | 1992-12-24 | 中井工業株式会社 | Belt conveyor installation structure |
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