JPS63177513A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS63177513A
JPS63177513A JP1025787A JP1025787A JPS63177513A JP S63177513 A JPS63177513 A JP S63177513A JP 1025787 A JP1025787 A JP 1025787A JP 1025787 A JP1025787 A JP 1025787A JP S63177513 A JPS63177513 A JP S63177513A
Authority
JP
Japan
Prior art keywords
phosphorus
region
oxide film
temperature
type semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1025787A
Other languages
Japanese (ja)
Other versions
JPH07118472B2 (en
Inventor
Hidetaka Yamagishi
山岸 秀隆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62010257A priority Critical patent/JPH07118472B2/en
Publication of JPS63177513A publication Critical patent/JPS63177513A/en
Publication of JPH07118472B2 publication Critical patent/JPH07118472B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To form a junction which has a favorable crystalline property and a depth of around 1.0-2.0mum but can not be formed by merely conducting individual implantation of respective ions by using implantation of specified numbers of phosphorus and arsenic ions in combination through a thin oxide film formed on the surface of a semiconductor substrate. CONSTITUTION:An N<+> type buried layer 2 is formed at a P-type semiconductor substrate 1 and an N-type semiconductor region 3 running as a collector is formed through an epitaxial growth. Then a P-type base region 5 is formed at the N-type semiconductor region 3 running as the collector of a bipolar transistor, for example. The oxide film 7 is prepared and a part of its oxide film where an emitter region 6 and a collector-contact region 4 are to be formed is removed and a thin oxide film is provided. Then phosphorus is ion-implanted by a dose of 3X10<15>-1.5X10<16>/cm<2> and arsenic is ion-implanted by the dose of 3X10<15>/cm<2> or less through the thin oxide film and the emitter region 6 and the collector-contact region 4 are formed. Subsequently, they are treated by heat and the emitter region having a favorable crystalline property and a depth of around 1.0-2.0mum is formed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はシリコン基板に不純物をイオン注入することに
より高濃度の半導体領域を形成する半導体装置の製造方
法に関し、特にリンイオンのイオン注入と砒素イオンの
イオン注入を併用することによって1.0〜2.0μm
の深さを有する接合を形成する半導体装置の製造方法に
関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device in which a highly concentrated semiconductor region is formed by ion-implanting impurities into a silicon substrate, and in particular, ion-implantation of phosphorus ions and arsenic ions. 1.0 to 2.0 μm by using ion implantation
The present invention relates to a method for manufacturing a semiconductor device that forms a junction having a depth of .

〔従来の技術〕[Conventional technology]

従来、不純物をイオン注入することによって高濃度のN
型半導体領域を形成する製造方法には、  。
Conventionally, high concentration of N was achieved by ion implantation of impurities.
The manufacturing method for forming the type semiconductor region includes:

リンイオンもしくは、砒素イオンを単独にイオン注入し
、1000℃以上の高温アニールを行い、不純物の活性
化および不純物の押込みを行っていた。
Phosphorus ions or arsenic ions were ion-implanted singly, and high-temperature annealing at 1000° C. or higher was performed to activate and push impurities.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の製造方法においては下記の欠点がある。 The conventional manufacturing method described above has the following drawbacks.

(1)リンイオンのイオン注入を行い高濃度のN型半導
体領域を形成する場合、リンイオン注入に起因する結晶
欠陥を除くには、薄い酸化膜を介し、リンイオン注入を
行った後に、700〜1000℃の温度でアニールを行
い、1060℃以上の温度において熱処理を行う必要が
ある。
(1) When ion implanting phosphorus ions to form a highly concentrated N-type semiconductor region, in order to remove crystal defects caused by phosphorus ion implantation, it is necessary to implant phosphorus ions through a thin oxide film and then heat the phosphorus ions at 700 to 1000°C. It is necessary to perform annealing at a temperature of 1060° C. or higher, and heat treatment at a temperature of 1060° C. or higher.

この場合、結晶欠陥の回復には、1060℃以上の熱処
理が不可欠であり、この1060℃以上の熱処理のため
に、形成可能な接合の深さは2.0μm以上となり2.
0μm以下の接合は形成できない。
In this case, heat treatment at 1060°C or higher is essential to recover crystal defects, and because of this heat treatment at 1060°C or higher, the depth of the bond that can be formed is 2.0 μm or more.
A junction of 0 μm or less cannot be formed.

(2)砒素イオンのイオン注入を行い高濃度のN型半導
体領域を形成する場合、砒素イオン注入に起因する結晶
欠陥は1000℃以上の温度でアニールを行うことによ
って素子特性に影響を与えないレベルまで回復する。し
かし同一半導体基板上にホウ素を用いたP型半導体領域
を持つ通常の集積回路においては、熱処理の制限により
、形成可能な接合の深さは1.0μm以下である等の欠
点がある。
(2) When arsenic ion implantation is performed to form a highly concentrated N-type semiconductor region, crystal defects caused by arsenic ion implantation can be removed to a level that does not affect device characteristics by annealing at a temperature of 1000°C or higher. recover to. However, a typical integrated circuit having a P-type semiconductor region using boron on the same semiconductor substrate has drawbacks such as the fact that the depth of the junction that can be formed is 1.0 μm or less due to heat treatment limitations.

本発明の目的は、従来の半導体装置の製造方法の欠点を
除去し、結晶性が良好で、がっ!、0〜2.0μmの深
さの接合を形成することができる半導体装置の製造方法
を提供することにある。
The purpose of the present invention is to eliminate the drawbacks of conventional semiconductor device manufacturing methods, to achieve good crystallinity, and to achieve excellent crystallinity. , it is an object of the present invention to provide a method for manufacturing a semiconductor device that can form a junction with a depth of 0 to 2.0 μm.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置の製造方法は、不純物をイオン注入
することにより高濃度の半導体領域を形成する半導体装
置の製造方法において、半導体基板に表面に形成した薄
い酸化膜を介して3×1015〜1.5 ×1015り
7cm2のリンイオンをイオン注入する工程と、3X1
0”ケ/C112以下の砒素イオンをイオン注入する工
程と、700〜900℃の低温かつ低濃度のリン拡散を
行いリンガラスを形成し、次いで純粋な窒素雰囲気中で
900〜1000℃の温度で熱処理を行う工程と、純粋
な窒素に微量の酸素を含むガス雰囲気中で950℃以上
の温度で熱処理し砒素不純物、リンネ純物を押込む工程
と、スチーム雰囲気中で800〜950℃の温度におい
て酸化を行う工程とを含んで構成される。
The method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device in which a highly concentrated semiconductor region is formed by ion-implanting impurities. .5 × 1015 × 7cm2 of ion implantation process of phosphorus ions, and 3 × 1
Phosphorus glass is formed by implanting arsenic ions of 0"K/C112 or less and phosphorus diffusion at a low temperature and low concentration of 700 to 900°C, and then at a temperature of 900 to 1000°C in a pure nitrogen atmosphere. A process of heat treatment, a process of heat treatment at a temperature of 950°C or higher in a gas atmosphere containing a trace amount of oxygen in pure nitrogen to push in arsenic impurities and Linnean impurities, and a process of heat treatment at a temperature of 800 to 950°C in a steam atmosphere. The method includes a step of performing oxidation.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
。第1図は、本発明の製造方法によって形成される第1
の実施例のバイポーラトランジスタの断面図である。
Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a first
FIG. 2 is a cross-sectional view of a bipolar transistor according to an embodiment of the present invention.

まず、P型半導体基板1にN+型埋込層2を形成し、次
いでエピタキシャルにてコレクタであるN型半導体領域
3を形成し、次いでバイポーラトランジスタのコレクタ
であるN型半導体領域3にP型のベース領域5を形成し
、酸化膜7を設け、エミッタ領域6及びコレクタコンタ
クト領域4を形成すべき部分の酸化膜を除去し、薄膜の
酸化膜を設け、前記薄膜の酸化膜を介して、3X10”
〜1.5 Xl016り/c112のドーズ量にてリン
イオンをイオン注入し、次に3×lOり/C11以下の
ドーズ量にて砒素イオンを注入し、エミッタ領域6およ
びコレクタコンタクト領域4を形成し、700〜800
℃の低温でかつ低温度のリン拡散を行いパッシベーショ
ン膜であるリンガラス層8を形成する。なお、この熱処
理は次工程の熱処理温度より低い温度で行う。その後、
900〜1000℃の温度において純粋な窒素雰囲気で
熱処理を行い、リンガラス層を安定化した後、950℃
以上の温度において、純粋な窒素に(15〜1.5%の
微量の酸素を含んだガス雰囲気中で、不純物を押込み、
次いで、800℃〜950℃の温度のスチーム雰囲気中
で酸化を行う。
First, an N+ type buried layer 2 is formed in a P type semiconductor substrate 1, then an N type semiconductor region 3 which is a collector is formed epitaxially, and then a P type layer is formed in the N type semiconductor region 3 which is a collector of a bipolar transistor. A base region 5 is formed, an oxide film 7 is provided, the oxide film in the portion where the emitter region 6 and the collector contact region 4 are to be formed is removed, a thin oxide film is provided, and a 3×10 ”
Phosphorus ions are implanted at a dose of ~1.5Xl016/c112, and then arsenic ions are implanted at a dose of 3x10/c11 or less to form the emitter region 6 and collector contact region 4. , 700-800
A phosphorus glass layer 8, which is a passivation film, is formed by performing phosphorus diffusion at a low temperature of .degree. Note that this heat treatment is performed at a temperature lower than the heat treatment temperature of the next step. after that,
After stabilizing the phosphorus glass layer by heat treatment in pure nitrogen atmosphere at a temperature of 900-1000℃, 950℃
At the above temperature, impurities are forced into pure nitrogen (in a gas atmosphere containing a trace amount of oxygen of 15 to 1.5%).
Oxidation is then carried out in a steam atmosphere at a temperature of 800°C to 950°C.

以上の製造方法によって結晶性の良好な1.0〜2.0
μmの深さのエミッタ領域を形成することが可能である
With the above manufacturing method, crystallinity of 1.0 to 2.0 is obtained.
It is possible to form emitter regions with a depth of μm.

すなわち、リンイオンのみのイオン注入においてエミッ
タ領域を形成しイオン注入に起因する結晶欠陥を回復す
るには、1060℃以上の温度による熱処理が必要であ
るが、この熱処理のためリンネ純物が押込まれベース領
域5とエミッタ領域6の接合の深さが2.0μm以上と
なるのであるが、本発明の様に砒素イオンのイオン注入
をリンのイオン注入と併用することによりリンイオン注
入のみの場合に比較し、より低温で結晶性を回復するこ
とが可能となり、1.0〜2.0μm程度のエミッタ領
域6とベース領域5の接合が得られるのである。
In other words, in ion implantation of only phosphorus ions, heat treatment at a temperature of 1060°C or higher is required to form an emitter region and recover crystal defects caused by ion implantation, but this heat treatment pushes the phosphorus pure ions into the base. The depth of the junction between the region 5 and the emitter region 6 is 2.0 μm or more, but by using arsenic ion implantation together with phosphorus ion implantation as in the present invention, compared to the case of only phosphorus ion implantation, , it becomes possible to recover the crystallinity at a lower temperature, and a junction between the emitter region 6 and the base region 5 of about 1.0 to 2.0 μm can be obtained.

なお、700〜800℃の低温かつ低濃度のリン拡散を
行う工程は、イオン注入後の低温アニールと、パッシベ
ーション膜として作用する緻密なリンガラス層を形成す
る工程を同時に行っており、900〜1000℃の温度
において純粋な窒素雰囲気で熱処理を行う工程は2st
epアニール法における高温アニール工程と、リンガラ
ス層を安定化する熱処理工程を同時に行っている。
Note that the process of performing low-concentration phosphorus diffusion at a low temperature of 700 to 800 degrees Celsius involves simultaneously performing low-temperature annealing after ion implantation and forming a dense phosphorus glass layer that acts as a passivation film. The process of heat treatment in a pure nitrogen atmosphere at a temperature of ℃ is the 2nd step.
The high-temperature annealing step in the EP annealing method and the heat treatment step to stabilize the phosphor glass layer are performed simultaneously.

また、不純物の押込み工程におけるガス雰囲気は、結晶
欠陥の回復を良好にするために、純粋な窒素に0.5%
〜1.5%の微量の酸素を含んだガス雰囲気が適当であ
る。
In addition, in order to improve the recovery of crystal defects, the gas atmosphere in the impurity intrusion process is made of pure nitrogen with a concentration of 0.5%.
A gas atmosphere containing a trace amount of oxygen of ~1.5% is suitable.

第2図は本発明の製造方法によって形成される第2の実
施例のツェナーダイオードの断面図である。
FIG. 2 is a sectional view of a Zener diode of a second embodiment formed by the manufacturing method of the present invention.

まず、第1の実施例と同様にP型半導体基板1にN+型
埋込層2.N型半導体領域3を形成し、次いで、ツェナ
ーダイオードの高濃度のP型半導体領域9を形成し、酸
化膜7を設け、高濃度のN型半導体領域6を形成すべき
部分の酸化膜を除去した後、第1の実施例と同様にリン
イオン注入と素イオン注入を併用してN型半導体領域6
を形成する。なお10はAf電極である。
First, as in the first embodiment, an N+ type buried layer 2. is formed on a P type semiconductor substrate 1. Form an N-type semiconductor region 3, then form a high-concentration P-type semiconductor region 9 of a Zener diode, provide an oxide film 7, and remove the oxide film in a portion where a high-concentration N-type semiconductor region 6 is to be formed. After that, similar to the first embodiment, phosphorus ion implantation and elementary ion implantation are used to form an N-type semiconductor region 6.
form. Note that 10 is an Af electrode.

この実施例では、ツェナー電圧をコントロールするため
に、浅い接合が必要な場合に有効である。
This embodiment is effective when a shallow junction is required to control the Zener voltage.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、リンイオンのイオン注入
と砒素イオンのイオン注入を併用することにより、リン
イオンまたは砒素イオンを単独でイオン注入することで
は形成不可能な結晶性の良好な1.0〜2.0μmの深
さの接合を形成可能とする効果がある。
As explained above, the present invention uses ion implantation of phosphorus ions and arsenic ions in combination to achieve good crystallinity of 1.0 to 1.0, which cannot be formed by implanting phosphorus ions or arsenic ions alone. This has the effect of making it possible to form a junction with a depth of 2.0 μm.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第1の実施例によって形成されたバイ
ポーラトランジスタの断面図、第2図は本発明の第2の
実施例により形成されたツェナダイオードの断面図であ
る。 1・・・P型半導体基板、2・・・N+型埋込み層、3
・・・N型半導体領域、4・・・コレクタコンタクト領
域、5・・・ベース領域、6・・・エミッタ領域(高濃
度のN型半導体領域)、7・・・酸化膜、8・・・リン
ガラス層、9・・・高濃度のP型半導体領域、10・・
・A/電極。
FIG. 1 is a sectional view of a bipolar transistor formed according to a first embodiment of the invention, and FIG. 2 is a sectional view of a Zener diode formed according to a second embodiment of the invention. 1...P type semiconductor substrate, 2...N+ type buried layer, 3
... N type semiconductor region, 4... Collector contact region, 5... Base region, 6... Emitter region (high concentration N type semiconductor region), 7... Oxide film, 8... Phosphorus glass layer, 9... High concentration P-type semiconductor region, 10...
・A/electrode.

Claims (1)

【特許請求の範囲】[Claims] 不純物をイオン注入することにより高濃度の半導体領域
を形成する半導体装置の製造方法において、半導体基板
に表面に形成した薄い酸化膜を介して3×10^1^5
〜1.5×10^1^6■/cm^2のリンイオンをイ
オン注入する工程と、3×10^1^5■/cm^2以
下の砒素イオンをイオン注入する工程と、700〜90
0℃の低温かつ低濃度のリン拡散を行いリンガラスを形
成し、次いで純粋な窒素雰囲気中で900〜1000℃
の温度で熱処理を行う工程と、純粋な窒素に微量の酸素
を含むガス雰囲気中で950℃以上の温度で熱処理し砒
素不純物、リン不純物を押込む工程と、スチーム雰囲気
中で800〜950℃の温度において酸化を行う工程と
を含むことを特徴とする半導体装置の製造方法。
In a method of manufacturing a semiconductor device in which a highly concentrated semiconductor region is formed by ion-implanting impurities, 3×10^1^5
A process of ion-implanting phosphorus ions of ~1.5×10^1^6■/cm^2, a process of ion-implanting arsenic ions of 3×10^1^5■/cm^2, and a process of 700 to 90
Phosphorus glass is formed by diffusing phosphorus at a low temperature and low concentration at 0°C, and then at 900-1000°C in a pure nitrogen atmosphere.
a heat treatment process at a temperature of 800 to 950℃ in a steam atmosphere, a heat treatment process at a temperature of 950℃ or higher to drive in arsenic impurities and phosphorus impurities in a gas atmosphere containing pure nitrogen and a trace amount of oxygen. 1. A method for manufacturing a semiconductor device, comprising a step of performing oxidation at a high temperature.
JP62010257A 1987-01-19 1987-01-19 Method for manufacturing semiconductor device Expired - Lifetime JPH07118472B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62010257A JPH07118472B2 (en) 1987-01-19 1987-01-19 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62010257A JPH07118472B2 (en) 1987-01-19 1987-01-19 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS63177513A true JPS63177513A (en) 1988-07-21
JPH07118472B2 JPH07118472B2 (en) 1995-12-18

Family

ID=11745267

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62010257A Expired - Lifetime JPH07118472B2 (en) 1987-01-19 1987-01-19 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH07118472B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006196550A (en) * 2005-01-11 2006-07-27 Denso Corp Method of manufacturing semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5987856A (en) * 1982-11-10 1984-05-21 Toshiba Corp Manufacture of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5987856A (en) * 1982-11-10 1984-05-21 Toshiba Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006196550A (en) * 2005-01-11 2006-07-27 Denso Corp Method of manufacturing semiconductor device

Also Published As

Publication number Publication date
JPH07118472B2 (en) 1995-12-18

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