JPH01276663A - Mis semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a high breakdown strength by a method wherein at least one well region selected among two or more well regions is also formed in the drain region of a first MIS semiconductor device. CONSTITUTION:Impurity ions are implanted into one main surface of a P-type semiconductor substrate 101 to form the deepest N-type well region 103 of a P-type channel high breakdown strength part. Then the N-type well region 104 of a lower breakdown strength part which is shallower than the formed N-type well region 103 and a P-type well region 105 are formed. Then the oxide film 107 of an isolation region is formed by a conventional LOCOS method and a gate film 108 is formed over the whole surface by, for instance, a thermal oxidation method. After that, a gate electrode 111 made of, for instance, polycrystalline silicon is formed by an ordinary method and the parts 112 and 116 which are brought into contact with the source and drain of a high breakdown strength transistor and the source and drain regions 113 and 117 of a low breakdown strength transistor are formed. With this constitution, the joint part between the offset region and the high impurity concentration diffused region of the drain of the high breakdown strength element is covered with the drain region which has the depth and impurity concentration nearly the same as those of the well region, so that a high breakdown strength can be obtained.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is applicable to MIS type semiconductor devices, especially to high voltage breakdown devices.
This invention relates to the m-structure of an s-type semiconductor device.

[Conventional technology]

As shown in FIG. 2, a conventional high-voltage MIS type semiconductor device includes an N-channel high-voltage element 209 formed on the surface of a P-type substrate 201 and a P-type impurity formed by ion implantation from the substrate surface. An N-channel low breakdown voltage element formed on the surface of the well region 207 and an N-type impurity well region 2 formed by ion implantation from the substrate surface.
There are a total of four types of M Is: a P-channel high breakdown voltage element formed on the surface of the 02 surface, and a P-channel low breakdown voltage element formed on the surface of the N-type impurity well region 208 formed by ion implantation from the substrate surface. It was made up of S-type transistors.

For high voltage elements, the diffusion region 2 to which high voltage is applied
Around 03 and 204, low impurity concentration offset regions 1 to 205 and 206 having the same electric type as the diffusion region were provided to ensure a breakdown voltage.

[Problem to be solved by the invention]

However, in the conventional Ti43M N-channel high voltage element having an offset region of about several microns in the lateral direction, the offset region is completely depleted at about several tens of volts, and the joint between the diffusion region 203 and the offset region 205 breaks. Therefore, for driving a fluorescent display tube which requires a withstand voltage of about 100 volts, an offset region of about several tens of microns is required, making it difficult to miniaturize the device.

In addition, the diffusion region 20 of the N-channel high voltage transistor
Due to the steep concentration gradient, a large number of Hola I carriers are generated at the PN junction between No. 3 and the substrate 201, which causes parasitic bipolar operation and adversely affects the on-voltage characteristics.

The present invention is intended to solve these problems, and its purpose is to provide a thin semiconductor device that can have a high breakdown voltage.

[Means to solve the problem]

The semiconductor device of the present invention includes a semiconductor substrate of one conductivity type, at least two impurity well regions having different depths and concentrations and having a conductivity type opposite to that of the substrate, and an impurity well region having a conductivity type opposite to that of the substrate formed on the surface of the substrate. A complementary MIS comprising a first MrS type semiconductor device and a second MIs type semiconductor device formed on the surface of the well region and having the same conductivity type as the substrate.
The MIS type semiconductor device is characterized in that at least one type of well region selected from the two or more types of wells is also formed in at least a drain region of the first MIS type semiconductor device.

〔Example〕

FIGS. 1(a) to 1(d) show examples of the method for manufacturing an MIS type semiconductor device of the present invention. Below, reference numeral 10 in Figure 1 specifically shows an embodiment of the present invention.
1 is a silicon substrate, for example, and for convenience of explanation, a P-type substrate will be taken as an example.

FIG. 1(a) The first step of the present invention is to first form an N-type well region, which is the deepest P-channel high breakdown voltage region, by ion implantation into the surface of a P-type semiconductor substrate. After forming a thick oxide film 102 on the surface of the substrate 101, the oxide film on the intended well region is partially etched away to expose the substrate 101, and ions of N-type impurities such as phosphorus are mainly introduced. For example, 100KEV is 7X10
``For about 1-2 minutes, impurities are selectively implanted using the oxide film as a mask.The implanted impurities are heat-treated for 50 hours at 1180°C in an oxygen atmosphere to diffuse into the substrate 101. Then, a predetermined well region 103 is formed.

FIG. 1(b) The second step of the present invention is to form an N-type well region and a P-type well region in the low breakdown voltage part, which are shallower than the N-type well region formed in the first step. It's about doing. First, as in the first step, an N-type impurity such as phosphorus is ion-implanted into a predetermined region at 100 KEV in an amount of about 8.times.10.sup.12 am.sup.-'. At this time, at least one type of well region selected from the second or more well regions is formed in the drain region of the N channel high surface (0-order) in the pressure part.
Similarly, as in the first step, a P-type impurity such as boron is ion-implanted into a predetermined region at 60 KEY at a rate of about 2 x 10 "am-". After heat treatment for 5 hours, the substrate 10
1 to form predetermined well regions 104 and 105 and a drain region 106 of an N-channel high voltage transistor. For the sake of explanation, only the drain region is formed here, but of course a source region may also be formed.

FIG. 1(c) After that, the oxide film 107 in the isolation region is removed using the conventional LOCO3 method, for example, in a water vapor atmosphere.
A gate film 108 of about 1500 OA is formed by heat treatment at 50 minutes at 50 minutes, and a gate film 108 of 250 OA is formed on the entire surface by, for example, thermal oxidation. is the diffusion layer of
These are formed by ion implantation of phosphorus and boron, respectively, before oxidation of LOGO8.

FIG. 1(d) Thereafter, a gate electrode l11 is formed using a conventional method, for example, polysilicon, 400 OA, by vapor phase growth, and then parts 112 and 116 for forming contacts 1 to the source and drain of the high voltage transistor. The source and drain regions 113 and 117 of the low breakdown voltage transistor are formed by, for example, ion implantation. After that, according to the conventional technology, 1-container edge film 114, aluminum wiring type 4
iIi! 115 etc. to obtain the structure of the present invention.

〔Effect of the invention〕

In the complementary MIS semiconductor device of the present invention manufactured as described above, the joint between the offset region of the high breakdown voltage element and the dense diffusion of the drain is covered with the drain region having the same depth and concentration as the well region. Even with the same offset length as , high withstand voltage is achieved. Furthermore, since the concentration gradient at the PN junction in the drain region becomes gentle, the ON breakdown voltage characteristics are improved.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(d) are cross-sectional views of the manufacturing process of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a main cross-sectional view of a semiconductor device according to the prior art. 101...P-type substrate 102...Oxide film 103...N-type well of high voltage P-channel transistor 104...P-type well of low-voltage N-channel transistor 105...N of low voltage P-channel transistor Type well 106...Drain region of high voltage N-channel transistor 107...LOCO3 108...Gate oxide film 109...Offset region of high voltage N-channel transistor 110...Offset region of high voltage P-channel transistor 111... Polysilicon gate electrode 112... Contact region of high voltage N-channel transistor 113... Drain and source region of low voltage P-channel transistor 114... Interlayer insulating film 115... Aluminum wiring 116...・Contact region 117 of high voltage P channel transistor...Drain and source region 201 of low voltage N channel transistor...P type substrate 202...N type well 203 of high voltage P channel transistor...High voltage N Drain region of channel transistor 204...Drain region of high voltage P-channel transistor 205...Offset region of high voltage N-channel transistor 206...Offset region of high voltage P-channel transistor 207...Low voltage N-channel transistor P-type well 208...N-type well 209 of low breakdown voltage P-channel transistor...High breakdown voltage N-channel transistor 210...Low breakdown voltage N-channel transistor 211...Low breakdown voltage P-channel transistor 212...High breakdown voltage Applicant for P-channel transistors and above Seiko Epson Co., Ltd. agent Patent attorney Masatoshi Kamiyanagi (1 other person) 1 Kai Low) Suspension FCb) 1st day (C-) 1 salary (4) 20th

Claims (2)

[Claims] (1) A semiconductor substrate of one conductivity type has at least two impurity well regions having a conductivity type opposite to that of the substrate and having different depths and concentrations, and a first impurity well region of a conductivity type opposite to that of the substrate formed on the surface of the substrate. a second MIS type semiconductor device formed on the surface of the well region and having the same conductivity type as the substrate;
In an MIS type semiconductor device including an S type semiconductor device, at least one type of well region selected from the two or more types of wells is also formed at least in a drain region of the first MIS type semiconductor device. An MIS type semiconductor device characterized by: (2) A semiconductor according to claim 1, characterized in that a shallower well region is selected from the two or more types of wells and is also formed in at least a drain region of the first MIS type semiconductor device. Device.