JPS63228662A - Manufacture of complementary type mos semiconductor device - Google Patents

Abstract

PURPOSE:To implement a high speed, by forming an N-type MOS transistor on a P-type single crystal silicon layer, and forming a P-type MOS transistor on a (110) face. CONSTITUTION:Patterns 18a and 18b are formed on the (100) face of an N-type silicon substrate. Silicon is implanted, and inversion preventing layers 19a, 19b and 19c are formed. Then the patterns 18a and 18b are removed. Patterns 21a, 21b and 21c are formed on an oxide film 20, which is formed on the substrate 17. Then with the patterns as masks, element isolating regions 20a, 20b and 20c are formed. Thereafter the patterns 21a, 21b and 21c are removed. Then, an N-type single crystal silicon layer is grown, and regions 22a and 22b are formed. Then, the region 22a is covered with a pattern 23. A P-type single crystal silicon layer 24 is formed on the region 22b. After the pattern 23 is removed, the side wall of the region 22a is exposed with a pattern 25 as a mask. After the pattern 25 is removed, an oxide film 26 is formed. After a phosphorus doped polycrystalline silicon layer 27 is deposited, a pattern 28 is formed, and gate electrodes 29a, 29b and 30 are formed. Then, P-type and N-type source and drain regions 311 and 321 and 312 and 322 are formed. Thus the operation can be made high and the integration density can be made high.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) This invention provides a complementary MOS semiconductor that increases the speed of n-channel MOS transistors, prevents latch-up, and miniaturizes elements. The present invention relates to a method for manufacturing a device.

(Prior art) As is well known, complementary MOS (hereinafter abbreviated as CMOS)
The semiconductor device has an n-channel MO on the same semiconductor substrate.
An S transistor and an n-channel MOS transistor are formed complementary to each other. In particular, recent CMOS semiconductor devices have high density.

With the increase in integration, there is a demand for the establishment of miniaturization technology.

Incidentally, conventionally, this type of CMOS semiconductor device is formed by the steps shown in FIGS. 3(a) to 3(Q), for example.

First, a thermal oxide film 2 is grown on an n-type silicon substrate 1 having a plane orientation index of (100), for example, and a resist pattern 3 is formed on the thermal oxide gI2 by photolithography, with a region where a well is to be formed removed.

Using the resist pattern 3 as a mask, apply boron to, for example, an acceleration voltage of 100 eV and a dose of 18.5×1012c.
A boron ion implantation layer 4 is formed on the substrate 1 by ion implantation under the conditions of m4 (as shown in FIG. 3(a)). Subsequently, the resist pattern 3 is removed and the ion implantation layer 4 is
A p-type wool region 5 is formed by heat treatment and diffusion at a temperature of 200° C. to an extent of 3011i. Next, the above thermal oxidation I
I! After etching and removing 2, thermal oxidation is performed again to form a thermal oxide film 196, and silicon nitride 17 is formed on this thermal oxide film 6 (as shown in FIG. y(b)). next,
The silicon nitride layer [17] where the field oxide film is to be formed is selectively removed by photoetching to form silicon nitride film patterns 7a to 7c (FIG. 1(C)).
(Illustrated).

Subsequently, a resist pattern 8 covering areas other than the p-well region 5 is formed by photolithography, and using this resist pattern 8 and the silicon nitride film pattern 7b as masks, for example, boron is heated at an acceleration voltage of 40 KeV and a dose of 8X.
After ion implantation under the conditions of 10' 3 cm, thermal diffusion is performed to form p+ type impurity layers 9, 9 for preventing field reversal.
(as shown in FIG. 4(d)). Subsequently, the resist pattern 8 is removed, and a resist pattern 10 covering the p-type well region 5 is formed again by photolithography.

Using this resist pattern 10 and the silicon nitride film patterns 7a and 7c as masks, for example, phosphorus is applied at an acceleration voltage of 100 KeV and a dose of 5XIO12 cm.
After ion implantation under the conditions of 2, thermal diffusion is performed to form an n+ type impurity layer 11.11 for preventing field inversion (as shown in FIG. 3(e)).

Next, the resist pattern 10 is removed, and selective oxidation is performed in a high temperature wet atmosphere using the silicon nitride film patterns 7a to 7C as oxidation-resistant masks to form field oxidation g112.12.12 (Fig. 3). <r> As shown).

Next, a thermal oxide film that will become a gate oxide film is grown on the device region separated by the field oxidation [912, 12, 12], a polycrystalline silicon film is deposited on this thermal oxide film, and then a polycrystalline silicon film is deposited on the thermal oxide film. Diffuse phosphorus into the silicon film. Subsequently, the polycrystalline silicon film is patterned to form a gate electrode 13.
1, 132, and these gate electrodes 13. ,
Using 132 as a mask, the thermal oxide film is etched to form gate oxides 1141 and 142. next,
Boron ions are implanted into the surface region of the silicon substrate 1 using the gate electrode tf1131 as a mask, and arsenic ions are implanted into the surface region of the p-type well region wt5 using the gate electrode 132 as a mask.

P+ type source and drain regions 151° and 161 and n+ type source and drain regions 152 and 162 are formed (as shown in FIG. 3(g)). Thereafter, a CVD-8i02 film is formed on the entire surface using a known technique (not shown), a contact hole is opened, and then aluminum is vapor deposited and patterned to form wiring, and a p-channel MOS is formed.
Transistor Ql and n-channel MOS transistor Q
A CMOS semiconductor device consisting of 2 is formed.

However, the conventional manufacturing method described above has the following drawbacks. First, each channel type MOS transistor is formed with a plane orientation index of (100), and this is because the reliability and current drive ability of the n channel type MOS transistor Q2 are taken into consideration. However, if the p-channel MOS transistor Q1 is formed on the (100) plane, the current driving ability will be significantly reduced, resulting in a reduction in operating speed. This is dealt with by increasing the size of the p-channel MoS transistor Q1. but,
Setting the size of MOS transistor Q1 large causes a new problem of increased parasitic capacitance. Therefore,
In order to solve this problem, it is conceivable to form the p-channel type MOS transistor Q1 on the (110) plane where the current driving ability can be maximized. To achieve this,
A CMOS semiconductor device with a three-dimensional structure in which a trench is dug perpendicularly into a silicon substrate with a (1,OO) plane, a (110) plane is formed on the sidewall of this groove, and an n-channel MOS transistor is arranged on this (110) plane. was held at the 1986 VLSI Symposium (SUBMICRON 3D 5URFACE-O
RI ENTAT 10N-OPT IM I ZED
CMOSTECHNOLOGY) T-Rete has been announced.

However, with the manufacturing method presented at this symposium,
To form a (110) plane, the plane orientation index is (100)
It is necessary to form grooves by etching the silicon substrate by RIE, which has the disadvantage that a damaged layer is formed on the substrate surface and the device characteristics are deteriorated.

In addition, in a CMOS semiconductor device with a conventional structure, as shown in Fig. 3 (Q
) As shown in FIG. 162), p-type well region 5, and n-type silicon substrate 1, an anomalous NPN transistor is formed, and a latch-up phenomenon occurs. This latch-up phenomenon is determined by the resistance of the silicon substrate 1 and the p-type well region 5 and the probability of arrival of minority carriers.

Since the arrival probability of the minority carriers is determined by the distance between the n-channel type device regions, the latch-up phenomenon becomes more likely to occur when the device is miniaturized, leading to deterioration of device characteristics. This makes it difficult to achieve high integration.

Furthermore, as shown in FIG. 3(b), when forming the p-type well region 5, the diffusion layer extends in the depth direction (direction perpendicular to the surface of the substrate 1) and in the lateral direction (direction perpendicular to the surface of the substrate 1). (for example, if it extends by 10 μm in the depth direction, it also extends by 7 to 8 μm in the lateral direction), which becomes an obstacle to miniaturization and causes a decrease in the degree of integration.

Further, as shown in FIGS. 3(d) and 3(e), since ions are implanted to prevent field reversal between n-type and p-type, there is a drawback that the number of photolithography steps is large and productivity is poor.

(Problems to be Solved by the Invention) As described above, in the conventional manufacturing method of a CMOS semiconductor device, the operating speed of the n-channel MOS transistor decreases, latch-up is likely to occur, and impurities are introduced during the formation of the well region. It has the disadvantage that it is difficult to achieve high integration because it is also diffused in the lateral direction. In addition, there are many photo-etching steps, and productivity is low.

This invention was made in view of the above circumstances,
The purpose is to provide a method for manufacturing a complementary MOS semiconductor device that can increase the speed of n-channel MOS transistors, prevent latch-up, miniaturize elements, and improve productivity.

[Structure of the invention] (Means and effects for solving the problem) That is, in order to achieve the above object, in this invention, an insulating film is formed on an n-type semiconductor substrate, and this insulating film is After selectively removing to form an element isolation region and exposing the surface of the semiconductor substrate, a plane orientation index of (100) is formed on the exposed surface of the semiconductor substrate separated by the element isolation region.
An n-type single crystal semiconductor layer is formed, and at least one of these single crystal semiconductor layers is doped with an impurity that forms a p-type to form an n-type and a p-type in at least two adjacent device regions.
Form a single crystal silicon layer of the mold. Then, an n-channel MoS transistor is formed in the p-type single-crystal silicon layer, and a part of the element isolation region in contact with the n-type single-crystal semiconductor layer is etched to remove the surface of the semiconductor substrate and the single-crystal silicon layer. Plane orientation index (1
The sidewall of 10) is exposed to form an n-channel MOS transistor having a channel along this sidewall.

By doing this, the n-channel type MOS transistor is formed on the (110) plane, so this MO
The mobility of the S transistor is increased, and the operating speed can be increased. Furthermore, since the n-type element region and the n-type element region are separated by the element isolation region, formation of a parasitic bipolar transistor can be prevented and latch-up can be reliably prevented. Moreover, if the selective epitaxial growth method is used when forming the element region, bird's beaks do not occur unlike when the LOCO8 method is used, and the element isolation region can be miniaturized. Thereby, it is possible to suppress reduction of the element region with respect to the design dimension, and it is possible to form a CMOS semiconductor device with high integration density.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. Figures 1 (a) to (i) sequentially show the manufacturing process. First, as shown in Figure 1 (a), the plane orientation index (100
) Photoresist patterns 18a and 18b are formed on the n-type silicon substrate 17 in a region where an element isolation region is to be formed, and phosphorus is applied at an acceleration voltage of 40 KeV and a dose of 4X.
Field inversion prevention layers 19a, 19b, and 19c are formed by ion implantation under the condition of 1013 Cm''.

Subsequently, the photoresist patterns t8a and 18b are formed.
A CVD oxide film 20 having a thickness of approximately 1 μm is formed on the entire surface of the silicon substrate 17 as shown in FIG.

Then, a photoresist is applied on the CVD oxide film 20, and photolithography is performed to create a CVDI area corresponding to the area where the element isolation area is to be formed. A resist pattern 21 is formed on the oxide film 20.
a.

21b and 21c are formed. Next, using the photoresist patterns 2ja, 21b, 21c as a mask, the cvoaa film 20 is selectively removed by reactive ion etching (RIE) to form device isolation regions (field oxidation II) 20a, 20b, 2.
Form 0c. The above photoresist pattern 21a.

When 21b and 21c are removed, the result is as shown in Figure (C).

Next, element isolation regions bll, 20a are formed on the exposed silicon substrate 17 by selective epitaxial growth.

An n-type single crystal silicon layer is grown to the same thickness as 20b and 20c. As a result, the element isolation regions 20a and 2
0b and between 20b and 200, respectively.
The device region 22a is made of a type of single crystal silicon layer.

22b is formed, as shown in Figure (d).

Subsequently, <8) As shown in the figure, the element region 22a is covered with a resist pattern 23, and an impurity forming a p-type, such as poron, is applied to the element region 22b at an accelerating voltage of 100 KeV.
A p-type single crystal silicon layer (
element area) 24.

Next, after removing the resist pattern 23, a layer of n-type single-crystal silicon J1 is formed on the element isolation regions 20b and 20c, on the p-type single-crystal silicon layer (element region) 24, and on the p-type single-crystal silicon layer (element region) 24.
22a (element region) and a portion of the element isolation region 20a are covered with a resist pattern 25, and using this resist pattern 25 as a mask, the element isolation region 20a is covered with a resist pattern 25.
The CVDII film is selectively removed by wet etching to expose the surface of the silicon substrate 11. As a result, the side walls of the element region 22a made of the n-type single crystal silicon layer are exposed as shown in FIG. This sidewall is the plane orientation index (110).

・Next, after removing the resist pattern 25, a gate oxide film 126 (film thickness 200 mm) is formed on the entire surface, and on this gate oxide film 26, phosphorus-doped polycrystalline silicon @ 27 (film thickness 400 mm thickness) is formed to become the gate electrode. people) are deposited and formed.

Thereafter, a resist pattern 28 is formed on the phosphorus-doped polycrystalline silicon layer 27 so as to cover the area where the gate electrode of the n-channel MOS transistor is to be formed ((g)
figure).

Next, using the resist pattern 28 as a mask, RI
The phosphorus-doped polycrystalline silicon layer 27 is etched using the E method to form a gate electrode 29a of an n-channel MOS transistor as shown in the figure (h).

29b, and a gate electrode 30 of an n-channel MoS transistor.

Next, the unnecessary gate electrode 29a remaining on the side wall of the element isolation region 20a- is removed, and the unnecessary gate oxide film 26 is removed by etching, and impurities forming p-type and n-type are ionized, respectively. The source and drain regions 31. of the n-channel MOS transistor are implanted.
, 32. and forming source and drain regions 312 and 322 of an n-channel MOS transistor, (i)
A CMO consisting of a p-channel type MoS transistor Q1 and an n-channel type MOS transistor Q2 as shown in the figure.
Complete the S semiconductor device.

In a CMOS semiconductor device formed using such a manufacturing method, as shown in Figure (1), the channel of the p-channel MOS transistor Q1 is formed in the (110) plane, so the mobility of this MOS transistor is −
This increases the operating speed. On the other hand, the channel of the n-channel MOS transistor Q2 has a surface orientation index (
100) plane, reliability and current drive capability are not reduced. Further, since the n-type element region and the n-type element region are separated by the element isolation region 1120b, formation of a parasitic bipolar transistor can be prevented and latch-up can be reliably prevented. Moreover, the element regions 22a, 22
Since the selective epitaxial growth method is used to form the region b, there is no occurrence of bird's beak as in the case of using the LOCO8 method, and the device isolation regions 20a to 20c can be miniaturized, and the design values of the device regions 22a and 22b can be reduced. Therefore, it is possible to suppress the reduction in the dimensions of the CMOS semiconductor device and form a CMOS semiconductor device with high integration density.

In addition, in the above embodiment, the field inversion prevention layers 19a to
Although the layer 19c is formed before the formation of the CVD oxide film wA20 which becomes the element isolation region, it may be formed after the formation of this oxide film 20. Further, if a low resistance substrate (eg, impurity concentration of 11×101aC' or more) is used as the silicon substrate 17, it is not necessary to form the field inversion prevention layers 19a to 19c.

FIGS. 2(a) to 2(C) show other embodiments of the present invention. In FIG. 2, the same components as in FIG. 1 are given the same reference numerals, and a high concentration of p
A + type single crystal silicon layer 33 is formed. That is, by the selective epitaxial growth method shown in FIG. 1(d), the n-type single crystal silicon 2 layer 22a has the same thickness as the element isolation regions 20a to 20c.

The process is similar until forming 22b. Next, the element region 22a is covered with a resist pattern 34, and an impurity that forms a p-type, such as boron, is ion-implanted into the element region 22b at an acceleration voltage of 100 KeV and a dose of 5 x 1013 cm4, and then heat treatment is performed at a high temperature. Figure la) converting into a monocrystalline silicon region 24 of the type.

Subsequently, ion implantation is performed again into the p-type single crystal silicon region 24 to form a single crystal silicon region! At the bottom of 124,
An impurity layer 33 having a higher concentration than at least this p-type wheel crystal silicon region 24 is formed (FIG. (b)).

Thereafter, in the same steps as in FIGS. 1(f) to (i), the n-channel type and n-channel type MOS transistors Q1 are
, Q2 are formed to complete a CMOS semiconductor device as shown in FIG.

According to such a manufacturing method, a p+ type impurity region 33 is formed between the silicon substrate 17 and the p type wheel crystal silicon layer 24.
Therefore, leakage current between the silicon substrate 17 and the source 312 or drain 322H of the n-channel MOS transistor Q2 can be reduced. This is because a depletion layer is likely to be formed when the impurity concentration between the silicon substrate 17 and the source 312 or drain 322 of the n-channel MOS transistor Q2 is low, but this can be alleviated by the high concentration impurity region 33.

Note that in the embodiment shown in FIG. 2 above, the element isolation region wt
Single crystal silicon layer 22a with the same thickness as 20a to 20c
, 22b are formed by selective epitaxial growth, and impurity ions are implanted to form the single crystal silicon layer 22b.
After converting into a p-type, impurity ions are implanted again.
The + type impurity layer 33 was formed. First, a single crystal silicon layer was formed thinly by epitaxial growth, and impurity ions were implanted to form the p + type impurity layer 33. After that, selective epitaxial growth was performed again to form the element isolation region. Single crystal silicon m22 to the same thickness as 20a~20C
b may be formed and converted to p-type.

[Effects of the Invention] As explained above, according to the present invention, p-channel type M
A method for manufacturing a complementary MOS semiconductor device can be obtained that can increase the speed of an OS transistor, prevent latch-up, miniaturize elements, and improve productivity.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining a method of manufacturing a complementary MOS semiconductor device according to one embodiment of the present invention, FIG. 2 is a diagram for explaining another embodiment of the present invention, and FIG.
The figure is a diagram for explaining a conventional method for manufacturing a complementary MOS semiconductor device. 17... Semiconductor substrate, 19a, 19b, 19
c... Impurity layer for preventing field inversion, 20...
Insulating film, 20a. 20b, 20c... element isolation region, 22a,
22b...single crystal silicon layer (single crystal semiconductor layer), Q
l...p channel type MOS transistor, Q2...
p-channel type MOS transistor, 33... impurity region. Applicant's agent Patent attorney Kazuichi Suzue Takehiko-l-N 1), Ω〜ノ

To N- ^ Q “0 Figure 1 Figure 2 ^ , 0m

Claims (5)

[Claims] (1) A step of forming an insulating film on a semiconductor substrate of a first conductivity type, a step of selectively removing the insulating film to form an element isolation region and exposing the surface of the semiconductor substrate, forming a single crystal semiconductor layer of a first conductivity type on an exposed surface of a substrate; and doping at least one of these single crystal semiconductor layers with an impurity forming a second conductivity type to form at least two adjacent device regions. forming a MOS transistor having a first conductivity type channel in the second conductivity type single crystal semiconductor layer; etching a part of the element isolation region in contact with the first conductivity type single crystal semiconductor layer to expose the surface of the semiconductor substrate and the sidewall of the first conductivity type single crystal semiconductor layer; 1. A method for manufacturing a complementary MOS semiconductor device, comprising the step of forming a MOS transistor having a channel of two conductivity types. (2) The method for manufacturing a complementary MOS semiconductor device according to claim 1, wherein the single crystal semiconductor layer is formed by a selective epitaxial growth method. (3) Complementary to claim 1, characterized in that an impurity layer for preventing field inversion is formed on the semiconductor substrate under the element isolation region with a first conductivity type having a higher impurity concentration than the substrate. A method for manufacturing a type MOS semiconductor device. (4) A second conductivity type impurity region having a higher impurity concentration than the second conductivity type single crystal semiconductor layer is formed between the second conductivity type single crystal semiconductor layer and the semiconductor substrate. A method for manufacturing a complementary MOS semiconductor device according to claim 1. (5) The first conductivity type is n type, the second conductivity type is p type, the plane orientation of the single crystal semiconductor layer is (100), and the plane orientation index of the sidewall of the first conductivity type single crystal semiconductor layer. 2. The method of manufacturing a complementary MOS semiconductor device according to claim 1, wherein: is (110).