JPH0445543A - Manufacture method of semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to finish an ion implantation process of impurities only at one time by selectively ionimplanting second conductivity type-impurities based on a slanting rotation ion implantation process, keeping a side wall oxide film as it remains. CONSTITUTION:N type impurities are selectively ion-implanted based on a slanting rotation ion implantation process, keeping a side wall oxide film as it remains. On a main surface of a P type silicon substrate 11, which is selectively cut in and exposed by the application of this ion implantation operation or a main surface which is cut into, is formed each N<+> region selectively as a source and a drain. On a side wall main surface of a P type silicon substrate. which is not cut into yet, is selectively formed each N<-> region 13 required for LDD structure by impurity ions which permeate a side wall oxide film 16 formed on the aforesaid side wall.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device, and more specifically, to a method of manufacturing a semiconductor device, and more specifically, to a method of manufacturing a semiconductor device.
The present invention relates to a method of manufacturing a transistor having a Dair+) I9 structure.

[Prior Art] A schematic structure of a conventional LDD structure type transistor of this type is shown in FIG. 3, and its main manufacturing steps are shown in FIGS. 4(a) to 4(d).

That is, in the device configuration of the conventional LDD structure type transistor shown in FIG. 3, reference numeral 21 indicates a P-type silicon substrate, and 22 is selectively formed on the main surface of the P-type silicon substrate 21 to serve as a source. The N''' regions 23, which become active regions as drains, are selectively shallow (formed to form an LDD structure) inside each of the N''' regions 2.
24 is a gate oxide film formed on the P-type silicon substrate 21 between the N- regions 23, 25 is a gate polysilicon layer provided on the gate oxide film 24, and 26 is the gate This is a spacer oxide film formed on the sides of polysilicon layer 25.

In this conventional LDD structure type transistor, an N- region 23 is formed inside each N-region 2 to suppress electric field concentration near the drain, thereby suppressing the generation of hot electrons and achieving high performance with a large current drive capability. This allows us to obtain a transistor structure that is ideal.

Therefore, as shown in FIGS. 4(a) to 4(d), manufacturing of this conventional LDD structure type transistor is as follows.
First, after patterning the gate polysilicon layer 25 including the gate oxide film 24 on the main surface of the P-type silicon substrate 21 (FIG. 2(a)), using this as a mask, N
By selectively ion-implanting type impurities and annealing, N- regions 23 are formed in each region (
After depositing an oxide film 26a thereon (FIG. 2C), a desired spacer oxide film 26 is formed by etching back (FIG. 2D).

Thereafter, as shown in FIG. 3, N-type impurities are selectively ion-implanted using the spacer oxide film 26 as a mask, and annealing is performed to form each of the N-type impurities.
N2 regions 22 are formed in each region 23, and in this way, the desired device configuration of a DD structure type transistor is obtained.

[Problem to be solved by the invention 1 However, the conventional LD manufactured as described above
In the case of a D-structure transistor, during manufacturing, after patterning the gate polysilicon, there are two impurity ion implantation steps, and in addition, a spacer oxide film deposition and etching removal (etchback) step. Each of them requires a large number of manufacturing steps and is too complicated.
There is a disadvantage that variations in each process eventually induce variations in the characteristics of the transistors themselves.

This invention was made to solve these conventional problems, and its purpose is to complete the two-step impurity ion implantation process in one time, and to reduce the spacer oxide film deposition process. By eliminating the process, we were able to simplify the number of manufacturing steps. A method for manufacturing this type of semiconductor device.

This S provides a method for manufacturing an LDD structure type transistor.

[Means for Solving the Problems] In order to achieve the above-mentioned object, a method for manufacturing a semiconductor device according to the present invention includes a method for manufacturing a semiconductor device according to the present invention. , a gate oxide film, and a gate polysilicon layer are sequentially formed, and then the main surface of the silicon substrate is simultaneously selected to a required depth when patterning the gate polysilicon layer of the gate polysilicon layer including the gate oxide film. forming a sidewall oxide film on the gate polysilicon layer, the gate oxide film, and each side surface portion of the silicon substrate into which the silicon substrate has been dug; By selectively ion-implanting impurities of the second conductivity type using an oblique rotational ion implantation method, a second conductivity type impurity, which will become an active region, is implanted onto the selectively dug main surface of the silicon substrate. While forming a high concentration impurity region, at the same time, impurity ions passing through the side wall oxide film form a low concentration impurity of a second conductivity type on the main surface of the side wall portion of the silicon substrate that is not dug down for forming the LDD structure. The method is characterized in that it includes a step of forming a region.

[For production]

Therefore, in the method of this invention, the side wall oxide film is left intact.
Then, by selectively ion-implanting impurities of the second conductivity type using the oblique rotational ion implantation method, the high concentration impurity region on the main surface of the silicon substrate that has been selectively dug is replaced with the silicon that has not been dug. Low-concentration impurity regions can be formed on the main surface of the side wall of the substrate at the same time, making it possible to perform the impurity ion implantation process only once. Since the dimensions of the region can be set, variations in the dimensions of the low concentration impurity region can be reduced.

〔Example〕

Hereinafter, as a method for manufacturing a semiconductor device according to the present invention, one embodiment of a method for manufacturing an LDD structure type transistor will be described in detail with reference to FIGS. 1 and 2.

FIG. 1 is a cross-sectional view schematically showing the general structure of a DD structure type transistor to which an embodiment of the method of the present invention is applied, and FIG. FIG. 3 is a cross-sectional view showing the manufacturing process in sequence.

Also in the device configuration of the LDD structure type transistor in the example shown in FIG. Highly concentrated impurity regions of a second conductivity type, which are formed on each main surface of the substrate 11 by selectively digging a portion thereof, and which serve as active regions as a source and a drain;
Here, the N'' region 13 is selectively formed shallowly on the main surface of the side wall portion of the P-type silicon substrate 11 that is not recessed, corresponding to the inner side of each N'' region 22. The high concentration impurity region of the second conductivity type constituting the structure is an N− region in this case, and ]4 is the N− region of each N− region.
- A gate oxide film formed on the main surface of the P-type silicon substrate 11 that is not dug down corresponding to between the regions 13; 15 is a gate polysilicon film as a gate electrode provided on the gate oxide film 14; Layer 6 is the gate polysilicon layer 15. This is a sidewall oxide film formed to cover the gate oxide film 14 and the sidewall surface of each N- region 13.

Therefore, in the LDD structure type transistor according to this embodiment as well, the N-
The regions 13 are formed, and by suppressing electric field concentration in the vicinity of the drain by these N- regions 13, generation of hot electrons can be suppressed and a high-performance transistor structure with a large current drive capability can be constructed.

As shown in FIGS. 2 fa) to 2 fc), the manufacturing of the LDD structure type transistor according to the structure of this embodiment starts with forming a gate oxide film on the main surface of the P-type silicon substrate 11. 14. and gate polysilicon layer 1
5 are sequentially formed, and then when patterning the gate polysilicon using a resist pattern as an etching prevention film as a mask, that is, when patterning the gate polysilicon layer 15 including these gate oxide films 14, the gate polysilicon layer 15 is patterned. Silicon layer 15. In accordance with the selective etching of the gate oxide film 14, at the same time, the main surface of the P-type silicon substrate 11 is also over-etched to selectively dig only the required depth d, and the resist used as a mask is etched. Remove the pattern ((a)l in the same figure).

Then, by thermally oxidizing these surfaces,
After forming the oxide film 16a on the entire surface (FIG. 2(b)), the oxide film 16a is etched back by anisotropic etching to remove the corresponding side surface portions, that is, the gate polysilicon layer 15. Then, the gate oxide film 14 and each side surface portion of the P-type silicon substrate 11 corresponding to the dug depth d are etched and removed so that the side wall oxide film 16 remains (see (C) in the same figure). ).

Thereafter, as shown in FIG. 1, while leaving the sidewall oxide film 16, N is implanted using an oblique rotational ion implantation method.
Type impurities are selectively ion-implanted and annealed, and as a result of this ion-implantation operation, the main surface of the P-type silicon substrate 11, which is selectively dug and exposed, is
In other words, each N0 region 12 as a source and drain is selectively formed on the dug main surface, and the N0 regions 12 are selectively formed on the main surface of the side wall portion of the P-type silicon substrate 11 that is not dug down. In this case, each N- region 13 for the LDD structure is selectively formed shallowly by impurity ions that pass through the sidewall oxide film 16 formed on the sidewall. The desired device configuration of the LDD structure type transistor is obtained.

Therefore, in the configuration of the LDD structure type transistor manufactured by the method of this embodiment, when compared with the conventional configuration described above, a similar device can be configured by only forming each N1 region 12 in the depth direction. The same effect and effect can be obtained as compared to the conventional manufacturing process.
In addition, in the case of the conventional method, the dimensional accuracy of each N' region 2 is affected by dimensional variations during the formation of the spacer oxide film 26, that is, variations in film thickness after deposition. However, in this embodiment method, the variation in dimensions in each N region 2 is affected by gate polysilicon patterning. Since this is only due to variations in the amount of subsequent etching of the silicon substrate, the variations can be reduced.

Incidentally, in the above embodiment method, the case where the present invention is applied to an N-channel transistor was described, but P
Of course, the present invention can be applied to channel transistors.

[Effects of the Invention] As detailed above, according to the method of the present invention, a gate oxide film and a gate polysilicon layer are sequentially formed on the main surface of a first conductivity type silicon substrate, and the gate When forming a gate polysilicon pattern for a gate polysilicon layer containing an oxide film, at the same time, the main surface of the silicon substrate is selectively etched to a required depth and overetched. A sidewall oxide film is formed on the film and each side surface of the dug silicon substrate, and with the sidewall oxide film left in place, a second conductivity type is implanted using an oblique rotational ion implantation method. By selectively implanting impurities, a high concentration impurity region of the second conductivity type, which will become an active region, is formed on the selectively dug main surface of the silicon substrate, and at the same time, a high concentration impurity region of the second conductivity type is formed on the main surface of the silicon substrate, which has been selectively dug. On the main surface of the side wall of the substrate, L is formed due to impurity ions passing through the side wall oxide film.
Since the second conductivity type low concentration impurity region for the DD structure is formed, the two impurity ion implantation steps required to form each impurity region in the conventional method are reduced to one. In addition, since the dimensions of the low-concentration impurity region are set by selectively digging into the silicon substrate, dimensional variations in the low-concentration impurity region can be reduced. It has excellent features such as being able to reduce it effectively, requiring little practice that affects transistor characteristics, and being relatively simple and easy to implement in terms of structure and means.

[Brief explanation of the drawing]

FIG. 1 is a sectional view schematically showing the general structure of a DD structure type transistor to which an embodiment of the method of the present invention is applied, and FIG.
Figures (a) to c) are cross-sectional views sequentially showing the main manufacturing steps of the above device, and Fig. 3 is a cross-sectional view schematically showing the general configuration of a conventional LDD structure type transistor. , and FIGS. 4(a) to 4(d) are sectional views sequentially showing the main manufacturing steps of the same device. 11... P-type silicon substrate, 12... N8 region, 13... N- region, 14... gate oxide film, 15... gate polysilicon layer, 16...・Side wall oxide film. Agent Masu Oiwa 1st evil c11 3rd cause 2nd evil

Claims (1)

[Claims] In a manufacturing process of a transistor having an LDD structure, a gate oxide film and a gate polysilicon layer are sequentially formed on the main surface of a silicon substrate of a first conductivity type, and then the gate oxide film is At the time of gate polysilicon patterning of the gate polysilicon layer containing the gate polysilicon layer, a step of simultaneously selectively digging and over-etching the main surface of the silicon substrate to a required depth, and etching the gate polysilicon layer, the gate oxide film, and A process of forming a sidewall oxide film on each side of the dug silicon substrate, and selectively ionizing impurities of the second conductivity type by an oblique rotational ion implantation method while leaving the sidewall oxide film. Inject it,
On the main surface of the selectively dug silicon substrate,
While forming a high concentration impurity region of the second conductivity type to become an active region, at the same time, an LDD structure is formed on the main surface of the side wall portion of the silicon substrate which is not dug down by impurity ions that pass through the side wall oxide film. forming a second conductivity type low concentration impurity region.