JP2804526B2 - Method for manufacturing MOS type semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a MOS type FET.
And a method for producing the same.

[Conventional technology]

2. Description of the Related Art Conventionally, a method of manufacturing this type of MOS FET will be described with reference to FIG. FIG. 2 shows a sectional view of the process.

First, a thick field oxide film 2 is selectively formed on the surface of a P-type silicon substrate 1 by the LOCOS method to perform element isolation. Next, a thin gate oxide film 3 is formed on a predetermined portion of the active region of the substrate 1. Furthermore, to form a polysilicon layer on the entire surface and to provide conductivity to the polysilicon layer
Doping with phosphorus (P) using PoCl ₃ as a diffusion source. Thus, the gate electrode 4 is formed by anisotropically etching the conductive polysilicon layer using the photolithography technique. Thereafter, the gate electrode 4 is used as a mask to ion-implant phosphorus to form a shallow N ⁻ -type low-concentration impurity region 5 over the entire region where the source / drain is to be formed on the surface of the substrate 1 (FIG. 2A).

Next, an SiO ₂ film 6 is deposited on the entire surface by a CVD method (FIG. 2B).

After that, the entire surface of the SiO ₂ film 6 is anisotropically etched by using the RIE method to form a sidewall 7 on a side surface of the gate electrode 4. Then, arsenic (As) is ion-implanted using the side wall 7 and the gate electrode 4 as a mask, and an N ⁺ -type high-concentration impurity region 8 is formed in a portion slightly separated from the gate electrode 4 in the source / drain formation planned region. It was formed deep to complete the NMOS FET (FIG. 2c).

[Problems to be solved by the invention]

However, in the above-described conventional method, it is difficult to detect the end point during the entire surface etching for forming the sidewalls 7, and the remaining elements may be left behind, or the field oxide film 2 or the substrate 1 may be etched. Has a large effect, which causes a problem such as generation of a leak current and deterioration of device characteristics.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a high-yield semiconductor device which is excellent in reliability and eliminates the influence of a sidewall element on an underlying element in view of the above-described problems.

[Means for solving the problem]

In order to achieve the above object, the present invention provides a step of sequentially forming a gate oxide film, a gate electrode material layer and a resist film on an active region of a semiconductor substrate, and a step of patterning the resist film into a predetermined shape; Using the resist film as a mask, the gate electrode material layer and the gate oxide film are etched under conditions such that only the periphery of the resist film is etched, and the opening and the gate electrode sandwiched by the opening are etched. Forming, a step of forming a silicon layer in the opening, a step of etching and removing the gate electrode material except for the gate electrode, and performing ion implantation using the gate electrode and the silicon layer as a mask, Forming a high-concentration impurity layer region, etching the silicon layer, and masking the gate electrode. To perform ion implantation, and a step of forming low concentration impurity layer regions.

[Action]

In the present invention, the formation of the gate electrode and the opening and the etching of the gate electrode material layer other than the gate electrode are performed using the same resist pattern as a mask, and the removal and removal of the gate electrode material layer for forming the high / low concentration impurity regions are performed. Since the removal of the silicon layer is performed using the etching selectivity, there is no need to perform the entire surface etching process for forming the sidewall as in the conventional method, so that the influence of the etching on the underlying elements such as the field oxide film and the substrate is suppressed. As a result, deterioration of device characteristics is prevented. In addition, since the device can be manufactured in one photolithography process, mask alignment errors are minimized, and workability is improved.

〔Example〕

An embodiment according to the method of the present invention will be described below with reference to FIG. FIG. 1 shows a sectional view of the process.

First, an N-type well layer 11a is formed on a predetermined portion of the (100) plane of the P-type silicon substrate 11. Next, a thick field oxide film 12 is selectively grown on the substrate 11 by the LOCOS method to perform element isolation. Then, over the entire surface, 200
A thick gate oxide film 13 and a 3000-thick molybdenum film 14 are sequentially laminated. Next, after a resist film 15 is applied on the molybdenum film 14, the resist film 15 is formed into a predetermined pattern by photolithography. Subsequently, using a peripheral etching method, the molybdenum film 14 and the gate oxide film 13 around the patterned resist film 15 are removed.
Is selectively removed by etching to simultaneously form an opening 14a and a gate electrode 16 having the opening 14a around the opening 14a. Note that the peripheral etching method in this case refers to a reactive ion etching method in which a chlorine gas and an oxygen gas are etched, and the occupation rate of the oxygen gas. Must be in the range of 60-70%. Thereafter, the molybdenum film 14 not covered with the resist film 15 is etched away by a thickness of 1500 ° by the same reactive ion etching method using an etchant having an oxygen gas occupancy of 50% or less (FIG. 1a).

Next, after the entire surface of the resist film 15 is removed, a Si layer 17 is epitaxially grown to a thickness of 700 in the opening 14a (FIG. 1B).

Thereafter, the gate electrode 16 is formed under the condition that the selectivity with Si is large.
The molybdenum film 14 containing is etched away by a thickness of 1500 mm. Furthermore, the PM of the substrate 11 is
OS-FET region, i.e. covered with a resist film abbreviated shown on N-type well layers 11a, the gate electrode 16 and the Si layer 17 as a mask, a dose of 8 × 10 ¹⁵ inos / cm ² of arsenic ⁽⁷⁵ As ⁺⁾ 50 KeV
Ion implantation with the acceleration energy of
17, N ⁺ -type high-concentration impurity regions 18 are formed deep on both sides. Subsequently, after removing the resist film, the NMOS FE of the substrate 11 is removed.
The region where T is to be formed is covered with a resist film (not shown), and the dose is 4 × 10 ^{15 using the} gate electrode 16 and the Si layer 17 as a mask.
Ion implantation of ions / cm ² boron fluoride ( ⁴⁹ BF ₂ ⁺ ) is performed at an acceleration energy of 25 KeV.
7P ⁺ type high concentration impurity regions 19 are formed deeply on both sides (FIG. 1c).

Thereafter, the resist film is removed, and the Si layer 17 is removed by etching under the condition that the selectivity with molybdenum is large.
Then, the N-type well layer 11a is again covered with a resist film (not shown), and a dose of 5 × 10
¹³ ions / cm ² of phosphorus ( ³¹ P ⁺ ) is ion-implanted at an acceleration energy of 30 KeV, and N ^{− is} implanted on both sides of the gate electrode 16 on the surface of the substrate 11.
The low-concentration impurity region 20 is formed shallow. Similarly, after removing the resist film, the region where the NMOS type FET is to be formed on the substrate 11 is covered with a resist film (not shown), and the gate electrode 16 is used as a mask to form a boron having a dose of 5 × 10 ¹³ ions / cm ² . ( ¹¹ B ⁺ ) is ion-implanted at an acceleration energy of 20 KeV,
P ⁻ -type low-concentration impurity regions 21 are formed shallowly on both sides of the gate electrode 16 on the surface of the mold well layer 11a. Thus, a CMOS type FET
Is completed (FIG. 1d).

In this embodiment, molybdenum is used as the gate electrode material. Alternatively, molybdenum silicide or polybutene polycide that can be subjected to peripheral etching may be used.

〔The invention's effect〕

As described above in detail, according to the present invention, the formation of the gate electrode and the opening and the etching of the gate electrode material layer are performed using the same resist pattern as a mask.
Since the removal of the gate electrode material layer and the silicon layer for forming the low-concentration impurity region is performed using the etching selectivity, the entire surface etching step is eliminated. As a result, the influence of the etching on the underlying elements such as the field oxide film and the substrate can be suppressed. Therefore, it is possible to prevent device characteristics from being deteriorated due to the occurrence of a leak current or the like, and to obtain a highly reliable device with high yield. Further, since the device can be manufactured in a single photolithography process, the above-described problems are solved by unique effects such as improved workability, cost reduction, and minimization of mask alignment errors. Can be solved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a process according to an embodiment of the method of the present invention, and FIG. 2 is a sectional view of a process of a conventional method. 11 ... P-type silicon substrate, 11a ... N-type well layer, 12 ...
... field oxide film, 13 ... gate oxide film, 14 ... molybdenum film, 15 ... resist film, 16 ... gate electrode, 17 ...
... Si layer, 18 ...... N ⁺ -type highly-doped impurity regions, 19 ...... P ⁺ -type high concentration impurity regions, 20 ...... N ^- -type low concentration impurity regions, 21 ...... P ^-
Type low concentration impurity region.

Claims (2)

(57) [Claims] A gate oxide film on an active region of a semiconductor substrate;
A step of sequentially forming a gate electrode material layer and a resist film; a step of patterning the resist film into a predetermined shape; and a step of forming a periphery of the resist film with respect to the gate electrode material layer and the gate oxide film using the resist film as a mask. Etching under conditions such that only the portion is etched to form an opening and a gate electrode sandwiched by the opening; forming a silicon layer in the opening; and Removing the gate electrode material by etching, performing ion implantation using the gate electrode and the silicon layer as a mask to form a high-concentration impurity layer region, and etching and removing the silicon layer. Forming a low-concentration impurity layer region by performing ion implantation using the gate electrode as a mask. A method for manufacturing a semiconductor device, comprising: 2. An etching process is performed on the gate electrode material layer and the gate oxide film using the resist film as a mask under conditions such that only a peripheral portion of the resist film is etched. forming a gate electrode sandwiched between the oxygen occupancy of the etching gas O <sub>2
2. The</sub> method for manufacturing a semiconductor device according to claim 1, wherein the etching is performed in a range of / (O ₂ + CCl ₄ ) in the range of 0.6 to 0.7.