JP2876626B2 - Method of manufacturing vertical MOS field effect transistor - Google Patents
Method of manufacturing vertical MOS field effect transistorInfo
- Publication number
- JP2876626B2 JP2876626B2 JP1174576A JP17457689A JP2876626B2 JP 2876626 B2 JP2876626 B2 JP 2876626B2 JP 1174576 A JP1174576 A JP 1174576A JP 17457689 A JP17457689 A JP 17457689A JP 2876626 B2 JP2876626 B2 JP 2876626B2
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- region
- forming
- gate electrode
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 230000005669 field effect Effects 0.000 title claims description 5
- 239000012535 impurity Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 6
- 229910052698 phosphorus Inorganic materials 0.000 description 6
- 239000011574 phosphorus Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- -1 phosphorus ions Chemical class 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、縦型MOS電界効果トランジスタの製造方法
に関する。The present invention relates to a method for manufacturing a vertical MOS field effect transistor.
第２図（ａ）〜（ｄ）は従来の縦型MOSトランジスタ
の製造方法を説明するための工程順に示した断面図であ
る。2 (a) to 2 (d) are cross-sectional views shown in the order of steps for explaining a method of manufacturing a conventional vertical MOS transistor.
まず、第２図（ａ）に示すように、N+型シリコン基板
１の上にN-型層２を形成し、表面にゲート酸化膜４を40
〜150nmの厚さに形成する。表面からリンイオン７を注
入してＮ型領域８を形成する。First, as shown in FIG. 2A, an N − -type layer 2 is formed on an N + -type silicon substrate 1, and a gate oxide film 4 is formed on the surface of the N − -type layer.
It is formed to a thickness of 150 nm. N-type regions 8 are formed by implanting phosphorus ions 7 from the surface.
次に、第２図（ｂ）に示すように、多結晶シリコンで
ゲート電極５を形成し、ホウ素をイオン注入してＰ型ベ
ース領域３を形成する。熱処理して結晶回復を行うこと
によりＮ型領域８が深くなる。Next, as shown in FIG. 2B, a gate electrode 5 is formed of polycrystalline silicon, and boron is ion-implanted to form a P-type base region 3. The N-type region 8 is deepened by performing the crystal recovery by heat treatment.
次に、第２図（ｃ）に示すように、リンをイオン注入
してＮ型ソース領域６を形成する。Next, as shown in FIG. 2C, phosphorus is ion-implanted to form an N-type source region 6.
次に、第２図（ｄ）に示すように、層間絶縁膜９で覆
い、ソース領域６の部分に窓あけした後、ソース電極10
を設ける。裏面にAl等でドレイン電極11を形成する。Next, as shown in FIG. 2D, after covering with an interlayer insulating film 9 and opening a window in the source region 6, a source electrode 10 is formed.
Is provided. A drain electrode 11 is formed on the back surface using Al or the like.
縦型MOSトランジスタでは、通常ノーマリオフ型でエ
ンハンスメント型が作られている。ノーマリオン型のデ
プリッション型を作るには、Ｐ型ベース領域３を形成後
に、しき値制御のイオン注入を行なわなければならず、
多結晶シリコン層のゲート電極５をしきい値制御のイオ
ン注入の後に形成するため、ホトリソグラフィにおける
目ずれが発生するという欠点がある。In a vertical MOS transistor, a normally-off type and an enhancement type are usually made. To form a normally-on depletion type, after forming the P-type base region 3, ion implantation for controlling the threshold value must be performed.
Since the gate electrode 5 of the polycrystalline silicon layer is formed after the ion implantation for controlling the threshold, there is a disadvantage that misalignment occurs in photolithography.
また、ゲート酸化膜形成後に、リンイオン注入を行な
うと、Ｐ型ベース領域形成時に押込まれて深くなるた
め、デプリッション型にするまでイオン注入量を上げる
と高濃度となり、耐圧が劣化するという欠点がある 〔課題を解決するための手段〕 本発明の縦型MOS電界効果トランジスタの製造方法
は、相対的に高不純物濃度の一導電型半導体基板上に相
対的に低不純物濃度の一導電型第１領域を形成してドレ
イン領域とする工程と、前記ドレイン領域上にゲート絶
縁膜を介してゲート電極を形成する工程と、前記ゲート
電極をマスクにして逆導電型不純物をイオン注入し熱処
理を施して前記ゲート電極の両側であって前記ゲート電
極と前記ゲート絶縁膜を介して一部オーバーラップする
ように二つの逆導電型ベース領域を形成する工程と、前
記二つの逆導電型ベース領域を形成後、前記ゲート電極
をマスクにして一導電型不純物を導入して前記二つの逆
導電型ベース領域内にそれぞれ一導電型ソース領域を形
成する工程と、前記ゲート電極を含む表面上から一導電
型不純物をイオン注入して前記二つのソース領域を接続
してチャネル領域となる一導電型第２領域を形成する工
程とを含んで構成される。In addition, if phosphorus ions are implanted after the formation of the gate oxide film, they are pushed deeper when the P-type base region is formed. [Means for Solving the Problems] A method for manufacturing a vertical MOS field effect transistor according to the present invention is a method for manufacturing a vertical MOS field effect transistor, comprising the steps of: Forming a drain region, forming a gate electrode on the drain region via a gate insulating film, ion-implanting a reverse conductivity type impurity using the gate electrode as a mask and performing a heat treatment. Forming two opposite conductivity type base regions on both sides of the gate electrode so as to partially overlap with the gate electrode with the gate insulating film interposed therebetween; Forming two opposite-conductivity-type base regions and then introducing one-conductivity-type impurities using the gate electrode as a mask to form one-conductivity-type source regions in the two opposite-conductivity-type base regions; Ion-implanting one-conductivity-type impurities from the surface including the electrode to connect the two source regions to form a one-conductivity-type second region serving as a channel region.
第１図（ａ）〜（ｃ）は本発明の一実施例を説明する
ための工程順に示した断面図である。1 (a) to 1 (c) are cross-sectional views shown in the order of steps for explaining an embodiment of the present invention.
まず、第１図（ａ）に示すように、N+型シリコン基板
１の上にドレイン領域となるN-型層２を形成し、表面に
厚さ40〜150nmのゲート酸化膜４を形成する。多結晶シ
リコン層を0.3〜１μｍの厚さに堆積し、ホトリソグラ
フィ技術を用いてゲート電極５を形成する。ゲート電極
５をマスクにしてホウ素をイオン注入し、熱処理してＰ
型ベース領域３を形成する。リンをイオン注入してＰ型
ベース領域３内にＮ型ソース領域６を形成する。First, as shown in FIG. 1A, an N − type layer 2 serving as a drain region is formed on an N + type silicon substrate 1, and a gate oxide film 4 having a thickness of 40 to 150 nm is formed on the surface. . A polycrystalline silicon layer is deposited to a thickness of 0.3 to 1 μm, and a gate electrode 5 is formed using a photolithography technique. Using the gate electrode 5 as a mask, boron ions are implanted,
A mold base region 3 is formed. An N-type source region 6 is formed in the P-type base region 3 by ion implantation of phosphorus.
次に、第１図（ｂ）に示すように、リンイオン７を加
速エネルギー200keV〜1MeVで注入してＮ型領域８を形成
する。Next, as shown in FIG. 1B, an N-type region 8 is formed by implanting phosphorus ions 7 at an acceleration energy of 200 keV to 1 MeV.
次に、第１図（ｃ）に示すように、リンガラス等で層
間絶縁膜９を0.5〜１μｍの厚さに堆積し、ソール領域
６の部分に窓あけし、ソース電極10を形成する。裏面に
ドレイン電極11を形成する。Next, as shown in FIG. 1 (c), an interlayer insulating film 9 is deposited to a thickness of 0.5 to 1 [mu] m using phosphor glass or the like, and a window is formed in the sole region 6 to form a source electrode 10. The drain electrode 11 is formed on the back surface.
上記実施例ではＮ型ソース領域６を設けた後に、Ｎ型
領域８を形成したが、逆にＮ型領域８を形成した後、Ｎ
型ソース領域６を設けても良い。In the above embodiment, the N-type region 8 was formed after the N-type source region 6 was provided.
A mold source region 6 may be provided.
また、上記実施例は、Ｎチャネルの場合について説明
したが、すべての極性を逆にすれば、Ｐチャネルの場合
にも本発明は適用される。In the above embodiment, the case of the N channel is described. However, if all the polarities are reversed, the present invention can be applied to the case of the P channel.
以上説明したように、本発明は、縦型MOSトランジス
タの製造において、多結晶シリコンのゲート電極をマス
クにして、Ｐ型ベース領域を形成後、比較的高いエネル
ギー（200keV〜1MeV）のイオン注入を行なうことによ
り、耐圧を劣化させることなく、しきい値を自由に制御
できる効果がある。As described above, according to the present invention, in the manufacture of a vertical MOS transistor, ion implantation of relatively high energy (200 keV to 1 MeV) is performed after forming a P-type base region using a polysilicon gate electrode as a mask. By doing so, there is an effect that the threshold value can be freely controlled without deteriorating the breakdown voltage.
第１図（ａ）〜（ｃ）は本発明の一実施例を説明するた
めの工程順に示した断面図、第２図（ａ）〜（ｄ）は従
来の縦型MOSトランジスタの製造方法を説明するための
工程順に示した断面図である。 １…N+型シリコン基板、２…N-型層、３…Ｐ型ベース領
域、４…ゲート酸化膜、５…ゲート電極、６…Ｎ型ソー
ス領域、７…リンイオン、８…Ｎ型領域、９…層間絶縁
膜、10…ソース電極、11…ドレイン電極。1 (a) to 1 (c) are cross-sectional views showing steps in order to explain an embodiment of the present invention, and FIGS. 2 (a) to 2 (d) show a conventional method for manufacturing a vertical MOS transistor. It is sectional drawing shown in order of the process for description. DESCRIPTION OF SYMBOLS 1 ... N + type silicon substrate, 2 ... N - type layer, 3 ... P type base region, 4 ... Gate oxide film, 5 ... Gate electrode, 6 ... N type source region, 7 ... Phosphorus ion, 8 ... N type region, 9 ... interlayer insulating film, 10 ... source electrode, 11 ... drain electrode.
Claims (1)
板上に相対的に低不純物濃度の一導電型第１領域を形成
してドレイン領域とする工程と、前記ドレイン領域上に
ゲート絶縁膜を介してゲート電極を形成する工程と、前
記ゲート電極をマスクにして逆導電型不純物をイオン注
入し熱処理を施して前記ゲート電極の両側であって前記
ゲート電極と前記ゲート絶縁膜を介して一部オーバーラ
ップするように二つの逆導電型ベース領域を形成する工
程と、前記二つの逆導電型ベース領域を形成後、前記ゲ
ート電極をマスクにして一導電型不純物を導入して前記
二つの逆導電型ベース領域内にそれぞれ一導電型ソース
領域を形成する工程と、前記ゲート電極を含む表面上か
ら一導電型不純物をイオン注入して前記二つのソース領
域を接続してチャネル領域となる一導電型第２領域を形
成する工程とを含むことを特徴とする縦型MOS電界効果
トランジスタの製造方法。1. A step of forming a first region of one conductivity type having a relatively low impurity concentration on a semiconductor substrate of one conductivity type having a relatively high impurity concentration to form a drain region, and forming a gate insulating film on the drain region. Forming a gate electrode through a film, and ion-implanting a reverse-conductivity-type impurity using the gate electrode as a mask and performing a heat treatment on both sides of the gate electrode via the gate electrode and the gate insulating film. Forming two opposite conductivity type base regions so as to partially overlap with each other, and after forming the two opposite conductivity type base regions, introducing the one conductivity type impurity using the gate electrode as a mask to form the two opposite conductivity type base regions. Forming a source region of one conductivity type in the base region of the opposite conductivity type; and ion-implanting impurities of one conductivity type from above the surface including the gate electrode to connect the two source regions to each other. Vertical MOS field effect method for producing a transistor, which comprises a step of forming a one conductivity type second region serving as Le region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1174576A JP2876626B2 (en) | 1989-07-05 | 1989-07-05 | Method of manufacturing vertical MOS field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1174576A JP2876626B2 (en) | 1989-07-05 | 1989-07-05 | Method of manufacturing vertical MOS field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0338840A JPH0338840A (en) | 1991-02-19 |
| JP2876626B2 true JP2876626B2 (en) | 1999-03-31 |
Family
ID=15980973
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1174576A Expired - Fee Related JP2876626B2 (en) | 1989-07-05 | 1989-07-05 | Method of manufacturing vertical MOS field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2876626B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5248627A (en) * | 1992-03-20 | 1993-09-28 | Siliconix Incorporated | Threshold adjustment in fabricating vertical dmos devices |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5553454A (en) * | 1978-10-16 | 1980-04-18 | Fujitsu Ltd | Method for producing semiconductor device |
| JPS5868979A (en) * | 1981-10-21 | 1983-04-25 | Hitachi Ltd | Semiconductor device |
-
1989
- 1989-07-05 JP JP1174576A patent/JP2876626B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0338840A (en) | 1991-02-19 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |