JPH02105469A - Mis type semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a channel length without increasing a junction capacity between an impurity diffusion layer and a substrate by containing one conductivity type diffusion layer whose impurity concentration is lower than that of a semiconductor substrate which is in contact with a bottom side of a source/drain region consisting of a reverse conductivity type diffusion layer in contact with an edge end section of a gate insulating film and is formed apart from a channel region. CONSTITUTION:A semiconductor device contains; a p-type silicon substrate 1, a gate insulating film 2 and a polycrystalline silicon gate electrode 3, an N-type low concentration diffusion layer 4 of a source/drain region having an impurity concentration of about 5X10<17> <18>cm<-3>, for example, which is formed in an area near a channel region to come into contact with an edge end section of the gate insulating film 2, an N-type high concentration diffusion layer 5 of a source/drain region having an impurity concentration of about 1X10<20>cm<-3>, for example, which is in contact with an end side of an N-type low concentration diffusion layer 4 and formed apart from a channel region, and a P-type low concentration diffusion layer 7 of an impurity concentration of about 5X10<5>cm<-3> which is in contact with a bottom side of the N-type high concentration diffusion layer 5 and is formed inside the p-type silicon substrate 1 apart from a channel region further than the N-type high concentration diffusion layer 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to MIS type semiconductor devices, and particularly to short channel insulated gate field effect transistors.

[Conventional technology]

FIG. 5 shows a cross-sectional structural diagram of an N-channel insulated gate field effect transistor having a conventional LDD structure.
A polycrystalline silicon gate electrode 3 is formed on a P-type silicon substrate 1 via a gate insulating film 2, and an n-type low voltage layer in the source or drain region is formed in a self-aligned manner using the gate electrode 3 and the Zide wall 6 as a mask. A concentration diffusion layer 4 and an n-type high concentration diffusion layer 5 are provided on a substrate 1, respectively.

[Problem to be solved by the invention]

However, in conventional general MIS semiconductor devices including the above-mentioned LDDi structure, punch-through between the source and drain tends to occur as the channel length becomes shorter.
Therefore, when trying to shorten the channel, it is necessary to increase the impurity concentration of the substrate to prevent this. For example,
When the gate length is shortened to about 1 μm, the impurity concentration of the substrate is reduced to 5×1016Cal-3~I×I
It becomes necessary to increase the temperature to O”cry-3. However,
On the other hand, as the impurity concentration of the substrate increases, the junction capacitance between the source and drain impurity diffusion layers and the substrate increases, resulting in a new disadvantage of slowing down the operating speed of the transistor.

In view of the above circumstances, the object of the present invention is to provide a source.

It is an object of the present invention to provide a MIS type semiconductor device in which the channel length can be shortened without increasing the junction capacitance between each impurity diffusion layer of the drain and the substrate.

[Means to solve the problem]

According to the present invention, a MIS type semiconductor device includes a -conductivity type semiconductor substrate, a gate insulating film and a gate electrode formed on the semiconductor substrate, and a gate insulating film and a gate electrode formed so as to be in contact with edge portions of the gate insulating film, respectively. source and drain regions formed of opposite conductivity type diffusion layers, and a conductive layer with a lower impurity concentration than that of the semiconductor substrate formed in the semiconductor substrate in contact with the bottom surfaces of the source and drain regions and spaced apart from the channel region. and a type diffusion layer.

〔Example〕

The present invention will be described in detail below with reference to the drawings.

FIG. 1 and FIG. 2 illustrate the present invention in an LDD structure, respectively.
A cross-sectional structural diagram showing an example of implementation in a channel MOS insulated gate field effect transistor and its A-
It is a substrate concentration distribution map of A' and BB' cross section. According to this embodiment, the N-channel MOS insulated gate field effect transistor with the LDD structure has an impurity concentration of IX 1017
cm-' p-type silicon substrate 1, gate insulating film 2, polycrystalline silicon gate electrode 3, and an impurity concentration of about 5. n-type low concentration diffusion layer 4 in the source 1 and drain region and n
For example, an impurity concentration layer of approximately 1×10"cm-' is formed in contact with the end face of the type low concentration diffusion layer 4 and away from the channel region.
n-type high concentration diffusion layer 5 in the source and drain regions having Formed impurity concentration: approximately 5 x 1015c
m"" p-type paper concentration diffusion layer 7. Here, 8 is n
This is an integrated structure of side walls used to form the type high concentration diffusion layer 5 and the p type paper concentration diffusion layer 7, respectively. According to this embodiment, as is clear from the substrate concentration distribution diagram in FIG. Since it is diluted to /20, the junction capacitance between the n-type heavily doped diffusion layers in the source and drain regions and the p-type silicon substrate 1 can be reduced to about 1/4. The MO3 field effect transistor of the above embodiment can be manufactured by the following method.

FIGS. 3(a) to 3(f) are process flow diagrams showing one method of manufacturing the above embodiment. That is, the impurity concentration is I
A p-type silicon substrate 1 of x 10 "cm-" is first prepared, and a gate insulating film 2 and a polycrystalline silicon gate electrode 3 are selectively formed on the substrate 1 into predetermined shapes, and then the gate electrode 3 is masked. As shown in Fig. 3(a), n-type impurity ions 9 (for example, phosphorus) are implanted at an acceleration voltage of 40 KeV and a dose of 1 x 10''(C111-2>).Then, heat treatment is performed to form an n-type low concentration. After forming the diffusion layer 4, a silicon oxide film 10 is formed to a thickness of 2000 nm over the entire surface of the substrate by the CVD method.
Figure (b)]. Next, after performing anisotropic etch back to form side walls 8a only on the side surfaces of gate electrode 3, N-type impurity ions 11 (for example, arsenic) are etched using gate electrode 3 and side walls 8a as masks. Accelerating voltage 70 KeV, dose amount 5 x 1015 (cm-
") [Fig. 3(c)), and then heat treatment for activation is performed to form an n-type high concentration diffusion layer 5. After that, a silicon oxide film 10 is again deposited on the entire surface of the substrate by the CVD method for 40 minutes.
After forming a thick film of 0.00 mm (Fig. 3(d)), an anisotropic etch back is performed to form a second side film 8b along the outer wall of the side wall 8a. , using the side gates 8a and 8b and the gate electrode 3 as masks, the n-type impurity ions 12 (for example, phosphorus) are accelerated at a voltage of 200 K e V and a dose of 5 x 1012
Inject under the conditions of (C1m-2) [Figure 3(e)]. Thereafter, by performing heat treatment to activate the impurities, the impurity concentration in the substrate region in contact with the bottom surface of the n-type high concentration diffusion layer 5 is reduced to about 1/20, as shown in FIG. 3(f). A Nord paper density diffusion layer 7 having a density of 5×10” cm is obtained.

FIGS. 4(a) to 4(f) are process flow diagrams showing another method for manufacturing the semiconductor device of the present invention. To manufacture the semiconductor device of the present invention, relatively high energy is required for implanting n-type impurity ions 12 when forming n-type low concentration diffusion layer 7. This is because it is necessary to implant impurity ions, such as phosphorus, to a depth near the bottom of the source and drain. Therefore, if the gate electrode 3 is not thick enough, the ions may not be blocked and may penetrate into the channel region. In such cases, the following manufacturing method is effective.

That is, as shown in FIG. 4(a), first, a gate insulating film 2 and a polycrystalline silicon gate electrode g+3 are formed on a p-type silicon substrate 1 by laminating them in a predetermined shape using a resist pattern 13 as a mask. . Next, a resist material is applied again while leaving the resist pattern 13, and after covering the gate electrode 3 with a thick resist pattern 14 with an appropriate margin, the n-type impurity ions 12 (for example, phosphorus) are accelerated. Voltage: 300 KeV Dose: 5×1012 (C
Inject under the conditions of Ifi-2) [Figure 3(b)]. Then, the resist patterns 13 and 14 are removed and heat treated to form an n-type low concentration diffusion layer 7 inside the substrate [FIG. 3(C)]. After that, following the method shown in Fig. 3, using the gate electrode 3 as a mask, n-type impurity ions 9 (for example, phosphorus) are accelerated at a voltage of 40 KeV and a dose of IX.
10" (cm-2) [Fig. 3(d)
), after performing heat treatment to form the n-type low concentration diffusion layer 4,
A side wall 8a is formed, and n-type impurity ions 1 are injected using the gate electrode 3 and the side wall 8a as a mask.
1 (for example, arsenic) at an accelerating voltage of 70 KeV and a dose of 5
Inject under the condition of X 1015 (cm-2) [Figure 3 (
d)]. Then, by activating these impurity ions by performing appropriate heat treatment, it is possible to form an n-type high concentration diffusion layer 5 in contact with the n-type low concentration diffusion layer 7 in the substrate.
Figure (f)]. In this method, a resist film is used as a mask for implanting high-energy impurity ions, so the gate electrode 3
It is possible to completely prevent ions from penetrating into the channel region. Furthermore, since the etch-back step for forming the side walls only needs to be performed once, there is an advantage that damage to the substrate can be reduced compared to the method shown in FIG. 3 in which this step is performed twice.

Although only the case of the LDD structure has been described above, the present invention is not limited to this and can be implemented to all MIS type semiconductor devices. At this time, since the n-type low concentration diffusion layer 7 is formed at a certain distance from the channel region, it does not affect the substrate concentration of the channel region at all. Therefore, the transistor including the gate threshold voltage value (Vih) Suppresses the increase in junction capacitance between the source and drain diffusion layers and the substrate that occurs when the channel length is shortened, without affecting the voltage-current characteristics, drain breakdown voltage, and snapback voltage of the transistor. be able to.

〔Effect of the invention〕

As explained in detail above, according to the present invention, the source,
Since the substrate impurity concentration near the bottom of the drain region can be reduced, it is possible to completely solve the problem of increased junction capacitance between the source and train regions and the substrate, which occurs when the channel length is shortened. . At this time, since the region where the substrate is pushed back is separated from the channel region by a certain distance, the voltage-current characteristics of the transistor including the gate threshold voltage (Vth) and the drain breakdown voltage.

In other words, according to the present invention, there is no need to affect the snap-back voltage or the like, and it is possible to achieve a very significant effect in miniaturizing and increasing the speed of MIS type semiconductor devices.

[Brief explanation of the drawing]

FIG. 1 and FIG. 2 illustrate the present invention in an LDD structure, respectively.
A cross-sectional structural diagram showing an example of implementation in a channel MO8 insulated gate field effect transistor and its A-
A', BB' cross-section substrate concentration distribution diagram, Figure 3 (a)
4(a) to (f) are process sequence diagrams showing one method of manufacturing the above embodiment, FIGS. 4(a) to 4(f) are process sequence diagrams showing another method of manufacturing the semiconductor device of the present invention, and FIG. The figure shows the conventional L
FIG. 2 is a cross-sectional structural diagram of an N-channel insulated gate field effect transistor having a DD structure. 1...p-type silicon substrate, 2...gate insulating film, 3
... Polycrystalline silicon gate electrode, 4... N-type low concentration diffusion layer, 5... N-type high concentration diffusion layer, 7... P-type paper concentration diffusion layer, 8. (8a, 8b)...Side two-all, 9,1.1.12...n-type impurity ion, 10.
...CVD silicon oxide film, 13.14...resist pattern.

Claims (1)

[Claims] A source and a drain consisting of a semiconductor substrate of one conductivity type, a gate insulating film and a gate electrode formed on the semiconductor substrate, and a diffusion layer of opposite conductivity type formed in contact with the edge of the gate insulating film, respectively. and a diffusion layer of one conductivity type formed in the semiconductor substrate in contact with the bottom surfaces of the source and drain regions and spaced apart from the channel region, the impurity concentration being lower than that of the semiconductor substrate. type semiconductor device.