JPH05121436A - Thin film transistor and its manufacture - Google Patents
Thin film transistor and its manufactureInfo
- Publication number
- JPH05121436A JPH05121436A JP30711891A JP30711891A JPH05121436A JP H05121436 A JPH05121436 A JP H05121436A JP 30711891 A JP30711891 A JP 30711891A JP 30711891 A JP30711891 A JP 30711891A JP H05121436 A JPH05121436 A JP H05121436A
- Authority
- JP
- Japan
- Prior art keywords
- region
- thin film
- gate electrode
- film transistor
- implanted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000012535 impurity Substances 0.000 claims abstract description 44
- 238000005224 laser annealing Methods 0.000 claims abstract description 7
- 239000004065 semiconductor Substances 0.000 claims description 15
- 230000001133 acceleration Effects 0.000 claims description 14
- 150000002500 ions Chemical class 0.000 claims description 14
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 abstract description 14
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 9
- 239000011574 phosphorus Substances 0.000 abstract description 9
- 238000010276 construction Methods 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 abstract 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 abstract 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 5
- 230000005684 electric field Effects 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- -1 phosphorus ions Chemical class 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 238000009826 distribution Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は薄膜トランジスタおよ
びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and its manufacturing method.
【０００２】[0002]
【従来の技術】薄膜トランジスタには、通常のＭＯＳ構
造の素子と比較して、耐圧の向上等を図って高信頼性化
した素子として、ＬＤＤ（Ｌｉｇｈｔｌｙ Ｄｏｐｅｄ
Ｄｒａｉｎ）構造と呼ばれるものがある。図４は従来
のこのような薄膜トランジスタの一例を示したものであ
る。この薄膜トランジスタでは、セラミック等からなる
基板１の上面にポリシリコン等からなる半導体層２が設
けられ、半導体層２の中央部の上面にゲート絶縁膜３を
介してゲート電極４が設けられている。半導体層２は、
チャネル領域２ａの両側に不純物濃度の低いソース領域
２ｂおよびドレイン領域２ｃが形成され、これら不純物
濃度の低いソース領域２ｂおよびドレイン領域２ｃの外
側に不純物濃度の高いソース領域２ｄおよびドレイン領
域２ｅが形成された構造となっている。このうち不純物
濃度の低いドレイン領域２ｃは高電界を緩和するための
領域であり、これにより通常のＭＯＳ構造の素子と比較
して、耐圧の向上等を図って高信頼性化した素子が得ら
れることになる。2. Description of the Related Art A thin film transistor is an LDD (Lightly Doped) element which is highly reliable by improving withstand voltage and the like as compared with an element having a normal MOS structure.
There is a so-called Drain structure. FIG. 4 shows an example of such a conventional thin film transistor. In this thin film transistor, a semiconductor layer 2 made of polysilicon or the like is provided on an upper surface of a substrate 1 made of ceramic or the like, and a gate electrode 4 is provided on an upper surface of a central portion of the semiconductor layer 2 via a gate insulating film 3. The semiconductor layer 2 is
A source region 2b and a drain region 2c having a low impurity concentration are formed on both sides of the channel region 2a, and a source region 2d and a drain region 2e having a high impurity concentration are formed outside the source region 2b and the drain region 2c having a low impurity concentration. It has a different structure. Of these, the drain region 2c having a low impurity concentration is a region for alleviating a high electric field, and as a result, an element having higher reliability by improving withstand voltage and the like can be obtained as compared with an element having a normal MOS structure. It will be.
【０００３】ところで、このような構造の薄膜トランジ
スタでは、ソース領域２ｂ、２ｄおよびドレイン領域２
ｃ、２ｅを低温度でアニールする場合、まずゲート電極
４をイオン注入マスクとして低濃度のイオンを注入し、
次いで不純物濃度の低いソース領域２ｂおよびドレイン
領域２ｃを覆うイオン注入マスクを用いて高濃度のイオ
ンを注入し、次いで４００℃程度またはそれ以下の温度
のレーザアニールを行うことにより、結晶化や注入不純
物の活性化をするようにしている。この場合、低温度下
で行う関係から、注入不純物の拡散は行われず、このた
め図５に示すように、不純物濃度の勾配が急俊となって
しまう。By the way, in the thin film transistor having such a structure, the source regions 2b and 2d and the drain region 2 are formed.
When annealing c and 2e at a low temperature, first, low concentration ions are implanted using the gate electrode 4 as an ion implantation mask,
Then, high-concentration ions are implanted using an ion implantation mask covering the source region 2b and the drain region 2c having a low impurity concentration, and then laser annealing at a temperature of about 400 ° C. or lower is performed to crystallize or implant impurities. I am trying to activate. In this case, since the impurities are not diffused at a low temperature, the gradient of the impurity concentration becomes steep as shown in FIG.
【０００４】[0004]
【発明が解決しようとする課題】このように、従来の薄
膜トランジスタでは、ソース領域２ｂ、２ｄおよびドレ
イン領域２ｃ、２ｅを低温度でアニールすると、不純物
濃度の勾配が急俊となってしまうので、高電界を十分に
緩和することができず、このため耐圧の向上等を十分に
図ることができないという問題があった。また、特に高
濃度のイオンを注入するときイオン注入マスクを用いて
いるので、工程数が増大するという問題もあった。この
発明の目的は、不純物濃度の勾配を緩やかにすることが
でき、また工程数を減少することのできる薄膜トランジ
スタおよびその製造方法を提供することにある。As described above, in the conventional thin film transistor, if the source regions 2b, 2d and the drain regions 2c, 2e are annealed at a low temperature, the gradient of the impurity concentration becomes abrupt, so that There is a problem that the electric field cannot be relaxed sufficiently, and thus the breakdown voltage cannot be sufficiently improved. Further, there is a problem that the number of steps is increased because an ion implantation mask is used when implanting ions of high concentration. An object of the present invention is to provide a thin film transistor and a method for manufacturing the same that can reduce the gradient of impurity concentration and reduce the number of steps.
【０００５】[0005]
【課題を解決するための手段】請求項１記載の発明は、
ソース領域およびドレイン領域の不純物濃度の等濃度線
のプロフィルをそれぞれゲート電極領域外の所定深さの
位置からゲート電極領域下の表面に向かって曲線状に形
成したものである。請求項２記載の発明は、ソース領域
側の斜めおよびドレイン領域側の斜めからドーズ量と加
速エネルギを変えてそれぞれ複数回ずつイオンを注入す
ることにより、ソース領域およびドレイン領域の不純物
濃度の等濃度線のプロフィルをそれぞれゲート電極領域
外の所定深さの位置からゲート電極領域下の表面に向か
って曲線状に形成するようにしたものである。The invention according to claim 1 is
The profile of the isoconcentration lines of the impurity concentration of the source region and the drain region is formed in a curved shape from a position of a predetermined depth outside the gate electrode region toward the surface below the gate electrode region. According to a second aspect of the present invention, by implanting ions a plurality of times at different dose amounts and acceleration energies obliquely on the source region side and obliquely on the drain region side, the same concentration of the impurity concentration of the source region and the drain region is obtained. Each of the line profiles is formed in a curved shape from a position of a predetermined depth outside the gate electrode region toward the surface below the gate electrode region.
【０００６】[0006]
【作用】この発明によれば、ソース領域およびドレイン
領域の不純物濃度の等濃度線のプロフィルをそれぞれゲ
ート電極領域外の所定深さの位置からゲート電極領域下
の表面に向かって曲線状に形成しているので、４００℃
程度またはそれ以下の温度のレーザアニールを行って注
入不純物を拡散させることなく活性化しても、不純物濃
度の勾配を緩やかにすることができる。また、ソース領
域側の斜めおよびドレイン領域側の斜めからドーズ量と
加速エネルギを変えてそれぞれ複数回ずつイオンを注入
すると、高濃度のイオンを注入するときもイオン注入マ
スクを用いることなく行うことができ、したがって工程
数を減少することができる。According to the present invention, the profile of the isoconcentration lines of the impurity concentration of the source region and the drain region is formed in a curved shape from the position of a predetermined depth outside the gate electrode region toward the surface below the gate electrode region. So 400 ℃
Even if the laser annealing is performed at a temperature of about or less to activate the implanted impurities without diffusing them, the gradient of the impurity concentration can be made gentle. In addition, when the dose amount and the acceleration energy are changed obliquely on the source region side and the drain region side, respectively, and ions are injected plural times, it is possible to perform high-concentration ion implantation without using an ion implantation mask. Therefore, the number of steps can be reduced.
【０００７】[0007]
【実施例】図１はこの発明の一実施例におけるＬＤＤ構
造の薄膜トランジスタの要部を示したものである。この
薄膜トランジスタでは、セラミック等からなる基板１１
の上面にアモルファスシリコンからなる半導体層１２が
設けられ、半導体層１２の全表面にゲート絶縁膜１３が
設けられ、半導体層１２の中央部に対応する部分のゲー
ト絶縁膜１３の上面にゲート電極１４が設けられてい
る。半導体層１２は、後で詳述するように、ゲート電極
１４をマスクとして３０°および１５０°の角度から、
ドーズ量と加速エネルギを変えてそれぞれ３回ずつイオ
ンを注入することにより、ソース領域１２ａおよびドレ
イン領域１２ｂの不純物濃度の等濃度線のプロフィルが
それぞれゲート電極１４領域外の所定深さの位置からゲ
ート電極１４領域下の表面に向かって曲線状に形成され
た構造となっている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an essential part of a thin film transistor having an LDD structure according to an embodiment of the present invention. In this thin film transistor, the substrate 11 made of ceramic or the like is used.
The semiconductor layer 12 made of amorphous silicon is provided on the upper surface of the semiconductor layer 12, the gate insulating film 13 is provided on the entire surface of the semiconductor layer 12, and the gate electrode 14 is provided on the upper surface of the gate insulating film 13 corresponding to the central portion of the semiconductor layer 12. Is provided. As will be described later in detail, the semiconductor layer 12 is formed from the angles of 30 ° and 150 ° using the gate electrode 14 as a mask,
By implanting ions three times with different dose amounts and acceleration energies, the contours of the isoconcentration profile of the impurity concentration of the source region 12a and the drain region 12b are respectively formed from the position of a predetermined depth outside the region of the gate electrode 14 to the gate. The structure is formed in a curved shape toward the surface under the electrode 14 region.
【０００８】ここで、半導体層に対して垂直にドーズ量
と加速エネルギを変えて３回イオンを注入する場合の一
例について図３を参照しながら説明する。まず、ドーズ
量１×１０14／ｃｍ2、加速エネルギ１３０ｋｅＶの条
件下でリンイオンを注入すると、図３において曲線Ａで
示すように、不純物濃度が高く、かつそのピークが深さ
ｘｊの浅い部分に現われる。次に、ドーズ量２×１０13
／ｃｍ2、加速エネルギ１４５ｋｅＶの条件下でリンイ
オンを注入すると、図３において曲線Ｂで示すように、
不純物濃度が中位で、そのピークが深さｘｊのやや深い
部分に現われる。次に、ドーズ量５×１０12／ｃｍ2、
加速エネルギ１６０ｋｅＶの条件下でリンイオンを注入
すると、図３において曲線Ｃで示すように、不純物濃度
が低く、かつそのピークが深さｘｊのより深い部分に現
われる。そして、この３回のリンイオン注入の合計は、
図３における曲線Ｄの如くなり、不純物濃度のピークが
深さｘｊの浅い部分に現われ、かつこの部分よりも深い
ところで不純物濃度の勾配が緩やかとなる。Here, an example of implanting ions three times by changing the dose amount and the acceleration energy perpendicularly to the semiconductor layer will be described with reference to FIG. First, when phosphorus ions are implanted under the conditions of a dose amount of 1 × 10 14 / cm 2 and an acceleration energy of 130 keV, as shown by a curve A in FIG. 3, the impurity concentration is high and the peak is in a shallow portion of depth xj. Appears. Next, the dose amount 2 × 10 13
When phosphorus ions are implanted under the conditions of / cm 2 and an acceleration energy of 145 keV, as shown by a curve B in FIG.
The impurity concentration is medium, and its peak appears in a slightly deeper portion of the depth xj. Next, the dose amount is 5 × 10 12 / cm 2 ,
When phosphorus ions are implanted under the condition of the acceleration energy of 160 keV, as shown by the curve C in FIG. 3, the impurity concentration is low and its peak appears in the deeper part of the depth xj. And the total of these three phosphorus ion implantations is
As shown by the curve D in FIG. 3, the peak of the impurity concentration appears in the shallow portion of the depth xj, and the gradient of the impurity concentration becomes gentle in the deeper portion than this portion.
【０００９】そこで、ゲート電極１４をマスクとして、
斜め注入型イオン打ち込み装置を用いてドレイン領域１
２ｂ側から３０°の角度でリンイオン注入をドーズ量１
×１０14／ｃｍ2、加速エネルギ１３０ｋｅＶの条件下
で行うと、不純物濃度が高く、かつそのピークが図１に
おいて曲線Ｐで示すようになる。この曲線Ｐは、ゲート
電極１４領域外の所定深さの位置からゲート電極１４領
域下でゲート電極１４領域の図１における右端部の近傍
の表面に向かって曲線状に形成される。次に、同じく３
０°の角度でリンイオン注入をドーズ量２×１０13／ｃ
ｍ2、加速エネルギ１４５ｋｅＶの条件下で行うと、不
純物濃度が中位で、そのピークが図１において曲線Ｑで
示すようになる。この曲線Ｑは、ゲート電極１４領域外
で曲線Ｐよりも深い位置からゲート電極１４領域下でゲ
ート電極１４領域の図１における右端部から左側にやや
離間した表面に向かって曲線状に形成される。次に、同
じく３０°の角度でリンイオン注入をドーズ量５×１０
12／ｃｍ2、加速エネルギ１６０ｋｅＶの条件下で行う
と、不純物濃度が低く、かつそのピークが図１において
曲線Ｒで示すようになる。この曲線Ｒは、ゲート電極１
４領域外で曲線Ｑよりも深い位置からゲート電極１４領
域下でゲート電極１４領域の図１における右端部から左
側により大きく離間した表面に向かって曲線状に形成さ
れる。また、ソース領域１２ａ側から１５０°の角度で
リンイオン注入を同様の条件下で同じく３回行うと、高
い不純物濃度のピークが図１において曲線Ｓで示すよう
になり、また中位の不純物濃度のピークが図１において
曲線Ｔで示すようになり、さらに低い不純物濃度のピー
クが図１において曲線Ｕで示すようになる。次に、４０
０℃程度またはそれ以下の温度のレーザアニールを行っ
てアモルファスシリコンからなる半導体層１２を結晶化
してポリシリコンにするとともに注入不純物を活性化す
ると、注入不純物の拡散が殆ど行われなくとも、図２に
示すように、不純物濃度の勾配が緩やかになる。Therefore, using the gate electrode 14 as a mask,
Drain region 1 using oblique implantation type ion implanter
Phosphorus ion implantation with a dose of 1 at an angle of 30 ° from the 2b side
When performed under the conditions of × 10 14 / cm 2 and acceleration energy of 130 keV, the impurity concentration is high and the peak thereof is as shown by the curve P in FIG. 1. This curve P is formed in a curved shape from a position of a predetermined depth outside the region of the gate electrode 14 under the region of the gate electrode 14 toward the surface in the vicinity of the right end portion of the region of the gate electrode 14 in FIG. Then also 3
Phosphorus ion implantation with a dose of 2 × 10 13 / c at an angle of 0 °
Under the conditions of m 2 and acceleration energy of 145 keV, the impurity concentration is medium and the peak thereof is as shown by the curve Q in FIG. 1. The curve Q is formed in a curve shape from a position deeper than the curve P outside the region of the gate electrode 14 toward a surface slightly separated from the right end portion of the gate electrode 14 region in FIG. .. Next, phosphorus ion implantation is performed at the same angle of 30 ° and the dose amount is 5 × 10 5.
When performed under the conditions of 12 / cm 2 and acceleration energy of 160 keV, the impurity concentration is low and the peak thereof is as shown by the curve R in FIG. This curve R is the gate electrode 1
It is formed in a curved shape from a position deeper than the curve Q outside the region 4 to a surface below the region of the gate electrode 14 and further away from the right end portion of the gate electrode 14 region in FIG. 1 to the left. Further, when phosphorus ion implantation is performed three times under the same conditions at an angle of 150 ° from the source region 12a side, a peak of high impurity concentration becomes as shown by a curve S in FIG. The peak becomes as shown by the curve T in FIG. 1, and the peak of the lower impurity concentration becomes as shown by the curve U in FIG. Then 40
When laser annealing at a temperature of about 0 ° C. or lower is performed to crystallize the semiconductor layer 12 made of amorphous silicon into polysilicon and activate the implanted impurities, even if the implanted impurities are hardly diffused, FIG. As shown in, the gradient of the impurity concentration becomes gentle.
【００１０】このように、この薄膜トランジスタでは、
ソース領域１２ａおよびドレイン領域１２ｂの不純物濃
度の等濃度線のプロフィルをそれぞれゲート電極１４領
域外の所定深さの位置からゲート電極１４領域下の表面
に向かって曲線状に形成しているので、４００℃程度の
レーザアニールを行って注入不純物を拡散させることな
く活性化しても、不純物濃度の勾配を緩やかにすること
ができ、ひいては高電界を十分に緩和することができ、
耐圧の向上等を十分に図ることができる。また、ソース
領域１２ａ側の斜めおよびドレイン領域１２ｂ側の斜め
からドーズ量と加速エネルギを変えてそれぞれ３回ずつ
イオンを注入すると、高濃度のイオンを注入するときも
イオン注入マスクを用いることなく行うことができ、し
たがって工程数を減少することができる。Thus, in this thin film transistor,
The profile of the isoconcentration lines of the impurity concentration of the source region 12a and the drain region 12b is formed in a curved shape from a position of a predetermined depth outside the region of the gate electrode 14 toward the surface below the region of the gate electrode 14, and therefore 400 Even if laser annealing at about ℃ is performed and the implanted impurities are activated without being diffused, the gradient of the impurity concentration can be made gentle, and the high electric field can be sufficiently relaxed.
It is possible to sufficiently improve the breakdown voltage. Further, when ions are implanted three times with the dose amount and the acceleration energy being changed obliquely on the source region 12a side and on the drain region 12b side, high-concentration ions are implanted without using an ion implantation mask. Therefore, the number of steps can be reduced.
【００１１】[0011]
【発明の効果】以上説明したように、この発明によれ
ば、ソース領域およびドレイン領域の不純物濃度の等濃
度線のプロフィルをそれぞれゲート電極領域外の所定深
さの位置からゲート電極領域下の表面に向かって曲線状
に形成しているので、４００℃程度またはそれ以下の温
度のレーザアニールを行って注入不純物を拡散させるこ
となく活性化しても、不純物濃度の勾配を緩やかにする
ことができ、ひいては高電界を十分に緩和することがで
き、耐圧の向上等を十分に図ることができる。また、ソ
ース領域側の斜めおよびドレイン領域側の斜めからドー
ズ量と加速エネルギを変えてそれぞれ複数回ずつイオン
を注入すると、高濃度のイオンを注入するときもイオン
注入マスクを用いることなく行うことができ、したがっ
て工程数を減少することができる。As described above, according to the present invention, the profiles of the isoconcentration lines of the impurity concentration of the source region and the drain region are respectively provided at a predetermined depth outside the gate electrode region and on the surface below the gate electrode region. Since it is formed in a curved shape toward, even if laser annealing at a temperature of about 400 ° C. or lower is performed to activate the implanted impurities without diffusing, the impurity concentration gradient can be made gentle, As a result, the high electric field can be relaxed sufficiently, and the breakdown voltage can be sufficiently improved. In addition, when the dose amount and the acceleration energy are changed obliquely on the source region side and the drain region side, respectively, and ions are injected plural times, it is possible to perform high-concentration ion implantation without using an ion implantation mask. Therefore, the number of steps can be reduced.
【図１】この発明の一実施例におけるＬＤＤ構造の薄膜
トランジスタの要部の断面図。FIG. 1 is a sectional view of an essential part of a thin film transistor having an LDD structure according to an embodiment of the present invention.
【図２】図１のＸ−Ｘ線に沿う部分の不純物濃度図。2 is an impurity concentration diagram of a portion along line XX in FIG. 1. FIG.
【図３】半導体層に対して垂直にドーズ量と加速エネル
ギを変えて３回イオンを注入した場合の不純物濃度分布
図。FIG. 3 is an impurity concentration distribution diagram when ions are implanted three times while changing the dose amount and the acceleration energy perpendicularly to the semiconductor layer.
【図４】従来のＬＤＤ構造の薄膜トランジスタの一部の
断面図。FIG. 4 is a partial cross-sectional view of a conventional thin film transistor having an LDD structure.
【図５】図４のＹ−Ｙ線に沿う部分の不純物濃度図。5 is an impurity concentration diagram of a portion along line YY in FIG.
１１ 基板 １２ 半導体層 １２ａ ソース領域 １２ｂ ドレイン領域 １３ ゲート絶縁膜 １４ ゲート電極 11 substrate 12 semiconductor layer 12a source region 12b drain region 13 gate insulating film 14 gate electrode
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 27/12 8728−4Ｍ 8617−4Ｍ Ｈ０１Ｌ 21/265 Ｆ 8617−4Ｍ Ａ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI Technical display location H01L 27/12 8728-4M 8617-4M H01L 21/265 F 8617-4MA
Claims (4)
ドレイン領域の不純物濃度の等濃度線のプロフィルがそ
れぞれゲート電極領域外の所定深さの位置からゲート電
極領域下の表面に向かって曲線状に形成されていること
を特徴とする薄膜トランジスタ。1. A profile of isoconcentration lines of impurity concentration of a source region and a drain region formed in a semiconductor layer is curved from a position at a predetermined depth outside the gate electrode region toward a surface below the gate electrode region. A thin film transistor, which is formed.
域にイオンが注入された薄膜トランジスタを製造するに
際し、 ソース領域側の斜めおよびドレイン領域側の斜めからド
ーズ量と加速エネルギを変えてそれぞれ複数回ずつイオ
ンを注入することにより、ソース領域およびドレイン領
域の不純物濃度の等濃度線のプロフィルをそれぞれゲー
ト電極領域外の所定深さの位置からゲート電極領域下の
表面に向かって曲線状に形成することを特徴とする薄膜
トランジスタの製造方法。2. When manufacturing a thin film transistor in which ions are implanted into a source region and a drain region of a semiconductor layer, the dose amount and the acceleration energy are changed from an oblique angle on the source region side and an oblique angle on the drain region side a plurality of times. By injecting, the profile of the isoconcentration lines of the impurity concentration of the source region and the drain region is formed in a curved shape from the position of a predetermined depth outside the gate electrode region toward the surface below the gate electrode region. And a method of manufacturing a thin film transistor.
あり、ソース領域およびドレイン領域にイオンを注入し
た後４００℃以下でアニールを行うことを特徴とする請
求項２記載の薄膜トランジスタの製造方法。3. The method of manufacturing a thin film transistor according to claim 2, wherein the semiconductor layer is amorphous silicon, and annealing is performed at 400 ° C. or lower after implanting ions into the source region and the drain region.
とを特徴とする請求項３記載の薄膜トランジスタの製造
方法。4. The method of manufacturing a thin film transistor according to claim 3, wherein the annealing is laser annealing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30711891A JP3293039B2 (en) | 1991-10-28 | 1991-10-28 | Method for manufacturing thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30711891A JP3293039B2 (en) | 1991-10-28 | 1991-10-28 | Method for manufacturing thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05121436A true JPH05121436A (en) | 1993-05-18 |
| JP3293039B2 JP3293039B2 (en) | 2002-06-17 |
Family
ID=17965247
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30711891A Expired - Fee Related JP3293039B2 (en) | 1991-10-28 | 1991-10-28 | Method for manufacturing thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3293039B2 (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0670604A2 (en) * | 1994-03-03 | 1995-09-06 | Xerox Corporation | MOS thin-film transistors with a drain offset region |
| EP0675543A2 (en) * | 1994-03-31 | 1995-10-04 | Seiko Instruments Inc. | Semiconductor device including protection means and manufacturing method thereof |
| WO1999036965A1 (en) * | 1998-01-13 | 1999-07-22 | Lsi Logic Corporation | A high voltage transistor having a field oxide gate region |
| JPH11345978A (en) * | 1998-04-03 | 1999-12-14 | Toshiba Corp | Thin film transistor, its manufacture, and liquid crystal display device |
| KR100332565B1 (en) * | 1998-01-13 | 2003-06-12 | 엘지.필립스 엘시디 주식회사 | Method for fabricating liquid crystal display |
| JP2005093874A (en) * | 2003-09-19 | 2005-04-07 | Seiko Epson Corp | Semiconductor device and method of manufacturing semiconductor device |
| US6951793B2 (en) | 2002-05-29 | 2005-10-04 | Toppoly Optoelectronics Corp. | Low-temperature polysilicon thin film transistor having buried LDD structure and process for producing same |
| JP2006032930A (en) * | 2004-06-14 | 2006-02-02 | Semiconductor Energy Lab Co Ltd | Doping device |
| US7148091B2 (en) | 2004-08-06 | 2006-12-12 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing thin film transistor |
| US7352003B2 (en) | 1995-11-07 | 2008-04-01 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device having thin film transistor with LDD region |
| US7847348B2 (en) | 2008-03-14 | 2010-12-07 | Samsung Electronics Co., Ltd. | Semiconductor apparatus |
| JP2011129332A (en) * | 2009-12-17 | 2011-06-30 | Nissin Ion Equipment Co Ltd | Ion beam irradiation device |
| JP2014236120A (en) * | 2013-06-03 | 2014-12-15 | トヨタ自動車株式会社 | Semiconductor device and manufacturing method therefor |
-
1991
- 1991-10-28 JP JP30711891A patent/JP3293039B2/en not_active Expired - Fee Related
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0670604A3 (en) * | 1994-03-03 | 1996-09-25 | Xerox Corp | MOS thin-film transistors with a drain offset region. |
| EP0670604A2 (en) * | 1994-03-03 | 1995-09-06 | Xerox Corporation | MOS thin-film transistors with a drain offset region |
| US6097064A (en) * | 1994-03-31 | 2000-08-01 | Seiko Instruments Inc. | Semiconductor device and manufacturing method thereof |
| EP0675543A2 (en) * | 1994-03-31 | 1995-10-04 | Seiko Instruments Inc. | Semiconductor device including protection means and manufacturing method thereof |
| EP0675543A3 (en) * | 1994-03-31 | 1996-10-16 | Seiko Instr Inc | Semiconductor device including protection means and manufacturing method thereof. |
| US7352003B2 (en) | 1995-11-07 | 2008-04-01 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device having thin film transistor with LDD region |
| US6194766B1 (en) | 1998-01-13 | 2001-02-27 | Lsi Logic Corporation | Integrated circuit having low voltage and high voltage devices on a common semiconductor substrate |
| US6133077A (en) * | 1998-01-13 | 2000-10-17 | Lsi Logic Corporation | Formation of high-voltage and low-voltage devices on a semiconductor substrate |
| KR100332565B1 (en) * | 1998-01-13 | 2003-06-12 | 엘지.필립스 엘시디 주식회사 | Method for fabricating liquid crystal display |
| WO1999036965A1 (en) * | 1998-01-13 | 1999-07-22 | Lsi Logic Corporation | A high voltage transistor having a field oxide gate region |
| JPH11345978A (en) * | 1998-04-03 | 1999-12-14 | Toshiba Corp | Thin film transistor, its manufacture, and liquid crystal display device |
| US6951793B2 (en) | 2002-05-29 | 2005-10-04 | Toppoly Optoelectronics Corp. | Low-temperature polysilicon thin film transistor having buried LDD structure and process for producing same |
| JP2005093874A (en) * | 2003-09-19 | 2005-04-07 | Seiko Epson Corp | Semiconductor device and method of manufacturing semiconductor device |
| JP2006032930A (en) * | 2004-06-14 | 2006-02-02 | Semiconductor Energy Lab Co Ltd | Doping device |
| US7148091B2 (en) | 2004-08-06 | 2006-12-12 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing thin film transistor |
| US7847348B2 (en) | 2008-03-14 | 2010-12-07 | Samsung Electronics Co., Ltd. | Semiconductor apparatus |
| JP2011129332A (en) * | 2009-12-17 | 2011-06-30 | Nissin Ion Equipment Co Ltd | Ion beam irradiation device |
| JP2014236120A (en) * | 2013-06-03 | 2014-12-15 | トヨタ自動車株式会社 | Semiconductor device and manufacturing method therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3293039B2 (en) | 2002-06-17 |
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