JPH11345978A - Thin film transistor, its manufacture, and liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability of a low-temperature polysilicon thin film transistor by reducing the turning-off current of the transistor by arranging an intermediate-concentration first semiconductor area of a specific concentration between a low-concentration third semiconductor area and a high- concentration second semiconductor area in the transistor. SOLUTION: In a thin film transistor(TFT), the impurity concentrations of a low-concentration source-drain area 5, an intermediate-concentration source- drain area 11, and a high-concentration source-drain area 12 are respectively set between 1×10<16> cm<-3> and 1×10<18> cm<-3> , between 1×10<18> cm<-3> and 1×10<20> cm<-3> , and between 1×10<20> cm<-3> and 1×10<22> cm<-3> . It is necessary to increase the resistance of the low-concentration impurity area 5 for relieving electric field in the vicinity of the drain and, conversely, it is essential to decrease the contact resistance between the high-concentration impurity area 12 and a source-drain electrode 8. A potential barrier is formed against a minority carrier at a junction when the TFT is turned off by providing an n* area 11 having good activation between an n<+> area 5 and an n<+> area 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a method of manufacturing the same, and more particularly to a liquid crystal display device using the thin film transistor.

2. Description of the Related Art An active matrix type liquid crystal display device (hereinafter simply referred to as a liquid crystal display device) has features such as being thin and light, capable of being driven at a low voltage, and being easily colorized. In recent years, it has been used as a personal computer, a word processor or a portable information terminal. Among them, a thin film transistor (Thin Film Transistor) is used as a switching element of a pixel portion.
or: hereinafter, referred to as TFT).
Due to high display quality and low power consumption, research and development are being actively conducted. TF from the viewpoint of the material of the semiconductor layer
T is roughly classified into amorphous silicon T using amorphous silicon as a material of a semiconductor layer.
There are two types: FT and polysilicon TFT using polysilicon as the material of the semiconductor layer. Polysilicon TFT
Has an advantage that the mobility is about 10 to 100 times higher than that of the amorphous silicon TFT. For this reason, the polysilicon TFT is optimal as a pixel switching element. In recent years, the polysilicon TFT has been used also as a component of a peripheral drive circuit, and as a result, a TFT of a pixel portion and a TFT of a peripheral drive circuit are formed on the same substrate, which is a so-called pixel portion. -Research and development of liquid crystal display devices with integrated drive circuits are being actively conducted. However, since a polysilicon TFT has a higher process temperature than an amorphous silicon TFT (for example, 800 ° C., hereinafter referred to as a high-temperature polysilicon TFT),
Previously, an expensive glass substrate having heat resistance had to be used as an insulating substrate. Therefore, the process temperature is lowered (for example, 300 ° C.) so that a cheaper glass material can be used.
(.Degree. C. to 600.degree. C.) has been attracting attention. However, there is a problem that the low-temperature polysilicon TFT has a higher resistance value in the source / drain region of the contact layer than the high-temperature polysilicon TFT. This is because the low-temperature process has a lower impurity activation rate in the source / drain regions, and therefore has a lower carrier concentration proportional to the electric conductivity. Source of contact layer
If the resistance value of the drain region is high, the series resistance component increases, so that a sufficient ON current of the TFT cannot be obtained, and image quality deteriorates.
The polysilicon TFT is amorphous silicon TF
Since the mobility is higher than T, the size of the TFT is reduced, but the electric field intensity in the high electric field region generated near the drain of the active layer needs to be reduced. If the electric field strength near the drain is high, an impact ionization phenomenon and injection of carriers into the gate insulating film occur, which causes a shift in the gate threshold voltage (V _th ) of the TFT and lowers the reliability of the TFT. There's a problem. When used in a peripheral drive circuit, there is no particular problem, but when used in a pixel switching element, a problem of image quality degradation occurs.
Therefore, in order to solve the above problem, a polysilicon TFT used for the pixel portion is provided with Lightly Doped.
Drain (hereinafter, LDD or n ^- hereinafter) structure,
In order to reduce the resistance of the source / drain contact layer, it has been considered to adopt an n ⁺ contact structure in which a high concentration impurity is added. 7 (a) to 7
(E) shows a method of manufacturing an array substrate of a liquid crystal display device using a conventional high-temperature polysilicon TFT having an LDD structure and an n ⁺ contact layer as a switching element in a pixel portion by thermal annealing at 800 ° C. or higher. It is sectional drawing. This liquid crystal display device has a structure in which a pixel portion and a peripheral driving circuit portion are formed on the same substrate. Here, only CMOS transistors are shown as constituent elements of the peripheral drive circuit. The conductivity type of the polysilicon TFT used as the switching element in the pixel portion is an n-type channel.
First, as shown in FIG. 7A, after a polysilicon film is formed on a transparent insulating substrate 81, the polysilicon film is patterned to form semiconductor layers 82a to 82c. Next, after a gate insulating film 83 is formed on the entire surface, gate electrodes 84 a to 84 c are formed on the gate insulating film 83. Next, as shown in FIG. 7B, phosphorus (P) ions are implanted into the TFT region of the pixel portion while the CMOS region of the peripheral drive circuit portion is covered with the resist 85. As a result, the impurity concentration is relatively low (for example, 1 × 10 ¹⁸ cm).
⁽ Less than ⁻³ ) n ⁻ type source / drain regions (hereinafter referred to as low concentration source / drain regions) 86
It is formed in a self-aligned manner with respect to c. Next, FIG.
After removing the resist 85, the p-type TFT region in the CMOS region in the peripheral drive circuit portion, the gate electrode 84c in the pixel portion and the low-concentration n ⁻ -type source / drain region 86 in the vicinity thereof are formed into a resist 87. In a state covered with
An ion implantation of phosphorus (P) is performed. As a result, n ⁺ -type source / drain regions (hereinafter referred to as high-concentration source / drain regions) 88a and 88c having a high impurity concentration (for example, 1 × 10 ²⁰ cm ⁻³ ) are formed. Contact layer 88c
In order to reduce the resistance, the impurity concentration of the regions 88a and 88c needs to be higher in the low temperature process than in the high temperature process. Next, as shown in FIG. 7D, after removing the resist 87, the peripheral drive is performed in a state where the n-type TFT region of the CMOS region of the peripheral drive circuit portion and the TFT region of the pixel portion are covered with the resist 89. Boron (B) ions are implanted into the p-type TFT region in the CMOS region of the circuit portion. As a result, the impurity concentration becomes relatively high (for example, 1 × 10 ^19).
cm ⁻³ to 10 ²⁰ cm ⁻³ ) p ⁺ -type source / drain regions 88b are formed. Finally, as shown in FIG. 7E, after the resist 89 is removed, thermal activation of impurities (for example, high-temperature thermal annealing at 800 ° C. or higher), formation of the interlayer insulating film 90, and formation of the source / drain electrodes 91 are performed. The basic structure of each TFT is completed by sequentially forming the TFTs. Thereafter, pixel electrodes (not shown) are formed to complete the basic structure of the array substrate. However, TFTs having such an LDD structure and an n ⁺ -type contact structure have the following problems. That is, the low-concentration n ⁻ -type source / drain regions 86 and the high-concentration n ⁺ -type source / drain regions 88a and 88
8c has a problem in that since the activation rate of impurities is low, the junction characteristics with the n ⁻ region or the n-type channel are poor, and the leakage current (hereinafter referred to as TFT OFF current) that flows when the TFT is OFF is large. is there.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a highly reliable thin film transistor having a smaller OFF current than a conventional thin film transistor, a method of manufacturing the same, and An object of the present invention is to provide a liquid crystal display device using the thin film transistor.

A first aspect of the thin film transistor according to the present invention is an insulating substrate, a semiconductor layer using polysilicon formed on the insulating substrate, and a semiconductor layer formed in contact with the semiconductor layer. A gate insulating film, a gate electrode formed in contact with the gate insulating film, an active layer formed in a region of the semiconductor layer corresponding to the gate electrode, and the semiconductor layer outside the active layer. The formed impurity concentration is 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³
And a first semiconductor region having a lower impurity concentration than the first semiconductor region and an impurity concentration formed in the semiconductor layer outside the first semiconductor region and having the same conductivity type as that of the first semiconductor region. And two semiconductor regions. In a second aspect of the thin film transistor according to the present invention, an insulating substrate, a semiconductor layer using polysilicon formed on the insulating substrate, a gate insulating film formed in contact with the semiconductor layer, A gate electrode formed in contact with the gate insulating film, an active layer formed in a region of the semiconductor layer corresponding to the gate electrode, and an impurity concentration formed in the semiconductor layer outside the active layer being 1 × 10 ¹⁸
cm ^-3 and higher than or equal 1 × 10 ²⁰ cm ^-3 under the first semiconductor region, higher than the first outer said semiconductor layer in impurity concentration formed above the first semiconductor region of the semiconductor region And a second semiconductor region having the same conductivity type as that of the first semiconductor region, and an impurity concentration formed in a region of the semiconductor layer between the active layer and the first semiconductor region, wherein the first semiconductor region has an impurity concentration of the first semiconductor region.
And a third semiconductor region having the same conductivity type as the first semiconductor region and lower than the first semiconductor region. The activation rate of the first semiconductor region is 40%.
It is preferable that it is above. Note that the first semiconductor region may be formed between the second semiconductor region and the insulating substrate. Note that the impurity concentration of the second semiconductor region is preferably 1 × 10 ²⁰ cm ⁻³ or more and 1 × 10 ²² cm ⁻³ or less. Note that a boundary surface of a junction between the active layer and the first semiconductor region may be located at a position offset from an end of the gate electrode. Preferably, the width of the first semiconductor region is 0.2 μm or more and 2 μm or less. The thickness of the active layer is 10 nm to 10 nm.
It is preferably 0 nm. In the method for manufacturing a thin film transistor according to the present invention, a step of forming a semiconductor layer using polysilicon at a temperature of 600 ° C. or lower so as to be in contact with an insulating substrate, and a step of forming a gate insulating film so as to be in contact with the semiconductor layer A step of forming a gate electrode so as to be in contact with the gate insulating film, and an impurity concentration of 1 × 10 ¹⁸ cm ⁻³ or more and less than 1 × 10 ²⁰ cm ^{−3 in the} semiconductor layer outside the gate electrode. Forming a first semiconductor region, and the semiconductor layer outside the first semiconductor region has a higher impurity concentration than the first semiconductor region and has the same conductivity type as that of the first semiconductor region. Forming two semiconductor regions. The region of the semiconductor layer corresponding to the gate electrode and the first
Forming a third semiconductor region having an impurity concentration lower than that of the first semiconductor region and having the same conductivity type as that of the first semiconductor region. Note that, before forming the second semiconductor region, a gate insulating film over a region of the semiconductor layer where the second semiconductor region is formed may be removed. Further, a liquid crystal display device according to the present invention is characterized in that the thin film transistors of the first and second aspects are used as switching elements. According to the present invention, in the low-temperature polysilicon TFT, the first semiconductor region in the middle concentration portion is disposed between the third semiconductor region in the low concentration portion and the second semiconductor region in the high concentration portion, or By arranging the medium-concentration portion between the channel region (active layer) and the high-concentration portion, good junction can be obtained between the low-concentration portion and the high-concentration portion, and between the channel and the high-concentration portion. In the OFF state, a sufficient potential barrier can be formed for minority carriers at this junction, and the minority carriers are effectively blocked. Therefore, the OFF current is small,
A highly reliable low-temperature polysilicon TFT can be realized, and a liquid crystal display device with less deterioration in image quality can be realized.

Embodiments of the present invention will be described below with reference to the drawings.
This will be described with reference to FIG. (First Embodiment) FIGS. 1A to 1F show the present invention.
FIG. 4 is a sectional view showing a manufacturing process of the TFT according to the first embodiment.
FIG. The TFT of this embodiment is a coplanar type TF
T. First, as shown in FIG.
1 has an intrinsic type (impurity concentration) having a predetermined shape as a semiconductor layer.
Is 1 × 10¹⁶cm^-3Forming polysilicon film 20)
I do. The insulating substrate 1 is made of, for example, glass or the like.
Substrate made of rim material or substrate with insulating coating on the surface
Used. The thickness of the polysilicon film 20 of the TFT is generally
10 nm to 100 nm, but in this embodiment,
If it is 50 nm. The method for forming the polysilicon film 20 is as follows.
For example, solid phase growth from amorphous silicon film
Such as a plasma CVD method and an LPCVD method.
After forming the amorphous silicon film,
Crystallization of morphous silicon film by laser annealing
Method and SiH_Four, SiF_Four, H_TwoSuch as raw material
The polysilicon film is directly deposited by plasma CVD using gas.
There is a contact forming method. Next, as shown in FIG.
After forming a gate insulating film 3 on the entire surface,
A gate electrode 4 is formed on the edge film 3. With the gate insulating film 3
For example, use a silicon oxide film or silicon nitride film
The thickness is, for example, 100 nm. Gate insulating film
Examples of the film forming method 3 include a CVD method and a plasma CVD method.
Method and an ECR-CVD method. Also, the gate insulating film 3
May be used, which is obtained by thermally oxidizing a polysilicon film.
No. Next, as shown in FIG.
Phosphorus (P) as an n-type impurity
The ion implantation is performed on the low-concentration n^-Mold saw
A drain region 5 is formed. n^-Mold source dray
The region sandwiched between the active regions 5 becomes the active layer 2. Then n
^-Source / drain region 5 has an average impurity concentration of 5
× 10¹⁷cm^-3And, as shown in FIG.
Has a maximum value near the center in the vertical direction, but has an almost flat distribution.
It has an impurity concentration profile. Where the source
・ The expression "drain region" is used.
The distinction between source and drain does not occur unless actually used, and
Also, the source and drain may be switched during use
Because there is. Next, as shown in FIG.
Electrode 4 and n near it^-Source / drain regions
5 is covered with a resist 6a.
Phosphorus (P) is ion-implanted into the polysilicon film, and
Concentration n^*Form source / drain regions 11 are formed. This
When n^*Type source / drain region 11 has an average impurity
The substance concentration is 1 × 10¹⁹cm^-3And shown in FIG.
Has a maximum near the center in the depth direction, but is almost flat
It has an impurity concentration profile with a flat distribution. next
After removing the resist 6a, as shown in FIG.
Gate electrode 4 and n near it^-Source / Drain
Region 5 and n near it^*Source / drain region 1
1 covered with a resist 6b,
Phosphorus (P) is ion-implanted into the polysilicon film to form two high
Concentration n⁺Form source / drain regions 12 are formed. This
When n⁺Type source / drain region 12 has an average impurity
The substance concentration is 1 × 10²⁰cm^-3And shown in FIG.
Has a maximum near the center in the depth direction, but is almost flat
It has an impurity concentration profile with a flat distribution. this
As a result, as shown in FIG.
A low concentration of n outside the active layer 2^-Mold source / drain area
Zone 5, medium concentration n^*Source / drain region 11, high concentration
Degree n⁺Source / drain regions 12 are sequentially formed
You. Next, after removing the resist 6b, a laser beam or
Activation of impurity (P) by energy beam such as electron beam
(Laser annealing) and heat activity at low temperature of 600 ° C or less
(Thermal annealing at 300 ° C. to 600 ° C.). Leh
Since the annealing is completed in a short time, the impurity concentration profile
There is no problem that the file changes. Below 600 ° C
The same applies to thermal annealing. Furthermore, for cost reduction
Even if an inexpensive glass substrate is used as the insulating substrate 1,
There is no problem that the substrate is thermally damaged. next,
An interlayer insulating film 10 is formed on the entire surface as shown in FIG.
After n⁺Insulation on the source / drain region 12
The film 3 and the interlayer insulating film 10 are removed by etching to obtain n⁺
Hole for the source / drain region 12
Open. Finally, after forming a conductive film on the entire surface,
Pattern the conductive film to form source / drain electrodes 8
Thus, the basic structure of the coplanar TFT is completed. Impure
The impurity concentration is low impurity concentration of the source / drain region 5.
Degree 1 × 10¹⁶cm^-3More than 1 × 10¹⁸cm^-3Less than medium
Impurity concentration of the source / drain region 11 is 1 × 10
¹⁸cm^-3More than 1 × 10²⁰cm^-3Less than high concentration source
The impurity concentration of the drain region 12 is 1 × 10²⁰cm^-3that's all
1 × 10^{twenty two}cm^-3It is desirable that: Low concentration
The impurity region 5 has a high resistance to alleviate the electric field near the drain.
Therefore, high impurity concentration regions 12 need to be
Reduction of contact resistance with drain electrode 8 (1k
Ω) is essential. Medium concentration source / drain region 11
Impurity concentration of 1 × 10¹⁸cm^-3More than 1 × 10²⁰cm^-3
The reason why the value is preferably smaller than the above is described below. FIG.
Is a non-doped polysilicon film having a thickness of 50 nm.
The impurity concentration of phosphorus (P) when activated at a low temperature of 0 ° C.
5 is a characteristic graph showing a relationship between a degree and an activation rate. This feature
The sex graph was first obtained by the inventor.
You. Carrier concentration is obtained by multiplying impurity concentration by activation rate
become. This carrier concentration is determined by performing hole measurement.
And the impurity concentration is SIMS (Secondary-Io).
n Mass Spectroscopy)
It is measured by performing an analysis. As shown in FIG.
When activation is performed at a low temperature of 00 ° C., the impurity concentration becomes 1
× 10¹⁸cm^-3Less than (low concentration area) and 1 × 10²⁰
cm^-3Low activation rate in larger area (high concentration area)
No. Note that the impurity concentration is 1 × 10²⁰cm^-31x for
10¹⁸cm^-3Shows the same activation rate as in the case of
Concentration is 1 × 10²⁰cm^-3In the case of
The impurity concentration of the drain region 12 is 1 × 10 ²⁰cm^-3Place
1 × 10²⁰cm^-3in the case of
Exclude Generally, implanted into a semiconductor by ion implantation
Impurities often exist at interstitial positions,
It has no role as a donor or acceptor. this
Therefore, impurities are placed in the lattice position and activated electrically
In addition, lattice defects caused by the implantation
After implantation, heat treatment (animation)
Do). However, forming a high concentration (n +) region
In the case of ion implantation for
Because of its large size, low-temperature annealing at 600 ° C or lower
Insufficient recovery and efficient activation like high temperature annealing
Does not progress. Low concentration (n^-) Io to form region
In the case of ion implantation, the impurity concentration for ion implantation is polysilicon.
The trap concentration (10¹⁶c
m^-3-10 ¹⁷cm^-3) Because it is almost the same level as
Has a low activation rate but good crystallinity. this
Has low film damage due to small film damage due to ion implantation.
This is because crystallization can be sufficiently recovered by the use of a metal. As described above, n +
Only the region has poor crystallinity. Therefore, as in the conventional case,
The channel in the active layer and n⁺Joining when joining regions
Department or n^-Region and n⁺Smell at the joint when joining the areas
When the TFT is OFF, minority carriers (in this case,
The potential barrier to holes)
Absent. This makes it possible to sufficiently block minority carriers
No, the OFF current of the TFT increases. I
However, in the present embodiment, n^-Region 5 and n⁺region
Good activation rate (40% or more)
N with good crystallinity^*By providing the region 11, this n^*
Good contact between region 11 and n + region 12 having poor crystallinity
A combination can be formed. As a result, the O
Sufficient for minority carriers in the above junction at FF
Potential barrier can be formed
Carrier can be effectively prevented, and the OFF current can be reduced.
Can be done. Note that this medium concentration impurity region 11
Is not more than 0.2 μm, the phosphor from n + region 12
The impurity diffusion of (P) cannot be suppressed. The width is 2 μm
The following should be considered to reduce the resistance of the medium concentration impurity region 11.
Desirable for According to the present embodiment, the medium concentration n^*Type
The activation rate of the source / drain region 11 is 40% or more.
, N^*Region 11 and n⁺If the junction with region 12 is
OFF because it blocks the rear with high efficiency
Low current polysilicon TFT with low current and high reliability
realizable. (Second Embodiment) FIGS. 4A to 4F show the present invention.
Showing the manufacturing process of the TFT according to the second embodiment of FIG.
It is sectional drawing. The TFT of this embodiment is a coplanar type T
FT. First, as shown in FIG.
Polysilicon film 2 of predetermined shape as semiconductor layer on plate 1
0 is formed. The material and forming method of the polysilicon film 20
The film thickness is the same as in the first embodiment. Next, FIG.
As shown in (b), a gate insulating film 3 was formed on the entire surface.
Thereafter, gate electrode 4 is formed on gate insulating film 3.
The material, forming method and film thickness of the gate insulating film 3 and the gate electrode 4
Are the same as in the first embodiment. Next, in FIG.
As shown in FIG.
Is implanted into the polysilicon film 20 as phosphorus (P).
And two low concentrations of n^-Shaped source / drain region 5
To achieve. Then n^-Of the source / drain region 5
Impurity concentration of 1 × 10¹⁷cm^-3And FIG. 2
As shown in (a), there is a maximum value near the center in the depth direction
But with an almost flat distribution of impurity concentration profiles
I have. Next, as shown in FIG.
And n near it^-Type source / drain region 5
In the state covered with the gate 6a, phosphorus (P) as an n-type impurity is
Ions are implanted into the polysilicon film and two medium concentrations of n^*
Form source / drain regions 11 are formed. This n^*region
11 has an impurity concentration of 1 × 10¹⁹cm^-3And FIG. 2
As shown in (a), there is a maximum value near the center in the depth direction
But with an almost flat distribution of impurity concentration profiles
I have. Next, after removing the resist 6a, FIG.
As shown, the gate electrode 4 and the n-type
Drain region 5 and n in the vicinity thereof^*Type source
With the rain area 11 covered with the resist 6b, the gate
The insulating film 3 is etched. Subsequently, the resist 6b is removed.
After leaving, n to be formed⁺Insulating film on region 12
The ion implantation is performed in a state where there is no. In this case, the insulating film
Since the loss due to the absorbed dopant can be eliminated,
The processing time for injection can be shortened. For example, the formed n
⁺The average impurity concentration of the region 12 is 1 × 10²⁰cm^-3Toss
You. In this case, since there is no upper insulating film, FIG.
As shown, the peak intensity of ion implantation comes near the surface
Therefore, only high concentration n⁺Source / drain regions
12 can be formed. Phosphorus as n-type impurity
(P) is ion-implanted into the polysilicon film to form two highly concentrated layers.
Degree n⁺Type source / drain region 12 formed near the surface
I do. As a result, as shown in FIG.
Low concentration of n outside the active layer^-Source / Drain
Region 5, medium concentration n^*Type source / drain region 11,
N outside⁺Source / drain regions 12
In addition, medium concentration n^*Source / drain region 11 at the bottom
It is formed. Next, after removing the resist 6b, the laser
Impurities due to energy beams such as laser light and electron beams
Activation of (P) (laser annealing) or 600 ° C or less
Thermal activation (thermal annealing below 600 ° C)
U. As in the first embodiment, the impurity concentration profile
There is no problem that the file changes. Next, FIG.
As shown, after forming an interlayer insulating film 10 on the entire surface, n⁺
Gate insulating film 3 on type source / drain region 12 and
The interlayer insulating film 10 is removed by etching, and n⁺Type source
Open contact hole for drain region 12
You. Finally, after forming a conductive film on the entire surface, this conductive film is
Etching to form source / drain electrodes 8
The basic structure of the planar type TFT is completed. In this embodiment
It is needless to say that the same effect as in the first embodiment can be obtained.
In addition, the following effects can be obtained. Sand
In this embodiment, n⁺Low ion implantation in region 12
It is performed under acceleration conditions (for example, 10 KeV to 30 KeV).
Where n^-Region 5, n^*Region 11 (and the p-type MOS
Gate insulating film 3 on source / drain regions (not shown)
N-type impurities such as phosphorus (P) with low acceleration
However, this has a good effect on the element characteristics.
n^-Region 5, n^*The ion implantation for forming the region 11 is high.
Gate insulation because of acceleration (for example, 50 KeV or more)
A large damage is left on the film 3. Then n⁺Region 12
At the time of formation, ions are implanted into the gate insulating film 3 at low acceleration.
As a result, the implanted dopant causes damage to the gate insulating film 3.
Acts to mitigate. Also, it is formed by a low temperature process.
Oxide film (insulating film) is different from thermal oxide film in density and good
Although this is not a good film, the dopant having a slightly different atomic radius from Si
Injection of punt atoms acts to properly terminate defects
And improve the film quality. In this case, the gate insulating film 3
Almost no ions are implanted in the source / drain regions.
No. In a TFT, the electric field intensity is high near the drain end.
And the best film quality is required. In that sense, n^-Territory
Area 5, n^*Region 11 (and source / drain of p-type MOS)
By implantation into the insulating film on the in-region (not shown)
High quality plays a large role in improving characteristics. (Third Embodiment) FIGS. 5A to 5F show the present invention.
Showing the manufacturing process of the TFT according to the third embodiment of the present invention.
It is sectional drawing. The TFT of this embodiment is also a coplanar type T
FT. In the present embodiment, n^-Eliminate LDD area
Instead of n^*Region 11 is the end of gate electrode 4
It has a structure offset from it. First, FIG.
As shown in (a), as a semiconductor layer on the insulating substrate 1
A polysilicon film 20 having a predetermined shape is formed. Polysil
The material, forming method and film thickness of the con film 20 are the same as those of the previous embodiment.
The same is true. Next, as shown in FIG.
After forming the gate insulating film 3, a gate is formed on the gate insulating film 3.
A gate electrode 4 is formed. Gate insulating film 3, gate electrode 4
The material, the forming method, and the film thickness are the same as in the previous embodiment.
You. Next, as shown in FIG.
And covered with resist 6a
In this state, phosphorus (P) as an n-type impurity is
Into two intermediate concentrations of n^*Type sauce dress
An in-region 11 is formed. This n^*Average of area 11
Pure substance concentration is 1 × 10¹⁹cm^-3And FIG. 2 (a)
As shown, it has a maximum value near the center in the depth direction, but almost
It has an impurity concentration profile having a flat distribution.
Next, after removing the resist 6a, as shown in FIG.
As described above, the gate electrode 4 and n^*Type source
With the rain area 11 covered with the resist 6b, the gate
The insulating film 3 is etched. Subsequently, the resist 6b is removed.
After leaving, n to be formed⁺The insulating film on the region 12
The ion implantation is performed in the absence. In this case, the insulating film absorbs
Ions due to the loss of dopants collected
Injection processing time can be reduced. For example, the formed n⁺
The impurity concentration of the region 12 is 1 × 10^{Two 0}cm^-3And this
Also, n⁺There is no insulating film on the region 12 and n⁺Area 12
Because the peak concentration of ion implantation comes near the surface of
Only high concentrations of n⁺Form source / drain regions 12
can do. Phosphorus (P) as an n-type impurity
Ion implantation into the silicon film yields two high-concentration n⁺Type
The source / drain region 12 is formed near the surface. This result
As a result, as shown in FIG.
Medium concentration n outside the conductive layer 2^*Source / drain regions
11, further high concentration n⁺Source / Drain
Region 12 is on top and medium concentration n^*Mold source / drain area
Zone 11 is formed at the bottom. The active layer 2 and n^*region
11 is offset from the end of the gate electrode 4
It is in the position. Then, such as laser light and electron beam
Activation of impurity (P) by energy beam (laser
Annealing) or thermal activation at a low temperature of 600 ° C. or less (600 ° C.).
C. or lower). Same as the previous embodiment
In addition, the problem that the impurity concentration profile changes
Absent. Next, as shown in FIG.
After forming the film 10, n⁺Source / drain region 12
Etching of the gate insulating film 3 and the interlayer insulating film 10
Remove n⁺Type source / drain region 12
Open contact hole. Finally, form a conductive film on the entire surface
After the formation, this conductive film is etched and the source drain
Electrode 8 to complete the basic structure of the coplanar TFT.
To achieve. Note that n^*Off from gate electrode end of region 11
The set amount x (see FIG. 3C) is n^-There is an LDD region
Since the resistance of the active layer 2 is higher than in the case,⁺Area 1
2 can be closer to the end of the gate electrode 4
You. Usually n^-The resistance of the LDD region is 100 kΩ or less
, N^*Region 11 is n^-Lower resistance by at least one digit than LDD area
(10 kΩ or less). However, the active layer 2 has n^-LD
Higher resistance (more than 10MΩ) by at least two orders of magnitude
To the gate end^*The area 11 may be expanded. This implementation
In the embodiment, the effect of the process reduction, and the second embodiment and
Needless to say, the same effect can be obtained.
Such effects can be obtained. That is, good activity of crystallinity
High activation rate with layer 2 and good crystal recovery by annealing
n^*The direct bonding of the region 11 provides good bonding characteristics.
TFT with low OFF current
You. Further, n^*By offsetting the area 11
And the deterioration due to the high electric field near the drain can be suppressed.
And a highly reliable TFT can be realized. (Fourth Embodiment) FIGS. 6A to 6F show the present invention.
Showing the manufacturing process of the TFT according to the fourth embodiment of the present invention.
It is sectional drawing. The TFT of this embodiment is an inverted stagger type T
FT. First, as shown in FIG.
After the gate electrode 4 is formed on the plate 1, the gate electrode 4
A gate insulating film 3 is formed on the entire surface. Gate insulating film
3. The material, forming method and film thickness of the gate electrode 4 are the same as those of the previous embodiment.
Same as the form. Next, as shown in FIG.
Polysilicon having a predetermined shape as a semiconductor layer on an edge substrate 1
A film 20 is formed. Material and formation of polysilicon film 20
The method and the film thickness are the same as those in the above embodiment. On this
300nm silicon nitride formed by CVD and patterned
Thereby, the channel protective film 13 is formed. Next
Next, as shown in FIG.
Phosphorus (P) as an n-type impurity
Ion implantation into the ion implantation film to obtain two low concentration n^-Type source
The drain region 5 is formed. This n^-Impurity concentration in region 5
The degree is 5 × 10^{1 7}cm^-3And as shown in FIG.
Has a maximum value near the center in the depth direction, but is almost flat
Has an impurity concentration profile having the following distribution. Next
Next, as shown in FIG.
And n near it^-Type source / drain region 5 as resist
6a, phosphorus (P) as an n-type impurity is
Ions are implanted into the silicon layer to form two medium-concentration n^*Type
Source / drain regions 11 are formed. This n^*Area 1
The impurity concentration of 1 is 1 × 10¹⁹cm^-3And FIG. 2
As shown in (a), there is a maximum value near the center in the depth direction.
Impurity concentration profile with almost flat distribution
Having. Next, after removing the resist 6a, FIG.
As shown in (e), the channel protective film 13 and its vicinity are formed.
Beside n^-Source / drain region 5 and n in the vicinity thereof^*
Source / drain region 11 covered with resist 6b
In this state, phosphorus (P) as an n-type impurity is added to the polysilicon film.
Ion implantation, two high concentrations of n⁺Mold source dray
Forming region 12. This n⁺Impurity concentration of region 12
Is 1 × 10²⁰cm^-3And as shown in FIG.
Has a maximum near the center in the depth direction, but is almost flat.
It has an impurity concentration profile having a distribution. This result
As a result, as shown in FIG.
A low concentration of n outside the conductive layer 2^-Source / drain regions
5. Medium concentration n^*Source / drain region 11, high concentration
N⁺Source / drain regions 12 are sequentially formed
You. Next, laser annealing or heat at a low temperature of 600 ° C or less
Activation is performed by annealing. Laser annealing is short
And the impurity concentration profile changes
No problem arises. The same applies to thermal annealing at a low temperature.
Furthermore, inexpensive insulating substrate 1 is used for cost reduction.
Even if a glass substrate is used, the glass substrate
No problem. Next, as shown in FIG.
After the interlayer insulating film 10 is formed on the entire surface, n⁺Type source
Gate insulating film 3 and interlayer insulating film 1 on rain region 12
0 by etching away, n⁺Source / drain regions
Then, a contact hole is opened with respect to No. Finally, all
After forming a conductive film on the surface, this conductive film is etched,
A source / drain electrode 8 is formed, and an inverted stagger type TFT is formed.
The basic structure of is completed. In this embodiment as well,
Needless to say, the same effect can be obtained.
The following effects are obtained. That is, this TFT is formed
With the color filter substrate facing the array substrate
When a liquid crystal display device is created by injecting liquid crystal between plates,
In order to make light incident from the lower part of the ray substrate, the gate electrode
Light shielding of the active layer, which is a channel, reduces light leakage.
Function as a thin TFT and play a large role in improving characteristics
No. The present invention is limited to the above-described embodiment.
is not. For example, in the above embodiment, the coplanar type
Although the case of a TFT or an inverted stagger type TFT has been described,
In the present invention, the reverse staggered TFT is used for film growth and patterning.
It can be applied to a staggered TFT in which the order is reversed. In addition,
In the first to fourth embodiments, the n-channel TF
T has been described as an example.
It is needless to say that can be applied. Also,
In the first to fourth embodiments, the active layer is intrinsic.
(Intrinsic), but impurities (eg,
For example, phosphorus or boron)¹⁷cm^-3Including degree
You may. Next, T of the first to fourth embodiments described above is used.
Active matrix using FT as pixel switching element
The configuration of the trix-type liquid crystal display device will be described with reference to FIG.
You. This liquid crystal display device has an array substrate 100 and a counter substrate.
200. Array substrate 100 is transparent insulation
Area 102a of a transparent substrate (for example, a glass substrate) 101
In addition, a plurality of signal lines 103 and
And a plurality of scanning lines 104, a signal line 103, and a scanning line 104.
Consisting of TFTs formed at each intersection with
Element 105 and an image provided for each switching element.
It has a configuration in which the elementary electrodes 106 are formed. Each sui
The gate of the switching element 105 is connected to the corresponding signal line 103.
Connected and one of the source and drain
And the other is connected to the pixel electrode 106.
Has been continued. The array substrate 100 is made of a transparent insulating material.
TFT is provided in the non-display area 102b around the conductive substrate 101.
Drive circuits 110 and the drive circuits 110
External end for supplying power and signals from the connected external
A child 120 is formed. On the other hand, the opposite substrate 200 is transparent.
On one surface of a clear insulating substrate 201, ITO (Indiu
m Tin Oxide) is a transparent conductive film
It is configured as a pole 203. these
The substrates 100 and 200 are opposed to each other so as to have a predetermined gap.
Is placed. Then, the display area 102 of the array substrate 100
a seal applied on the non-display area 102b so as to surround a
It is bonded by the material 300. For sealing material 300
Is an injection port 301 for injecting a liquid crystal material as shown in FIG.
Are formed. Then, the substrates 100 and 200
After bonding, the liquid crystal composition is
(Not shown) is injected into the gap and sealed
The liquid crystal display device is completed. Note that the liquid crystal display is
-In the case of a liquid crystal display device, the counter substrate 200 or
A color filter is formed on one side of the array substrate 100
Configuration. TFTs of the First to Fourth Embodiments
Is used as the pixel switching element.
Current can be reduced to prevent image quality degradation.
Can be. In addition, without departing from the gist of the present invention.
If so, various modifications are possible.

As described above, according to the present invention, it is possible to provide a highly reliable thin film transistor having a smaller OFF current than the conventional one, a method of manufacturing the same, and a liquid crystal display device using the thin film transistor. Become.

[Brief description of the drawings]

FIG. 1 is a process cross-sectional view showing a manufacturing process of a TFT according to a first embodiment of the present invention.

FIG. 2 shows n of the TFT according to the first embodiment of the present invention.
FIG. 9 is a diagram showing an impurity concentration profile of a type impurity (phosphorus) and an impurity concentration profile of an intermediate concentration layer of the TFT according to the second embodiment.

FIG. 3 is an enlarged view of an impurity region of the TFT of the present invention.

FIG. 4 is a process cross-sectional view showing a manufacturing process of a TFT according to a second embodiment of the present invention.

FIG. 5 is a process cross-sectional view showing a manufacturing process of a TFT according to a third embodiment of the present invention.

FIG. 6 is a process cross-sectional view showing a manufacturing process of a TFT according to a fourth embodiment of the present invention.

FIG. 7 is a process sectional view showing a manufacturing process of an array substrate of a conventional liquid crystal display device integrated with a pixel portion and a peripheral driving circuit portion.

FIG. 8 is a graph showing a relationship between an impurity concentration, an activation rate, and a carrier concentration in a low-temperature process.

FIG. 9 is a schematic view illustrating a configuration of an active matrix liquid crystal display device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Insulating substrate 2 ... Active layer 3 ... Gate insulating film 4 ... Gate electrode 5 ... n ^- type source / drain region 8 ... Source / drain electrode 10 ... Interlayer insulating film 11 ... n ^* -type source / drain region 12 ... n ⁺ Type source / drain region 20: polysilicon film

Claims (12)

[Claims] 1. An insulating substrate, a semiconductor layer using polysilicon formed on the insulating substrate, a gate insulating film formed in contact with the semiconductor layer, and formed in contact with the gate insulating film An active layer formed in a region of the semiconductor layer corresponding to the gate electrode, and an impurity concentration formed in the semiconductor layer outside the active layer is 1 × 10 ¹⁸ cm ⁻³ or more. And a first semiconductor region of less than 1 × 10 ²⁰ cm ⁻³ and an impurity concentration formed in the semiconductor layer outside the first semiconductor region is higher than that of the first semiconductor region and the first semiconductor region And a second semiconductor region having the same conductivity type as the semiconductor region. 2. An insulating substrate, a semiconductor layer using polysilicon formed on the insulating substrate, a gate insulating film formed in contact with the semiconductor layer, and a gate insulating film formed in contact with the gate insulating film ³ or more ^- a gate electrode, an active layer formed in a region of the semiconductor layer corresponding to the gate electrode, the impurity concentration formed on the semiconductor layer outside of the active layer 1 × 10 ¹⁸ cm And a first semiconductor region of less than 1 × 10 ²⁰ cm ⁻³ and an impurity concentration formed in the semiconductor layer outside the first semiconductor region is higher than that of the first semiconductor region and the first semiconductor region A second semiconductor region of the same conductivity type as the semiconductor region; and an impurity concentration formed in a region of the semiconductor layer between the active layer and the first semiconductor region, which is lower than that of the first semiconductor region. Same as the first semiconductor region A thin film transistor characterized by comprising a third semiconductor region of a conductivity type, the. 3. An activation rate of the first semiconductor region is 40.
%. 4. The thin film transistor according to claim 1, wherein said first semiconductor region is formed between said second semiconductor region and said insulating substrate. 5. An impurity concentration of said second semiconductor region is 1
The thin film transistor according to claim 1, wherein the thickness is not less than × 10 ²⁰ cm ^{−3 and not} more than 1 × 10 ²² cm ⁻³ . 6. The thin film transistor according to claim 1, wherein a boundary surface of a junction between the active layer and the first semiconductor region is located at a position offset from an end of the gate electrode. 7. The width of the first semiconductor region is 0.2 μm.
The thin film transistor according to claim 1, wherein the thickness is not less than 2 μm. 8. The active layer has a thickness of 10 nm to 100 n.
3. The thin film transistor according to claim 1, wherein m is m. 9. A step of forming a semiconductor layer using polysilicon at a temperature of 600 ° C. or less so as to be in contact with the insulating substrate; a step of forming a gate insulating film so as to be in contact with the semiconductor layer; A step of forming a gate electrode so as to be in contact with the film;
A first not less than × 10 ¹⁸ cm ^-3 and less than 1 × 10 ²⁰ cm ^-3
Forming a semiconductor region, and a second semiconductor having an impurity concentration higher than that of the first semiconductor region in the semiconductor layer outside the first semiconductor region and having the same conductivity type as that of the first semiconductor region. Forming a region; and a method of manufacturing a thin film transistor. 10. The semiconductor device according to claim 1, wherein said first semiconductor region has a lower impurity concentration than said first semiconductor region and has the same conductivity type as a region between said semiconductor layer region corresponding to said gate electrode and said first semiconductor region. 10. The method of manufacturing a thin film transistor according to claim 9, further comprising the step of forming a third semiconductor region. 11. The method according to claim 9, wherein before forming the second semiconductor region, a gate insulating film on a region of the semiconductor layer where the second semiconductor region is formed is removed. 12. A liquid crystal display device using the thin film transistor according to claim 1 as a switching element.