JPH11111985A - Manufacture of thin-film transistor and liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method through which a highly reliable thin-film transistor having superior electrical characteristics and high durability can be formed. SOLUTION: After a polysilicon film has been formed on an insulating substrate 1, the substrate 1 is divided into elements having a prescribed shape. Then, after a gate insulating film 4 has been formed on the upper surface of each divided polysilicon film, a gate electrode 5 is formed on the upper surface of the insulating film 4. Thereafter, a source region 6, a drain region 7, and a channel region 8 are formed by implanting impurity ions into the polysilicon film by using the gate electrode 5 as a mask. After the regions 6, 7, and 8 have been formed, an inter-layer insulating film 9 is formed on the upper surface of the gate insulating film 4, and the source and the drain areas 6 and 7 are exposed by forming contact holes through part of the insulating film 9. Then, after the interface is stabilized by performing heat treatment at a temperature of >=400 deg.C, metal wires 11 are ohmic-contacted with the source and the drain regions 6 and 7 via the contact hole.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for manufacturing a thin film transistor formed on an insulating substrate, for example, a thin film transistor used for an active matrix type liquid crystal display device.

[0002]

2. Description of the Related Art Thin film transistors (hereinafter referred to as TFTs) used in active matrix type liquid crystal display devices.
Has an amorphous silicon type TFT (a-Si type TF)
T) and a polysilicon type TFT (p-Si type TFT). The p-Si type TFT has characteristics that the mobility of electrons is higher by one to two digits than that of the a-Si type TFT, a CMOS configuration is possible, power consumption is small, and a built-in peripheral driving circuit is easy.

[0003]

In manufacturing a p-Si type TFT, a heat treatment for stabilizing an interface characteristic between a gate oxide film and a polysilicon layer and a method for lowering the resistance of a source / drain portion are required. Heat treatment is indispensable, and these heat treatments are performed at a temperature of about 400 to 600 ° C.

However, since the p-Si type TFT is formed on a glass substrate, there is a problem that the process temperature cannot be too high, and the gate oxide film must be formed at a low temperature. Characteristics tend to vary, and there are also problems in durability and reliability.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a manufacturing method capable of forming a thin film transistor having excellent electrical characteristics, durability, and reliability. .

[0006]

According to a first aspect of the present invention, there is provided a first step of forming a polycrystalline silicon layer on an insulating substrate, and a step of forming a polycrystalline silicon layer on an upper surface of the polycrystalline silicon layer. A second step of forming a gate oxide film; a third step of forming a gate electrode in a part of the gate oxide film; and implanting impurity ions using the gate electrode as a mask. A fourth step of forming a source region and a drain region therein, a fifth step of covering a surface of the polycrystalline silicon layer with an interlayer insulating film, and forming a first contact hole in a part of the interlayer insulating film. A sixth step of exposing the source region and the drain region, and a seventh step of performing a heat treatment at a temperature equal to or lower than a strain point of the insulating substrate to stabilize an interface state of the first contact hole. Process and Embedding a conductive layer on the first contact hole, the conductive layer and a the source region is in ohmic contact, and, and a eighth step of ohmic contact with the drain region and the conductive layer.

According to a second aspect of the present invention, in the method of manufacturing a thin film transistor according to the first aspect, in the sixth step, the first contact hole is formed by etching, and in the seventh step, the first contact hole is formed. A heat treatment is performed at a predetermined temperature for a predetermined time so that damage caused by etching of the gate oxide film in contact with the first contact hole is recovered.

According to a third aspect of the present invention, in the method of manufacturing a thin film transistor according to the first or second aspect, the heat treatment is performed at a temperature of 400 ° C. or more in the seventh step.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device using the manufacturing method of the first to third aspects.
After the step, a ninth step of covering the upper surface of the conductive layer with a second interlayer insulating film, and forming a second contact hole in a part of the second interlayer insulating film to expose the conductive layer And forming a pixel electrode in ohmic contact with the conductive layer via the second contact hole.
1 step.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a method of manufacturing a thin film transistor according to the present invention will be specifically described with reference to the drawings. Hereinafter, as an example, a method for manufacturing a thin film transistor used in an active matrix liquid crystal display device will be described.

FIG. 1 is a cross-sectional view of a thin film transistor according to the present invention, FIGS. 2 and 3 are views showing a manufacturing process of the thin film transistor of FIG. 1, and FIG. The thin film transistor of the present embodiment is a so-called p-Si type TFT formed using polysilicon as a material. Hereinafter, a manufacturing process of the thin film transistor shown in FIG. 1 will be described with reference to FIGS.

First, step S1 of FIG. 4 and FIG.
As shown in FIG. 1A, an amorphous silicon (amorphous silicon) film 2 having a film thickness of 500 to 1000 angstroms is formed on an insulating substrate 1 made of non-alkali glass, alkali glass or the like by plasma CVD. The amorphous silicon film 2 can be formed not only by plasma CVD but also by a thermal decomposition method of disilane using a low pressure CVD apparatus.

Next, as shown in step S2 of FIG.
Heat treatment is performed at about 400 ° C. for about 1 hour to desorb hydrogen in the amorphous silicon film 2. This heat treatment step is provided in order to prevent ablation due to laser irradiation when crystallizing amorphous silicon.

Next, step S3 in FIG. 4 and FIG.
As shown in FIG. 1B, the amorphous silicon film 2 is irradiated with a laser to be crystallized to form a polycrystalline silicon (polysilicon) film 3 and then to separate elements into a predetermined shape.

Next, step S4 in FIG. 4 and FIG.
As shown in (c), a gate insulating film 4 is formed on the upper surface of the polysilicon film 3 by a normal pressure CVD method. Next, FIG.
As shown in Step S5, the gate insulating film 4 is heat-treated at a temperature of 500 ° C. or more for about 5 hours. In this case, as the heat treatment temperature is higher, the polysilicon film 3 and the gate insulating film 4
And the interface state generated between them becomes smaller, and the reliability of the gate insulating film 4 becomes higher. More specifically, the higher the heat treatment temperature, the smaller the amount of characteristic shift in a BTS test or the like, but the greater the deformation of the insulating substrate 1 such as warpage or undulation. Also, the cooling rate is (−2) ° C./min to (−
5) Within the range of ° C./min, the amount of shrinkage increases.

Next, step S6 in FIG. 4 and FIG.
As shown in (d), the gate electrode 5 is formed on the gate insulating film 4.
To form Next, step S7 in FIG.
As shown in (a), using the gate electrode 5 as a mask,
Impurity ions are implanted into the polysilicon film 3 to form a source region 6, a drain region 7, and a channel region 8 having a self-aligned structure. At this time, a p-channel type or n
The type of impurity ions to be implanted is changed depending on whether or not a channel type is used.

Next, step S8 of FIG. 4 and FIG.
As shown in (b), an interlayer insulating film 9 is formed on the upper surface of the gate insulating film 4. Next, as shown in step S9 of FIG. 4, heat treatment is performed at about 600 ° C. for about 3 hours to reduce the resistance of the source region 6 and the drain region 7. At this time, the higher the heat treatment temperature, the lower the resistance, and the better the electrical characteristics, but the larger the amount of shrinkage of the insulating substrate 1.

Next, step S10 of FIG. 4 and FIG.
As shown in FIG. 1C, contact holes 10 are formed at predetermined locations in the gate insulating film 4 and the interlayer insulating film 9. Next, as shown in step S11 of FIG. 4, heat treatment is performed at a temperature of about 400 ° C. or higher for 15 to 180 minutes. Thereby, the interface state density of 4 × 10 ¹¹ (cm ⁻² eV ⁻¹ ) becomes 3
It was reduced to × 10 ¹⁰ (cm ^-2 eV ^-1 ), and it was confirmed that good characteristics were obtained. The heat treatment in step S11 is performed in an atmosphere of an inert gas such as nitrogen.

Next, step S12 of FIG. 4 and FIG.
As shown in (d), a metal wiring 11 is ohmic-joined to the source region 6 and the drain region 7 via the contact hole 10 and an interlayer insulating film 12 is formed on the upper surface thereof.
As in step S13 in FIG. 4, a contact hole is formed, a transparent electrode 13 is formed on the metal wiring 11, and processed into a predetermined shape.

Next, the thin film transistor array substrate formed by the above-mentioned steps is arranged opposite to the opposing substrate at a predetermined interval, and liquid crystal is injected between the substrates and bonded to each other to obtain a liquid crystal display device. .

As described above, in the present embodiment, the interlayer insulating film 9
After the contact hole 10 is formed at a predetermined position and before forming the source electrode and the drain electrode, heat treatment is performed at a temperature of 400 ° C. or more, so that the interface can be stabilized. When TF is formed, the contact resistance can be reduced and the mobility can be improved.
The electrical characteristics of T are improved. As a result, the driving speed of the liquid crystal display device can be improved. When a TFT is formed without performing heat treatment after forming a contact hole 10 for forming a source electrode and a drain electrode as in the related art, a large amount of direct current (for example, the ratio W / L of the gate width W to the gate length L becomes large). 10/5
μm, a DC current of 0.1 mA or more)
There is a problem that the transistor characteristics deteriorate and the on / off ratio cannot be obtained.

On the other hand, as shown in step S11 of FIG. 3, after forming the gate insulating film 4 and the contact hole 10 and performing a heat treatment at a temperature of 400 ° C. or more, a TFT having a source electrode and a drain electrode formed thereon is used. In a reliability test, it was confirmed that a sufficient on / off ratio can be obtained even when a direct current of 0.1 mA flows through the sample of W / L = 10/5. The reason for the improved characteristics is that when a contact hole is formed in the gate insulating film 4, particularly when the contact hole is formed by dry etching such as RIE, the sidewall of the contact hole 10 in the gate insulating film may be damaged. It is considered that this damage was recovered by the heat treatment process.

In this embodiment, after the heat treatment for recovering the interface damage is performed, the metal wiring 11
A source electrode and a drain electrode are formed. At this time, heat treatment is required, but the metal wiring 11 is usually made of Al or
Since Al alloy is used as a material, if heat treatment is performed at a high temperature, hillocks may be generated, and heat treatment must be performed at a low temperature. However, in the present embodiment, a high-temperature heat treatment for recovering damage is performed before the formation of the source electrode and the drain electrode, so that hillocks do not occur.

In step S11 of FIG.
An example of heat treatment at 400 ° C has been described, but the heat treatment temperature is 400 ° C.
With the above, the same effect can be obtained.

In the above embodiment, the thin film transistor used in the liquid crystal display device has been described as an example. However, the thin film transistor according to the present embodiment can be applied to various transistors used in devices other than the liquid crystal display device.

[0026]

As described above in detail, according to the present invention, after a contact hole is formed for the purpose of forming a source electrode and a drain electrode, damage to the gate insulating film caused when the contact hole is formed is reduced. Since the source electrode and the drain electrode are formed after the heat treatment for recovery, the electrical characteristics, durability and reliability of the TFT are improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a thin film transistor according to the present invention.

FIG. 2 is a manufacturing process diagram of the thin film transistor of FIG. 1;

FIG. 3 is a manufacturing process diagram following FIG. 2;

FIG. 4 is a flowchart illustrating a procedure of a manufacturing process.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 insulating substrate 2 amorphous silicon film 3 polysilicon film 4 gate insulating film 5 gate electrode 6 source region 7 drain region 8 channel region 9, 12 interlayer insulating film 10 contact hole 11 metal wiring 13 transparent electrode

Claims (4)

[Claims] A first step of forming a polycrystalline silicon layer on an insulating substrate; a second step of forming a gate oxide film on an upper surface of the polycrystalline silicon layer; and a part of the gate oxide film In the third step, a gate electrode is formed.
Implanting impurity ions using the gate electrode as a mask,
A fourth step of forming a source region and a drain region in the polycrystalline silicon layer; a fifth step of covering a surface of the polycrystalline silicon layer with an interlayer insulating film; Forming a contact hole, exposing the source region and the drain region, and performing a heat treatment at a temperature equal to or lower than a strain point of the insulating substrate to stabilize an interface state of the first contact hole. A seventh step of embedding a conductive layer in the first contact hole, making an ohmic contact between the conductive layer and the source region, and making an ohmic contact between the conductive layer and the drain region. And a method for manufacturing a thin film transistor. 2. In the sixth step, the first contact hole is formed by etching, and in the seventh step, damage due to etching of the gate oxide film in contact with the first contact hole is recovered. 2. The method according to claim 1, wherein the heat treatment is performed at a predetermined temperature for a predetermined time. 3. The method according to claim 1, wherein the heat treatment is performed at a temperature of 400 ° C. or more in the seventh step. 4. A ninth step of covering the upper surface of the conductive layer with a second interlayer insulating film after the eighth step, and forming a second contact hole in a part of the second interlayer insulating film. A tenth step of forming and exposing the conductive layer; and an eleventh step of forming a pixel electrode in ohmic contact with the conductive layer via the second contact hole. A method for manufacturing a liquid crystal display device using the manufacturing method according to any one of Items 1 to 3.