JPH0637314A - Thin-film transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To facilitate the formation of a gate overlapping LDD by forming a gate electrode in two-layer structure of an upper layer and a lower layer and performing the ion implantation of impurities with both electrodes being used for a mask without equalling the width of both electrodes. CONSTITUTION:A gate electrode 5 of a lower layer is worked for a predetermined shape with a reactive ion etcher. Then, the width of an electrode for the gate electrode 5 of a lower layer is made to be 5mum. After that, a polysilicon film to act as a gate electrode 7 of an upper layer is formed on the whole surface of a glass substrate 1 including the electrode 5 of a lower layer. And then the width of an electrode for the gate electrode 7 of an upper layer is so worked as to become 3mum with the center line of the electrode width of the gate electrode 5 of a lower layer being aligned with that of the gate electrode 7 of an upper layer. Next, P-type ion implantation is so performed as to form a high concentration region in a gate electrode 6 and at the same time to form an impurity region 10 having an LDD structure in the polysilicon film. Since the gate electrode width of an upper and a lower layer is not the same, a gate overlapping LDD structure may be easily formed with once implantation of impurity ions being performed by using the gate electrode of an upper and a lower layer for a mask.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a manufacturing method thereof, and more particularly to a thin film transistor manufactured on an insulating substrate such as a liquid crystal display and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, the performance of liquid crystal displays has been remarkably improved. In particular, an active matrix liquid crystal display having a switching function such as a diode or a thin film transistor for each picture element greatly contributes to the improvement of image quality and the increase in screen size. ing. Many thin film transistors provided for each picture element use amorphous silicon as an active layer of the transistor on an insulating substrate, which enables a large area and a low process temperature (up to 350 ° C.). It has advantages such as.

In addition, a thin film transistor using polysilicon as an active layer has been partially commercialized, and by utilizing its high mobility characteristic, not only switching for each picture element but also a driving circuit is constituted, We have realized a liquid crystal display with an integrated drive circuit. However, since the process temperature of a polysilicon thin film transistor is usually high, a glass substrate cannot be used and a quartz substrate is used.
The quartz substrate is more expensive than the glass substrate, and it is difficult to increase the area. Therefore, the immediate goal of polysilicon thin film transistors is to reach the usable temperature of the glass substrate (~ 6
It is to develop a process that can obtain stable characteristics at (00 ° C).

[0004]

When a polysilicon thin film transistor is used as described above, the greatest advantage is that a liquid crystal display integrated with a drive circuit can be realized.
However, since the off-state current of the polysilicon thin film transistor is higher than that of the amorphous silicon thin film transistor, it cannot be said to be suitable as a transistor provided for each pixel.

As a method of reducing the off current of a polysilicon thin film transistor, a dual gate structure, a thin film of polysilicon, and an LDD (Lightly Doped Drain) structure have been considered, but all have advantages and disadvantages. The dual gate structure is a method in which two or more transistors are connected in parallel and have a common gate electrode, and the off-current is reduced by relaxing the drain electric field when the transistors are turned off. However, it is not desirable to form two or more transistors in a limited space because it leads to a reduction in the aperture ratio of the picture element.

The thinning of polysilicon is a very simple method, and the off current is reduced by increasing the resistance between the source and the drain by thinning. However, the expected reduction effect has not been obtained. LDD (Lightly Doped
In the Drain structure, for example, when the source / drain is an n ⁺ layer, an n ⁻ layer is provided between the channel and the source and between the channel and the drain. As shown in FIG. 13, the gate electrode 2 is usually formed on the polysilicon film 22.
3 is formed, low-concentration ions are implanted using the gate electrode 23 as a mask to form an n ⁻ layer 24 (FIG. 13).
(A)). Next, a side wall insulator 25 is formed on the side wall of the gate electrode 23, and then ion implantation is performed again to form the n ⁺ layer 2
This is realized by forming 6 (FIG. 13B).

As another method, as shown in FIG. 14, an n ⁻ layer 34 is formed by oblique rotation ion implantation using the gate electrode 33 as a mask (FIG. 14A), and then a normal ion implantation method is applied. To form the n ⁺ layer 35 (FIG. 14).
(B)). This method is called a gate overlap LDD structure because the n ⁻ layer 34 deeply enters the channel region and has a structure having a large overlap with the gate.

In either structure, the off-current can be reduced by relaxing the drain electric field and improving the breakdown voltage, but in the LDD structure of FIG. 13, the source n ^- layer is formed when a voltage is applied to the gate. The current resistance is reduced due to the parasitic resistance of. On the other hand, in the gate overlap LDD structure of FIG. 14, the n ⁻ layer exists below the gate electrode, so that the current driving capability is not impaired. However, in any of the methods, there are problems that it is necessary to perform ion implantation twice, and the manufacturing process such as formation of sidewall insulators or oblique rotation ion implantation becomes complicated.

Next, the problems of low temperature process polysilicon thin film transistors which can use glass substrates will be touched upon. Since the thin film transistor is generally a field effect transistor, its characteristics are greatly affected by the state of the interface between the gate insulating layer and the polycrystalline Si film that serves as the channel. Therefore, in the conventional high temperature process, the interface between the gate insulating layer and the channel is formed inside the channel layer by the thermal oxidation method, and the interface state is kept good. On the other hand, in the low temperature process, since the gate insulating layer also needs to be formed at a low temperature, the above thermal oxidation method cannot be used. Therefore, a method is adopted in which the polycrystalline Si film is processed into a predetermined shape, the surface is cleaned with hydrofluoric acid or the like, and then the gate insulating film is formed by sputtering, CVD, or the like. However, the interface state density has not been sufficiently reduced.

Therefore, a method of continuously forming a gate insulating film without exposing it to the atmosphere after forming a polycrystalline Si film has been studied. In this method, the gate insulating film and the polycrystalline Si film are formed. When processed into a predetermined shape, the side surface of the polycrystalline Si film is exposed. Then, when the gate electrode is formed thereafter, the sidewalls of the gate electrode and the exposed polycrystalline Si film come into contact with each other, which causes a problem that the leak current increases. Therefore, it is necessary to protect the sidewall of the polysilicon with an insulator, but it is necessary that the insulator protecting the sidewall of the polysilicon and the gate insulating film can be selectively etched. Therefore, the gate insulating film and the sidewall are protected. There is a problem that the insulating material for protection is limited.

The present invention has been made in view of the above problems, and is an ideal manufacturing method even in a low temperature process in which a glass substrate can be used, and is the best method for reducing the off current. It is an object of the present invention to provide a thin film transistor and a method of manufacturing the thin film transistor which can relatively easily realize a certain gate overlap LDD structure.

[0012]

In order to achieve the above-mentioned object, according to the present invention, a thin film transistor in which a polysilicon layer which becomes an active layer of a transistor, a gate insulating film and a gate electrode are sequentially formed on an insulating substrate. There is provided a thin film transistor, wherein the gate electrode has a two-layer structure of an upper layer gate electrode and a lower layer gate electrode, and the electrode width of the upper layer gate electrode and the electrode width of the lower layer gate electrode are not the same width.

From another point of view, (i) a step of sequentially forming a polysilicon layer, a gate insulating film, and a lower gate electrode on an insulating substrate to form a laminated film, (ii) the laminated film And then forming an insulator on the sidewall of the island pattern, (iii) processing only the lower gate electrode into a predetermined shape, and further forming an upper gate electrode on the lower gate electrode. And (iv) processing the upper gate electrode into a predetermined shape, (v) implanting impurity ions into the polysilicon layer using the lower gate electrode and the upper gate electrode as a mask, A method of manufacturing a thin film transistor including a step of forming an impurity diffusion region is provided.

The insulating substrate in the present invention is not particularly limited as long as it is a substrate usually used for a thin film transistor, and a glass substrate, a quartz substrate or the like can be used. Then, an insulating film such as a nitride film is laminated on the insulating substrate directly or in order to prevent diffusion of impurities from the substrate to a thickness of about 500 to 3000 Å, and a polysilicon film to be an active layer of the thin film transistor is formed. . This polysilicon is formed at a temperature of 500 to 600 ° C. in a vacuum or in an inert gas atmosphere after forming an amorphous silicon film using silane gas or the like at 400 to 600 ° C. by a known method such as a CVD method. It can be formed by annealing for several hours. Further, it can be similarly performed in a high temperature process using a quartz substrate or the like. At this time, the film thickness of polysilicon is 500 to 1500Å
A degree is preferable. The film formed as the gate insulating film can be variously selected within the range that does not adversely affect the transistor characteristics, but the SiO ₂ film is preferable. S
The iO ₂ film can be formed by a known method, for example, a CVD method. At this time, the thickness of the SiO ₂ film is 500 to
About 1500Å is preferable. Note that the steps from forming amorphous silicon on an insulating substrate to forming a gate insulating film should be performed in a vacuum or in an inert gas atmosphere without being exposed to the outside air. Is preferred.

The gate electrode of the thin film transistor according to the present invention has a two-layer structure of a lower layer and an upper layer, and the electrode widths of the upper layer gate electrode and the lower layer gate electrode do not have the same width. That is, the upper layer gate electrode has a larger electrode width than the lower layer gate electrode, or the lower layer gate electrode has a larger electrode width than the upper layer gate electrode. However, when the electrode width of the lower layer gate electrode is larger than that of the upper layer gate electrode, a part of the lower layer gate electrode is exposed when processing the upper layer gate electrode, and therefore the etching time is not accurately controlled. However, if the lower gate electrode is smaller than the electrode width of the upper gate electrode, the above problem is prevented. It is preferable to have an electrode width larger than that of the lower layer gate electrode. Note that the electrode width of these gate electrodes depends on the size of a thin film transistor to be manufactured and is not particularly limited. Further, the lower layer gate electrode and the upper layer gate electrode can be variously selected from various metals or polysilicon films, etc. within a range that does not adversely affect the transistor characteristics, but in the case of polysilicon, at the time of ion implantation for source / drain formation, A gate electrode can be formed by simultaneously implanting ions. Polysilicon can be formed by a known method, for example, a CVD method using a silane gas.

In the present invention, a polysilicon layer, a gate insulating film and a lower gate electrode are sequentially formed on an insulating substrate, and then these three layer structures are simultaneously etched using the same resist pattern to form an island shape. Form in a pattern. The etching in this case can be performed by a known method, but it is preferable to perform patterning by anisotropic etching so that the cross-sectional shape of each layer after etching becomes perpendicular to the substrate. Moreover, sidewalls of an insulator are formed on the sidewalls of the patterned three-layer structure. This sidewall is formed of a known insulating film, for example, a SiO ₂ film for 3000.
It can be formed by a known method such as stacking up to about 8000 Å and anisotropic etching.

Further, in the present invention, only the lower layer gate electrode is processed into a predetermined shape, and the upper layer gate electrode is formed and processed on the lower layer gate electrode, and then the lower layer and the upper layer gate electrodes are used as a mask for impurity ions. Is implanted into the polysilicon layer to form an impurity diffusion region.

[0018]

In the above structure and method, since the gate electrode has a two-layer structure of the upper layer gate electrode and the lower layer gate electrode, and the electrode width of the upper layer gate electrode and the electrode width of the lower layer gate electrode are not the same width. The gate overlap LDD structure is easily formed by implanting impurity ions using the upper and lower gate electrodes as a mask.

Further, since the polysilicon layer serving as the active layer of the transistor, the gate insulating film and the lower gate electrode are successively formed, the interface between the polysilicon layer and the gate insulating film is always stable and in good condition. To be kept. Further, since the upper surface of the laminated film of the polysilicon layer, the gate insulating film and the lower gate electrode is the lower gate electrode material, the etching process for forming the insulator on the sidewall of the patterned laminated film of the three-layer structure is performed. At this time, it can be easily formed without requiring selective etching with the gate insulating film.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a thin film transistor according to the present invention will be described with reference to the drawings. Example 1 FIG. 1 shows an example of a thin film transistor,
(A) is a plan view, (b) is a sectional view taken along the line AA, and (c) is B.
It is a -B line sectional view. This thin film transistor includes a SiN film 2, a polysilicon layer 3 and a SiO ₂ film on a glass substrate 1.
The films 4 are sequentially laminated, the lower gate electrode 5 is formed on the SiO ₂ film 4, and the upper gate electrode 7 having a width smaller than the width of the lower gate electrode 5 is formed on the lower gate electrode 5. Has been formed. Then, an impurity diffusion region 10 having an LDD structure is formed in a self-aligned manner in the polysilicon layer 3 serving as a channel portion, and the metal electrode wiring 9 is connected to the impurity diffusion region 10 to form a thin film transistor. .

A method of manufacturing the above thin film transistor will be described below with reference to the drawings. First, as shown in FIG. 2, a SiN film 2 is deposited on the glass substrate 1 to prevent the diffusion of impurities from the glass by about 3000 Å, and then an amorphous silicon film is formed thereon by a plasma CVD apparatus. To film. The film forming conditions are as follows: SiH ₄ gas diluted with H ₂ at a substrate temperature of 400 to 600 ° C. is decomposed by heat and plasma to obtain about 100
Deposit 0Å. Next, in order to polycrystallize the amorphous silicon film, annealing is performed in vacuum at about 600 ° C. for 1 hour to form a polysilicon film 3. Subsequently, a SiO ₂ film 4 serving as a gate insulating film is formed by a low pressure CVD apparatus to a thickness of about 1000Å. In the above steps from the formation of the amorphous silicon film to the formation of the gate insulating film, the movement of the glass substrate 1 from the plasma CVD apparatus to the annealing furnace and from the annealing furnace to the low pressure CVD apparatus is performed by a load held in vacuum. It goes through the lock room. Then, a polysilicon film to be the lower gate electrode 5 is formed by a low pressure CVD apparatus to a thickness of about 1500 Å.

Then, as shown in FIG. 3, three layers of the polysilicon layer 3, the SiO ₂ film 4 and the lower gate electrode 5 on the silicon nitride film 2 are etched with the same resist pattern to form an island pattern. To process. Reactive ion etching is used for etching each layer, and anisotropic etching is performed so that the cross-sectional shape after etching is perpendicular to the glass substrate 1. For the etching of the polysilicon layer 3, a mixed gas of SF ₆ and CCl ₄ is used as SiO ₂
CHF ₃ was used as an etching gas for etching the film 4.

Next, as shown in FIG. 4, the glass substrate 1
A SiO ₂ film 6 is formed on the entire surface by a sputtering device to a thickness of about 5000Å. After that, CHF _{3 with} reactive ion etcher
Is used as a reactive gas, as shown in FIG.
₂ Anisotropic etching is performed so that the film 6 remains only on the sidewalls of the island pattern. The end point of the etching can be detected by knowing that the silicon nitride film 2 is exposed by the progress of the etching by plasma analysis.

Thereafter, as shown in FIG. 6, the lower gate electrode 5 is processed into a predetermined shape by a reactive ion etcher. At this time, the electrode width of the lower gate electrode 5 (see FIG.
In (b), the transistor length: L) was set to 5 μm. After that, as shown in FIG. 7, the upper gate electrode 7 is formed on the entire surface of the glass substrate 1 including the lower gate electrode 5 by a low pressure CVD apparatus.
Then, a polysilicon film to be used as a film is formed by about 1500 Å.

Next, as shown in FIG. 8, the electrode width of the upper gate electrode 7 (transistor length: M in FIG. 8B) is set to 3 with the center line of the electrode width of the lower gate electrode 5 being the same.
Process to μm. Next, as shown in FIG. 9, PH ₃ diluted with hydrogen gas was used in a plasma ion doping apparatus.
Plasma is formed using gas and P (phosphorus) ions are implanted to form a high concentration region in the gate electrode 6 and an impurity diffusion region 10 having an LDD structure in the polysilicon film.

After that, as shown in FIG. 10, a SiO ₂ film 11 to be an interlayer insulating film is formed to a thickness of about 5000 Å, a contact hole is formed in a portion to be an impurity diffusion region 10, and then a metal wiring 9 is formed. To produce an N-type thin film transistor. The P ion concentration distribution of the thin film transistor thus manufactured is shown in FIG. As shown in FIG. 11, the impurity diffusion region 1 in which the gate electrode 6 does not exist immediately above
In the portion of the polysilicon layer 3 which becomes 0, P of sufficient concentration is formed.
Ions are implanted to form an n ⁺ region. On the other hand, the polysilicon layer 3 in which only the lower gate electrode 5 exists immediately above
Is doped with P ions in an amount that is about two orders of magnitude smaller than that in the high-concentration impurity diffusion region 10 to become an n ⁻ region. In addition, almost no P ions reached the polysilicon layer 3 where both the upper gate electrode 7 and the lower gate electrode 5 exist immediately above.

Therefore, in this thin film transistor, the upper layer gate electrode 7 and the lower layer gate electrode 5 have the same electrode width of 3 μm.
As compared with the thin film transistor in the case of, the off current could be reduced by about 2 digits. Further, the driving capability of the drain current when turned on was about the same. Example 2 By the same method as in Example 1, a three-layer film of a polysilicon layer 3 to be an active layer, a SiO ₂ film 4 to be a gate insulating film and a polysilicon film to be a lower gate electrode 15 is processed into an island pattern. Then, the insulator of the SiO ₂ film 6 is formed on the side wall of the island pattern. In Example 2, after processing the electrode width (L) of the lower layer gate electrode 15 to 3 μm, a polysilicon film to be the upper layer gate electrode 17 was formed and the center line of the electrode width of the lower layer gate electrode 15 was made the same. The electrode width (M) of the upper gate electrode 17 is processed to 5 μm. Then, the thin film transistor shown in FIG. 12 was manufactured in the same manner as in Example 1.

The off-current of the thin film transistor thus manufactured was also reduced by about two digits, which is the same as in Example 1. Since the gate overlap LDD is realized by performing ion implantation after forming the upper layer gate electrode and the lower layer gate electrode with different electrode widths as in the first and second embodiments, It was possible to reduce the off-current without impairing the current driving capability.

[0029]

As described above, in the thin film transistor and the method of manufacturing the same according to the present invention, the gate electrode has a two-layer structure of the upper layer gate electrode and the lower layer gate electrode, and the electrode width of the upper layer gate electrode and the electrode of the lower layer gate electrode. Since the width is not the same as the width, the gate overlap LDD structure can be easily formed by implanting impurity ions once using the upper and lower layer gate electrodes as a mask. Therefore,
It was possible to realize a reduction in off-current without impairing the drive capability of the ion current.

Further, since the polysilicon layer serving as the active layer of the transistor, the gate insulating film, and the lower gate electrode are successively formed, the interface between the polysilicon layer and the gate insulating film is always stable and in a good state. Thus, a thin film transistor can be manufactured. Therefore, high-performance transistor characteristics can be stably obtained even in a low temperature process of 600 ° C. or lower.

Further, since the upper surface of the laminated film of the polysilicon layer, the gate insulating film and the lower layer gate electrode is the lower layer gate electrode material, in order to form an insulator on the side wall of the patterned laminated film of the three-layer structure. In the etching process, the selective manufacturing of the gate insulating film is not particularly required, and the manufacturing process of the thin film transistor can be simplified.

[Brief description of drawings]

FIG. 1 is a schematic plan view and a schematic cross-sectional view of a main part showing an embodiment of a thin film transistor according to the present invention.

2A and 2B are schematic cross-sectional views of a main part showing a manufacturing process of Example 1, where FIG. 2A is a cross-sectional view taken along the line AA of FIG. 1 and FIG. .

3A and 3B are schematic cross-sectional views of a main part showing a manufacturing process of Example 1, where FIG. 3A is a cross-sectional view taken along the line AA of FIG. 1 and FIG. 3B is a cross-sectional view taken along the line BB of FIG. .

4A and 4B are schematic cross-sectional views of a main part showing the manufacturing process of Example 1, where FIG. 4A is a cross-sectional view taken along the line AA of FIG. 1 and FIG. .

5A and 5B are schematic cross-sectional views of a main part showing a manufacturing process of Example 1, where FIG. 5A is a cross-sectional view taken along the line AA of FIG. 1 and FIG. 5B is a cross-sectional view taken along the line BB of FIG. .

6A and 6B are schematic cross-sectional views of a main part showing the manufacturing process of Example 1, where FIG. 6A is a cross-sectional view taken along the line AA of FIG. 1, and FIG. 6B is a cross-sectional view taken along the line BB of FIG. .

7A and 7B are schematic cross-sectional views of a main part showing the manufacturing process of Example 1, where FIG. 7A is a cross-sectional view taken along the line AA of FIG. 1 and FIG. .

8A and 8B are schematic cross-sectional views of a main part showing the manufacturing process of Example 1, where FIG. 8A is a cross-sectional view taken along the line AA of FIG. 1 and FIG. .

9A and 9B are schematic cross-sectional views of a main part showing the manufacturing process of Example 1, where FIG. 9A is a cross-sectional view taken along the line AA of FIG. 1, and FIG. 9B is a cross-sectional view taken along the line BB of FIG. .

10A and 10B are schematic cross-sectional views of a main part showing the manufacturing process of Example 1, where FIG. 10A is a cross-sectional view taken along the line AA of FIG. 1 and FIG.
FIG. 6 is a sectional view taken along line BB of FIG.

FIG. 11 is a diagram showing a P ion concentration distribution after P ion implantation in the thin film transistor in Example 1.

12A and 12B are a schematic plan view and a schematic sectional view of a main part showing another embodiment of the thin film transistor according to the present invention.

FIG. 13 is a schematic cross-sectional view for explaining a method of manufacturing a thin film transistor having a conventional LDD (Lightly Doped Drain) structure.

FIG. 14 is a schematic cross-sectional view for explaining a method of manufacturing a conventional thin film transistor having a gate overlap LDD structure.

[Explanation of symbols]

1 glass substrate (insulating substrate) 3 polysilicon layer 4 SiO ₂ film (gate insulating film) 5 lower layer gate electrode 6 SiO ₂ film (insulator) 7 upper layer gate electrode 8 gate electrode 10 impurity diffusion region

Claims (2)

[Claims] 1. A thin film transistor in which a polysilicon layer serving as an active layer of a transistor, a gate insulating film, and a gate electrode are sequentially formed on an insulating substrate, and the gate electrode is a two-layer structure including an upper gate electrode and a lower gate electrode. A thin film transistor having a structure, wherein the electrode width of the upper gate electrode and the electrode width of the lower gate electrode are not the same. 2. (i) a step of forming a laminated film by successively and continuously forming a polysilicon layer, a gate insulating film and a lower gate electrode on an insulating substrate, (ii) forming the laminated film in an island pattern And then forming an insulator on the side wall of the island pattern, (iii) processing only the lower layer gate electrode into a predetermined shape,
Further, a step of forming an upper layer gate electrode on the lower layer gate electrode, (iv) a step of processing the upper layer gate electrode into a predetermined shape, (v) an impurity using the lower layer gate electrode and the upper layer gate electrode as a mask The method of manufacturing a thin film transistor according to claim 1, further comprising the step of implanting ions into the polysilicon layer to form an impurity diffusion region.