JPH08330599A - Thin film transistor, its manufacture and display - Google Patents

Abstract

PURPOSE: To provide a thin film transistor which can avoid the deterioration of subthreshold characteristics of a thin film transistor, while disconnection of a gate electrode is prevented, by tapering the edge part of a semiconductor thin film which turns to a channel layer. CONSTITUTION: In this thin film transistor, a channel part 1a, a source part 1b and a drain part 1c are formed in a poly-Si film 1 on an insulating substrate 9, and a gate electrode 3 is formed on the channel part 1a via a gate insulating film 2. An insulating slant part is formed on the edge part of at least the channel part la of the poly-Si film 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor, a method of manufacturing the thin film transistor, and a thin film transistor and a display device using the thin film transistor.

[0002]

2. Description of the Related Art FIG. 10 is a perspective view showing one of conventional thin film transistor groups forming a circuit for driving an active matrix liquid crystal display or the like.
1 is a sectional view taken along the line AA of FIG. 10, and FIG. 12 is a line B- of FIG.
FIG. 11 and 12 show the insulating substrate 2
9 and the passivation film 24 are added.

Reference numeral 21 in the figure denotes a polycrystalline silicon film (hereinafter referred to as a poly-Si film) formed on an island for insulation between elements on an insulating substrate 29.
The y-Si21 film is an amorphous silicon film (hereinafter a-Si).
A film) is deposited on the insulating substrate 29 and patterned or before laser patterning is performed.

Channel 2 of the poly-Si film 21
SiO is formed on the region to be 1a. ₂Membrane gate
An insulating film 22 is formed, and a gate is formed on the gate insulating film 22.
The second electrode 23 is formed. These gate insulating films 22
The gate electrode 23 is, for example, the poly-Si film.
SiO to be the gate insulating film 22 on 21₂Membrane and game
After forming the poly-Si film to be the
A resist film is applied on the poly-Si film and not shown
Resist exposure through a mask and development process
Leave the resist film at the position corresponding to the channel area
However, the poly other than the part where the resist film is left
-Si film and SiO₂After etching the film,
It is obtained by removing the strike film.

A source region 21b and a drain region 21c are formed on both sides of the channel 21a of the poly-Si film 1. The source region 21b, the drain region 21c, and the gate electrode 23 are formed by performing impurity doping on the poly-Si film forming them. A passivation film 24 is formed on the glass substrate so as to cover the gate electrode 23, and the passivation film 24 is formed through contact holes formed in the passivation film 24 on the source region 21b and the drain region 21c. The source electrode 25 and the drain electrode 26 deposited on the film 24 are the source region 21 b and the drain region 21.
c are contacted respectively.

[0006]

In the above-mentioned thin film transistor, the poly-Si film 21 is formed to have a film thickness of 50 to 100 nm. The poly-Si film 21 is formed on the poly-Si film 21 via the gate insulating film 22. Gate electrode 23
On the edge portion of the poly-Si film 21 becomes thin due to the step.

The gate electrode 23 is, as described above,
It is formed by a poly-Si film that has good heat resistance and a simple formation process. A laser activation method is promising for sufficiently reducing the resistance of this poly-Si film by a low-temperature and short-time process. is there. In this case, in order to fully activate the poly-Si film up to the boundary surface with the gate insulating film 22, it is desirable that the thickness of the poly-Si film be 100 nm or less.

However, when the poly-Si film which becomes the gate electrode 23 is formed thin, the gate electrode 23 becomes thin on the edge portion of the poly-Si film 21 as described above, so that the disconnection occurs at that portion. It is easy to occur.
On the other hand, in order to avoid this disconnection, the poly-Si
The edge of the channel of the membrane 1 is tapered (inclined)
It is thought that it is formed in. However, a thin film transistor using a channel layer processed into a taper shape has a drawback that a subthreshold characteristic is poor as compared with a thin film transistor which is not subjected to taper processing.

FIG. 13 shows drain currents of a thin film transistor (B in the drawing) having a tapered edge portion and a thin film transistor (A in the drawing) having no tapered processing.
It is a gate voltage characteristic diagram. As you can see from this figure,
It can be seen that the characteristics of the tapered thin film transistor are deteriorated. Both thin film transistors are n-channel type, and the channel part is W / L
= 10/10 (μm).

In view of the above circumstances, the present invention provides a thin film transistor capable of avoiding the deterioration of the subthreshold characteristic of the thin film transistor while tapering the edge portion of the semiconductor thin film serving as a channel to prevent disconnection of the gate electrode. To aim.

[0011]

In order to solve the above-mentioned problems, a thin film transistor of the present invention has a channel portion, a source portion and a drain portion formed in a semiconductor thin film formed on an insulating substrate, and the channel portion is formed. In a thin film transistor formed by forming a gate electrode on an insulating film, an insulating sloping portion or a high resistance sloping portion is formed at least at an edge portion of a channel portion of the semiconductor thin film.

In the above structure, the semiconductor thin film may be made of a polycrystalline semiconductor film, and the high resistance gradient portion may be made of an amorphous semiconductor film. Further, the method of manufacturing a thin film transistor of the present invention comprises a step of forming a semiconductor thin film which becomes a channel part, a source part and a drain part on an insulating substrate, and an inclined part at least at an edge part of the channel part of the semiconductor thin film. The method is characterized by including a step of forming and a step of insulating or increasing the resistance of the inclined portion.

In the above manufacturing method, a polycrystalline semiconductor film may be formed as the semiconductor thin film, and the sloped portion may be made amorphous as a process for increasing the resistance of the sloped portion. The display device of the present invention is characterized in that the thin film transistor is used as a pixel driving element.

Furthermore, the display device of the present invention is characterized in that a thin film transistor formed by the method for manufacturing a polycrystalline semiconductor film is used as a pixel driving element.
According to the above thin film transistor, since the insulating slanted portion or the high resistance slanted portion is formed at least at the edge portion of the channel portion of the semiconductor thin film, the inclination of the slanted portion prevents disconnection of the gate electrode, and It is possible to avoid the deterioration of the threshold rise due to the insulating property or the high resistance of the inclined portion.

According to the method of manufacturing a thin film transistor, the thin film transistor having the above structure can be easily manufactured, and a thin film transistor having excellent characteristics can be obtained. Furthermore, by using the thin film transistor as an image display element, it is possible to obtain a display device that provides good display.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below with reference to the drawings showing its embodiments. 1 is a cross-sectional view showing a thin film transistor of the present invention, and FIG. 2 is a view taken along the line AA of FIG. Reference numeral 1 in the drawing denotes a polycrystalline silicon film (hereinafter, referred to as a poly-Si film) formed in an island shape on the insulating substrate 9 for insulation between elements. This poly-
Si is formed on the region to be the channel 1a of the Si film 1.
A gate insulating film 2 made of an O ₂ film is formed, and a gate electrode 3 is formed on the gate insulating film 2. A source region 1b and a drain region 1c are formed on both sides of the channel region 1a of the poly-Si film 1.

A passivation film 4 is formed so as to cover the gate electrode 3 and the like, and is deposited on the passivation film 4 through the contact holes formed in the passivation film 4 on the source region 1b and the drain region 1c. The formed source electrode 5 and drain electrode 6 are in contact with the source region 1b and the drain region 1c, respectively.

Then, 30 to 70 are formed on the entire peripheral edge portion of the above-mentioned island-shaped poly-Si film 1.
The insulating sloped portion 10 is formed so as to be inclined downward at an angle of °. With such a configuration, poly-
Since the insulating sloped portion 10 is formed at the edge portion of the Si film 1, the inclination of the sloped portion 10 prevents the disconnection of the gate electrode 3, and the insulation of the sloped portion 10 lowers the threshold characteristic. Can be avoided. That is, the characteristics shown by the graph A in FIG. 13 described in the description of the conventional example are almost maintained.

Next, a method for manufacturing the above thin film transistor will be described.
This will be described with reference to FIG. In addition, FIG. 3 shows AA of FIG.
It corresponds to the view seen from the direction of the arrow. First, as shown in FIG.
As shown in FIG.
An amorphous silicon film (hereinafter referred to as an a-Si film) by a VD method.
1) is formed to a thickness of 500Å. And A
rF excimer laser 300-400 mJ / cm ²Strength of
By irradiating the a-Si film 1 ',
-Si film 1'is recrystallized to obtain poly-Si film 1.
It And to make islands for element-to-element insulation,
Area somewhat larger than the area where the poly-Si film should be left
Then, a resist film 11 is formed.

Next, as shown in FIG. 3B, the resist film 11 and the poly-Si film 1 are isotropically etched at the same etching rate. As a result, the poly-Si film 1 having the inclined portion 10 'at the edge portion of the entire circumference is obtained. By adjusting the etching rate, the inclination angle of the inclined portion 10 'can be adjusted. In etching, SF ₆ + O ₂ is used as an etching gas in dry etching, and in the case of wet etching, an HF / HNO ₃ based etchant is used.

Next, as shown in FIG. 3C, with the resist film 11 left, oxygen ions are injected from above the insulating substrate 9 with a dose amount of 5 × 10 ¹⁶ cm ^-2 and an implantation strength of Three
It is injected into the inclined portion 10 'under the condition of 0 keV. As a result, the oxygen concentration of the inclined portion 10 ′ increases, the portion is insulated, and the insulating inclined portion 10 is formed. After that,
Using a known technique, as shown in FIG. 2 (d), after removing the resist film 11, SiO ₂ film 2 serving as a gate insulating film 2 'after the forming by sputtering or the like, the SiO ₂ film 2' A poly-Si film 3 ′ is formed on the top of the film to a thickness of 1000 Å. Then, these SiO ₂ film 2'and poly
Patterning the -Si film 3 ', and using this as a mask, the poly-Si film 3'and the poly-Si film 1
Then, phosphorus (P ⁺ ) or boron (B ⁺ ) is ion-implanted into
Activate. As a result, the source region 1b and the drain region 1c are formed in the poly-Si film 1,
The gate electrode 3 is formed by the y-Si film 3 '.

Further, the passivation film 4 made of a SiO ₂ film or the like is formed by the APCVD (normal pressure CVD) method. Then, the source region 1b and the drain region 1c
After forming a contact hole in the passivation film 4 above, Al or the like is deposited on the passivation film 4 to form a source electrode 5 and a drain electrode 6 in contact with the source region 1b and the drain region 1c through the contact hole.

With the above manufacturing method, poly-Si
The formation of the inclined portion 10 ′ in the film 1 can be performed when forming an island for inter-element insulation, and the step of insulating the inclined portion 10 ′ into the insulating inclined portion 10 is a resist film for island formation. Since it is possible to perform the oxygen ion implantation with 11 left, only the oxygen ion implantation step is added as a step. Therefore, the thin film transistor including the insulating sloped portion 10 relatively easily increases the cost. Can be formed without.

In the above embodiment, the insulating sloped portion 10 was formed by implanting oxygen ions into the sloped portion 10 '.
It is not limited to this, for example, implantation of nitrogen ions,
It can also be performed by laser doping treatment in an oxygen or nitrogen atmosphere, plasma treatment, or the like. This insulation treatment can also be applied to a thin film transistor having an a-Si film instead of the poly-Si film 1.

Further, by irradiating a laser, for example, with a laser to the inclined portion 10 ′ made of the poly-Si film 1, a high resistance high resistance inclined portion which is not insulation is formed. Good. Even in such a case, the threshold characteristic equivalent to that of the above-mentioned embodiment can be obtained. When the high resistance slope portion is formed of the amorphous semiconductor film as described above, the a-Si film 1 ′ formed on the substrate is recrystallized except for the high resistance slope portion. It is possible to use a method including a step of converting into a compound.

Further, in the above description, the insulating slanted portion is formed on the semiconductor thin film, but the invention is not limited to this, and the insulating slanting portion is made of an insulating material such as a SiO ₂ film in addition to the semiconductor thin film. You may make it form a part. To this end, a SiO ₂ film is formed on the channel portion 1a of the island-shaped poly-Si film 1 and anisotropic etching is performed, so to speak, in the manner of a sidewall formation process, an insulating sloped portion is formed at the edge portion. Can also be formed.

The insulating sloped portion or the high resistance sloped portion may be a sloped portion formed in a stepped shape. This step-shaped inclined portion can be formed by sequentially reducing the size of the resist film and repeating the etching. Here, a polycrystalline silicon TFT manufactured by the method for manufacturing a polycrystalline silicon film of the present application as described above, and a transmissive LCD using the TFT as a pixel driving element
A method of manufacturing a pixel portion of (Liquid Crystal Display) will be described with reference to the drawings.

FIG. 4 is a specific plan structure view of the periphery of the pixel portion, and FIGS. 5 and 6 are cross-sectional structure views taken along the section line A--A in FIG. The pixel portion is composed of a TFT as a driving element, a liquid crystal cell and a storage capacitor CS. The gate G of the TFT is connected to the gate line Gm,
The drain D of the TFT is connected to the drain wiring Dn. The display electrode of the liquid crystal cell and the auxiliary capacitance electrode CS are connected to the source S of the TFT. The liquid crystal cell and the storage capacitor form a signal storage element.

As shown in FIG. 5A, the insulating film 3 is formed on the entire surface.
1 is formed on the substrate 30 by the manufacturing method of the present application.
Polycrystalline silicon film 32 having an inclined portion which becomes an active layer of
To form. Further, as shown in FIG. 5B, atmospheric pressure CVD (AP-CVD) is performed on the polycrystalline silicon film 32.
Method, low pressure CVD (LP-CVD) method or the like, and a polycrystalline silicon film 34 is formed thereon by using a thermal CVD method.

Thereafter, as shown in FIG. 5C, a resist 35 is patterned on the polycrystalline silicon film 34, and the polycrystalline silicon film is etched to form a gate electrode 36.
To form. The gate electrode 36 may be formed of metal such as aluminum or chromium by vapor deposition or sputtering. Further, as a method of forming the gate insulating film 33, an atmospheric pressure CVD (AP-CVD) method, a low pressure CVD (LP-CVD) method, or the like is used. As a material of the gate insulating film, a silicon oxide film, a silicate glass, a silicon nitride film or the like is used.

Then, as shown in FIG. 5D, patterning 37 is performed on the gate insulating film 33, and an opening 38 is formed in the gate insulating film by anisotropic etching. Is doped 39 with an n-type impurity such as phosphorus. Furthermore, as shown in FIG.
An n-type drain region 40 and a source region 41 are formed in the polycrystalline silicon film. At the same time, the gate electrode is also doped with an n-type impurity such as phosphorus. As a result, the resistance of the gate electrode 36 can be reduced.

As shown in FIG. 6F, indium tin oxide (ITO) is formed on the pixel region of the substrate.
e) The auxiliary capacitance electrode 42 made of ITO or the like is formed.
Further, a gate wiring 43 made of a metal such as molybdenum, a metal silicide, or a polycrystalline silicon film is formed on the gate electrode by a sputtering method.

Further, as shown in FIG. 6G, an interlayer insulating film 44 made of silicon nitride or the like is formed on the entire surface of the substrate. Then, the interlayer insulating film 44 is partially removed by etching, and a contact hole 45 is formed above the drain region 40 and the source region 41. Then, IT is formed on the interlayer insulating film located in the pixel portion by a sputtering method.
A display electrode 46 made of O is formed. A part of the display electrode 46 is electrically connected to the source region 41 through the contact hole 45. Further, a conductive material is formed on the entire surface and then patterned to form a drain electrode 47 and a source electrode 48 which are connected to the drain region 40 and the source region 41, respectively.

Through the above steps, a TFT having a polycrystalline silicon film as an active layer is completed. By the way, as shown in FIG. 7, a pixel portion of an LCD using the above-mentioned TFT as a pixel driving element has a transparent insulating substrate 40 on which a polycrystalline silicon TFT is formed and a transparent insulating substrate on which a common electrode 42 is formed. 41 is made to face each other, and liquid crystal is enclosed between each substrate to form a liquid crystal layer 43, which is completed.

FIG. 8 shows an active matrix type LCD block configuration of the present embodiment. Each scanning line (gate wiring) G1 ... Gn, Gn + 1 ... Gm and each data line (drain wiring) D1 ... Dn, Dn + 1 ... Dm are arranged in the pixel section 50. ing. The gate lines and the drain lines are orthogonal to each other, and the pixels 51 are provided in the orthogonal portions.
Then, each gate wiring is connected to the gate driver 52, and a gate signal (scanning signal) is applied. Further, each drain wiring is connected to a drain driver (data driver) 53 so that a data signal (video signal) is applied. The peripheral drive circuit 54 is configured by these drivers. And
At least one of the drivers is provided in the pixel unit 50.
An LCD formed on the same substrate as is generally called a driver integrated type (driver built-in type) LCD. The gate driver 52 may be provided on both sides of the pixel section 50. Further, the drain driver 53 may be provided on both sides of the pixel section 50.

FIG. 9 shows an equivalent circuit of a pixel provided in a portion orthogonal to the gate wiring Gn and the drain wiring Dn. The pixel is composed of a TFT as a pixel driving element, a liquid crystal cell LC, and a storage capacitor. The gate of the TFT is connected to the gate wiring Gn, and the drain of the TFT is connected to the drain wiring Dn. And the source of the TFT is
The display electrode (pixel electrode) of the liquid crystal cell LC and the auxiliary capacitance (storage capacitance or additional capacitance) are connected. The liquid crystal cell LC and the storage capacitor form the signal storage element. The voltage Vcom is applied to the common electrode of the liquid crystal cell LC (the electrode on the opposite side of the auxiliary capacitance electrode). On the other hand, in the auxiliary capacitor, a constant voltage VR is applied to the electrode opposite to the electrode connected to the source of the TFT. The common electrode of the liquid crystal cell LC is literally a common electrode for all pixels. An electrostatic capacitance is formed between the display electrode and the common electrode of the liquid crystal cell LC. In the auxiliary capacitor, the electrode on the side opposite to the electrode on the side connected to the source of the TFT may be connected to the adjacent gate wiring Gn + 1.

In the pixel thus constructed, when the gate wiring Gn is set to a positive voltage and a positive voltage is applied to the gate of the TFT, the TFT is turned on. Then, the data signal applied to the drain wiring Dn charges the electrostatic capacitance and the auxiliary capacitance of the liquid crystal cell LC. On the contrary, the gate wiring Gn
When a negative voltage is applied to the gate of the TFT,
The TFT is turned off, and the voltage applied to the drain wiring Dn at that time is held by the electrostatic capacity and the auxiliary capacity of the liquid crystal cell LC. In this way, by supplying a data signal to be written to the pixel to the drain wiring Dn and controlling the voltage of the gate wiring Gn, the pixel can hold an arbitrary data signal. The transmittance of the liquid crystal cell LC changes according to the data signal held by the pixel, and an image is displayed.

[0038]

As described above, according to the present invention, disconnection of the gate electrode is prevented by the inclination of the insulating sloping portion or the high resistance sloping portion, and at the same time, the threshold rise due to the insulation or high resistance of the sloping portion. Of deterioration is avoided.
Further, there is an effect that the thin film transistor having this configuration can be easily manufactured.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a thin film transistor of the present invention.

FIG. 2 is a sectional view taken along the line AA of FIG.

FIG. 3 is a cross-sectional view showing a manufacturing process of the thin film transistor of the present invention.

FIG. 4 is a specific plan structure diagram around a pixel portion.

5 is a cross-sectional view taken along the line AA of FIG.

6 is a sectional view taken along the line BB of FIG.

FIG. 7 is a cross-sectional view of a pixel portion of an LCD using a TFT as a pixel driving element.

FIG. 8 is an active matrix type LC according to the present embodiment.
It is a D block block diagram.

FIG. 9 is an equivalent circuit diagram of a pixel provided in a portion orthogonal to a gate line Gn and a drain line Dn.

FIG. 10 is a perspective view showing one of conventional thin film transistor groups forming a circuit for driving an active matrix liquid crystal display or the like.

11 is a sectional view taken along the line AA of FIG.

12 is a sectional view taken along the line BB of FIG.

FIG. 13 is a drain current-gate voltage characteristic diagram of a thin film transistor whose edge portion is tapered and a thin film transistor which is not tapered.

[Explanation of symbols]

 1 poly-Si film 1a channel part 1b source part 1c drain part 2 gate insulating film 3 gate electrode 4 passivation film 10 insulating gradient part

Claims (6)

[Claims] 1. A thin film transistor comprising a semiconductor thin film formed on an insulating substrate, a channel portion, a source portion, and a drain portion, and a gate electrode formed on the channel portion via an insulating film. A thin film transistor having an insulating sloping portion or a high resistance sloping portion formed on at least an edge portion of a channel portion of the thin film. 2. The thin film transistor according to claim 1, wherein the semiconductor thin film is made of a polycrystalline semiconductor film, and the high resistance slope portion is made of an amorphous semiconductor film. 3. A step of forming a semiconductor thin film to be a channel part, a source part, and a drain part on an insulating substrate; a step of forming an inclined part at least at an edge part of the channel part of the semiconductor thin film; A step of insulating or increasing the resistance of the inclined portion. 4. The method of manufacturing a thin film transistor according to claim 3, wherein a polycrystalline semiconductor film is formed as the semiconductor thin film, and the inclined portion is made amorphous as a treatment for increasing the resistance of the inclined portion. 5. A display device using the thin film transistor according to claim 1 as a pixel driving element. 6. A display device using a thin film transistor formed by the method for producing a polycrystalline semiconductor film according to claim 3 or 4 as a pixel driving element.