JPS5553454A - Method for producing semiconductor device - Google Patents

Method for producing semiconductor device

Info

Publication number
JPS5553454A
JPS5553454A JP12708178A JP12708178A JPS5553454A JP S5553454 A JPS5553454 A JP S5553454A JP 12708178 A JP12708178 A JP 12708178A JP 12708178 A JP12708178 A JP 12708178A JP S5553454 A JPS5553454 A JP S5553454A
Authority
JP
Japan
Prior art keywords
sio2
pattern
type
electrodes
memory data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12708178A
Other languages
Japanese (ja)
Inventor
Izumi Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP12708178A priority Critical patent/JPS5553454A/en
Publication of JPS5553454A publication Critical patent/JPS5553454A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)

Abstract

PURPOSE:To shorten the manufacturing period and improve integration degree by forming memory data pattern during the process close to the completion. CONSTITUTION:Poly Si gate electrodes 11 are formed on p-type Si 10 and as masking the electrodes 11 and SiO2 12, sources 13 and drains 14 are formed. Then it is coated by SiO2 15 to form a pattern 16 of Si3N4 and oxidized under high humidity to form a SiO2 17 around the gate electrodes. Then the pattern 16 and SiO2 15 are removed by etching and a resist mask 18 for memory data pattern is formed and P-type ion is injected. The injection is made by applying high energy and impurity injected into channel even through poly Si electrodes. Accordingly the potential value is high and the element changes from depression type to enhancement type. The resist is removed and electrode window is formed and wiring is made to form a desired memory data pattern. Thus, non-necessitated memory element is used as high potential value and a drain electrode can be formed against two memory elements to allow design of highly integratable pattern.
JP12708178A 1978-10-16 1978-10-16 Method for producing semiconductor device Pending JPS5553454A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12708178A JPS5553454A (en) 1978-10-16 1978-10-16 Method for producing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12708178A JPS5553454A (en) 1978-10-16 1978-10-16 Method for producing semiconductor device

Publications (1)

Publication Number Publication Date
JPS5553454A true JPS5553454A (en) 1980-04-18

Family

ID=14951094

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12708178A Pending JPS5553454A (en) 1978-10-16 1978-10-16 Method for producing semiconductor device

Country Status (1)

Country Link
JP (1) JPS5553454A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56150860A (en) * 1980-04-24 1981-11-21 Fujitsu Ltd Manufacture of semiconductor memory device
JPS584969A (en) * 1981-06-30 1983-01-12 Fujitsu Ltd Semiconductor device
JPS5821369A (en) * 1981-07-30 1983-02-08 Toshiba Corp Fixed memory storage
JPS5870567A (en) * 1981-10-22 1983-04-27 Nippon Denso Co Ltd Manufacture of semiconductor device
JPH0274044A (en) * 1988-09-09 1990-03-14 Nec Kyushu Ltd Manufacture of mos transistor
JPH0338840A (en) * 1989-07-05 1991-02-19 Nec Corp Manufacture of vertical-type mos field-effect transistor

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56150860A (en) * 1980-04-24 1981-11-21 Fujitsu Ltd Manufacture of semiconductor memory device
JPS584969A (en) * 1981-06-30 1983-01-12 Fujitsu Ltd Semiconductor device
JPH0328072B2 (en) * 1981-06-30 1991-04-17 Fujitsu Ltd
JPS5821369A (en) * 1981-07-30 1983-02-08 Toshiba Corp Fixed memory storage
JPS5870567A (en) * 1981-10-22 1983-04-27 Nippon Denso Co Ltd Manufacture of semiconductor device
JPH0328833B2 (en) * 1981-10-22 1991-04-22 Nippon Denso Co
JPH0274044A (en) * 1988-09-09 1990-03-14 Nec Kyushu Ltd Manufacture of mos transistor
JPH0338840A (en) * 1989-07-05 1991-02-19 Nec Corp Manufacture of vertical-type mos field-effect transistor

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