JPS5870567A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To remarkably shorten a delivery term by a method wherein the threshold voltage is adjusted by an ion implantation after the formation of gate metallic patterns, and a mask programmable ROM (eye of ROM) is formed in the latter stage of the manufacture process. CONSTITUTION:A P type si substrate is isolated with a channel stopper and a field oxide film. and a doped poly Si gate 8 and an N layer 10 are formed on a gate oxide film 7 and covered with an SiO2 film 9. After an Si3N4 11 and a PSG15 are superposed, and the PSG is opened 15 and allowed to reflow, electrode windows 16 are formed. Next, a resist mask 17 is applied, and an enhance type MOS is converted into a depletion type by a P ion implantation resulting in the formation of the eye 18 of the PROM14. The resist 17 is removed, and an Al wiring containing Si is provided and protected with an Si3N420. Since the threshold voltage is varied by an ion implantation through the poly Si gate pattern in this manner, a special area for the eye of the ROM is un- necessitated resulting in a high integration, and the writing into the eye of the ROM can be performed in the latter process. Therefore, the delivery term of a device can be extremely shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor devices, especially! Scup Four Grammaple ROM
The present invention relates to a manufacturing method.

Conventionally, when forming a mask program ROM, the diffusion region formed on the semiconductor substrate and the vapor-deposited metal are generally connected or not, that is, with or without forming a contact hole. However, in recent years, there has been a demand for higher integration density, and the area occupied by the contact elements in the conventional method has increased, creating problems in the direction of higher integration. Furthermore, in recent years, in order to solve the above-mentioned drawbacks in N-channel E/DMO8 integrated circuits, after forming a gate oxide film, impurity ion tube implantation with the same polarity as that of the source and drain is performed, and then a gate metal is formed in the channel region below the gate. , a drain diffusion layer is formed, a contact hole is formed, a wiring metal layer is vapor-deposited, a pattern is formed, and a mask pattern is formed.
Some books even form an OM department. However, in this method, the formation of the mask quadrature maple ROM (hereinafter referred to as "ILOM eye") is performed frequently, and the process of forming the ROM eye is in the early stage of wafer manufacturing, so it takes a long time. There are some drawbacks.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that can solve the above-mentioned drawbacks.

That is, in the present invention, in order to form a highly integrated ROM section, a gate metal pattern is formed, and then charged particles such as phosphorus, boron, etc. are introduced into the ROM through the gate metal by ion implantation. selectively injected to form
This is to change the threshold voltage of the MIa type transistor. Further, according to the present invention, since the ROM eyes are formed at a late stage of wafer manufacturing, semiconductor devices can be provided quickly and highly integrated as described above.

Next, in order to better understand the present invention, a detailed explanation will be given using a manufacturing process of an N-channel MOa type integrated circuit device as an example shown in the drawings.

Figure 1 shows a P-type 6-10Ω single crystal with 3 (100) crystal planes on the surface of a 9/IJ controller substrate 1 with a thickness of goo-10.
A thermal oxide film 8 of 00mm is formed, and an 8i film is formed on the thermal oxide film 8.
3N, a film (silicon nitride film) 8 is formed, and the silicon nitride film 8 is partially removed leaving an active region 4 that is to become a MOS) runister, etc., and a parasitic M is formed in the removed part.
This figure shows how boron is formed by ion implantation as a channel stopper 6 to prevent the inversion of O8. The silicon nitride film 8 not covered with the photoresist was removed by using a photoresist as a mask (!F4-0. system plasma etching) to remove the silicon nitride film 8. The nitride V silicon film 8 acts as an oxidation-resistant mask against thermal oxidation of the silicon substrate l, and allows the field oxide film region 6 to be formed by a so-called selective oxidation method.Then, the silicon nitride film 8 and the thermal oxide film are formed. This field oxide film 6 should have a thickness of about 0.7 to IJμ.

Next, thermal oxidation was performed to form a silicon dioxide film 7 as a gate insulating film having a thickness of 500 to 1000 Å at the opening of the field oxide film 6, that is, at the active region. Next, polycrystalline silicon 8 doped with phosphorus or arsenic at a high concentration was deposited over the entire surface to a thickness of 0.8 to 0.4 μm. In this example, a low pressure CVD method was used. Continued to be MOS)
The gate portion (gate metal pattern) of the Lancistor and the portions that will become the polycrystalline silicon wiring layer are selectively covered with photoresist, for example, CF, +0. Polycrystalline silicon 8 was selectively etched by system plasma etching. Thereafter, a silicon dioxide film 9 having a thickness of 600 to 1000 μm was formed on the surface of the patterned polycrystalline silicon 8 by thermal oxidation. Subsequently, phosphorus or arsenic was implanted by the ion implantation method to form the source, drain IO, etc. of the M08 transistor, as shown in FIG. Note that in this example, the ion implantation was performed while leaving a silicon dioxide film formed as a gate insulating film with a thickness of 600 to 1000 μm on the surface of the region where the source, drain, etc. were to be formed. , the surface of the substrate l in the region where the drain is to be formed may be exposed. Alternatively, the process may be performed without forming the V silicon dioxide film 9 on the surface of the polycrystalline silicon 8.

Next, silicon nitride II on the entire surface! 11 from 8oO to 100
The 0Vp8i0. Membrane (hereinafter referred to as P2O membrane) is
was deposited on the entire surface to a thickness of 0.5 to 1.0 μm. Continued MO
S), Funsista Part 18 and Mask Derogbu Maple R
P in the OM section 14 etc. using photoresist as a mask.
8Gllllxs was partially etched to form an opening 16. After that, with the so-called P8G riff p-technology, 1
Heat treatment was performed at around 000°C to soften the sharp edges of P8011tg. At this time, nitrided V 1 precipitated over the entire surface.
The 3-layer film 11 acts as a stopper during etching of P801i1g. Regarding P8G Lift Sea, for example, when it is oxidized in steam, it acts as an oxidation-resistant mask for the silicon substrate 1 and polycrystalline silicon 8.

In the 8th v!, a contact hole 16 for electrical connection was subsequently formed. Shown in J.

Next, in order to form ROM eyes in the four-grammar ROM portion of the mask, ROM eye ribs were formed using a photoresist film. Using this photoresist film 17 as a mask, phosphorus, for example, was selectively implanted through the polycrystalline silicon 8 by ion implantation. After removing the photoresist, heat treatment was subsequently performed in an atmosphere of 400 to 900 tl:,N.

In this embodiment, impurities having the same polarity as the source and drain are implanted, and the enhancement type MO8) mask is changed to the depletion type to form the ROM eye 1B. Although FIG. 1 shows that one ROM eye is formed out of four, it is not necessary to limit the number to this number. Further, the implanted impurity does not need to pass through the polycrystalline silicon entirely, and may only partially pass through the polycrystalline silicon. Further, the impurity may be implanted into the silicon dioxide film 70 portion as a gate insulating film, and furthermore, the impurity may be implanted into the silicon dioxide film 70 portion as a gate insulating film.
It may even extend to the 0 part. Figure @4 shows a state in which the impurity implanted up to the silicon substrate l has passed through.

Subsequently, as the wiring metal layer 19, a 1-B4 silicon-containing aluminum film is deposited to form a desired pattern, and a silicon nitride film deposited by plasma deposition is then deposited as a passivation film. The state of formation is shown in FIG.

Note that in this embodiment, the source is NMO8.

An impurity with the same polarity as the drain was implanted, but this
8. It goes without saying that the present invention can be applied to CMOB as well as other semiconductor devices. Further, an impurity having a different polarity from that of the source and drain may be implanted, and in some cases, a non-polar impurity that changes the threshold voltage may be implanted.

Further, in this embodiment, the ROM mesh was formed after the contact holes were formed, but it can also be formed after the metal wiring layer pattern is formed. Alternatively, it may be performed in a step before large-scale contact formation.

As described above, in the present invention, the threshold [EE] can be changed by injecting impurities into the channel region of the MO8 transistor by ion implantation or the like through the gate metal pattern of polycrystalline silicon. Therefore, there is no need for a special area for the ROM, and high integration can be achieved. In addition, in the case shown in this embodiment, the writing process of the ROM can be performed in the later stage of wafer delta processing (in this embodiment, it is carried out after the formation of the tact hole), which reduces the delivery time for providing semiconductor devices. It can be extremely shortened, and has a microscopic advantage over the conventional method of forming ROM eyes before forming the gate metal pattern. The difference is particularly large. This highly integrated mask program ROM
It becomes possible to provide semiconductor devices including the following in a short delivery period.

[Brief explanation of drawings]

FIGS. 1 to 6 are side cross-sectional views at various manufacturing steps as an example for explaining a semiconductor device according to the present invention. l...Single crystal silicon substrate, 6...Field film, 8...Polycrystalline silicon, 10-...Source, drain diffusion layer, 11...Silicon nitride film, 19...P
2O film, 17... Photoresist film, 18... RO
M-eye, 19 --- wiring metal layer. Representative Patent Attorney Takashi Okabe

Claims (1)

[Claims] (1) A step of forming a gate insulating film tube in an M I B type semiconductor device, a step of forming a gate metal pattern on the insulating film, and a step of forming source and drain diffusion layers. and injecting the charged particles so that at least four portions of the charged particles pass through the gate metal in a selected region of the gate metal pattern. (8) Said MI 8I! forming a silicon nitride film and forming a P2O film prior to the step of injecting charged particles through the metal in the selected region of the gate metal pattern of the semiconductor device; A method for manufacturing a semiconductor device according to claim 1, comprising the step of selectively removing P 8 Gjl in a desired region.