KR0150684B1 - A manufacturing method of a semiconductor device with multi-well - Google Patents
A manufacturing method of a semiconductor device with multi-well Download PDFInfo
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- KR0150684B1 KR0150684B1 KR1019940037670A KR19940037670A KR0150684B1 KR 0150684 B1 KR0150684 B1 KR 0150684B1 KR 1019940037670 A KR1019940037670 A KR 1019940037670A KR 19940037670 A KR19940037670 A KR 19940037670A KR 0150684 B1 KR0150684 B1 KR 0150684B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000005468 ion implantation Methods 0.000 claims abstract description 45
- 238000000034 method Methods 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000010408 film Substances 0.000 claims description 35
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 19
- 239000010409 thin film Substances 0.000 claims description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 13
- 230000003647 oxidation Effects 0.000 claims description 11
- 238000007254 oxidation reaction Methods 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 6
- 230000003064 anti-oxidating effect Effects 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims 1
- 238000002513 implantation Methods 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
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Abstract
본 발명은 고에너지 이온주입으로 공정을 간소화하기 위한 다중웰 구조를 갖는 반도체 소자 제조방법에 관한 것으로, 반도체 기판위에 선택적 이온주입마스크를 형성하는 단계 ; 상기 선택적 이온주입 마스크를 이용한 P(또는 N) 웰 이온주입을 수행하여 깊은 P(또는 N) 웰과 얕은 P(또는 N) 웰을 동시에 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.The present invention relates to a method of manufacturing a semiconductor device having a multi-well structure for simplifying a process by high energy ion implantation, the method comprising: forming a selective ion implantation mask on a semiconductor substrate; And performing a P (or N) well implantation using the selective ion implantation mask to simultaneously form a deep P (or N) well and a shallow P (or N) well.
Description
제1a도 내지 제1c도는 종래기술에 따른 반도체 소자 제조 공정도.1a to 1c is a semiconductor device manufacturing process chart according to the prior art.
제2a도 내지 제2d도는 본 발명의 일 실시예에 따른 반도체 소자 제조 공정도.2a to 2d is a semiconductor device manufacturing process chart according to an embodiment of the present invention.
제3a도 내지 제3e도는 본 발명의 다른 실시예에 따른 반도체 소자 제조 공정도.3A to 3E are diagrams illustrating a semiconductor device manufacturing process according to another exemplary embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
21 : 실리콘 기판 22 : 실리콘산화막21 silicon substrate 22 silicon oxide film
23 : 감광막 패턴 24 : 깊은 P웰23 photoresist pattern 24 deep P well
25 : 얕은 P웰 26 : N웰25: shallow P well 26: N well
본 발명은 반도체 제조반야에 관한 것으로, 특히 다중웰을 갖는 반도체 소자 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing field, and more particularly to a method for manufacturing a semiconductor device having multiple wells.
일반적으로, 고집적 소자에서는 상중웰을 형성하고 그 각각의 웰에 소자를 제조하고 있다. 이 기술은 깊은 P(또는 N)웰 내부에 얕은 N(또는 P)웰을 형성하고 이 곳에 P(또는 N) MOS 소자를 제작하는 것이다. 이러한 삼중웰 기술을 사용할 경우에 깊은 P(또는 N)웰과 얕은 N(또는 P)웰 사이에 커다란 캐패시턴스가 형성되어 MOS 소자가 노이즈에 강한 특성과 α-파티클에 의한 소프트 에러비율을 감소시킬 수 있다.In general, high density devices form a phase well and fabricate devices in their respective wells. This technique creates shallow N (or P) wells inside deep P (or N) wells and fabricates P (or N) MOS devices there. When using this triple well technique, large capacitances are formed between the deep P (or N) wells and the shallow N (or P) wells, which allows the MOS device to reduce noise and soft error rate due to α-particles. have.
제1a도 내지 제1c도는 종래기술에 따른 삼중웰 형성 공정도로서, 이를 참조하여 그 공정을 설명하면 다음과 같다.1a to 1c is a triple well forming process chart according to the prior art, the process will be described with reference to this as follows.
먼저, 제1a도에 도시된 바와 같이 실리콘 기판(1)상에 두꺼운 감광막 패턴(2)을 형성하여 상기 실리콘 기판(1)을 노출시킨 다음, 이온주입(Ion Implantation) 공정을 수행하여 P웰(3)을 형성한다.First, as illustrated in FIG. 1A, a thick photosensitive film pattern 2 is formed on the silicon substrate 1 to expose the silicon substrate 1, and then an ion implantation process is performed to perform P well ( 3) form.
이어서, 제1b도에 도시된 바와 같이 N웰(4)을 형성하고, 제1c도에 도시된 바와 같이 얕은 P웰을 형성하기 위해서 두꺼운 감광막 패턴(5)을 형성한 다음, 이를 마스크로 사용하여 이온주입 공정을 수행하여 P웰(6)을 형성한다.Subsequently, an N well 4 is formed as shown in FIG. 1B, and a thick photoresist pattern 5 is formed to form a shallow P well as shown in FIG. 1C, and then used as a mask. An ion implantation process is performed to form the P well 6.
이와 같이 종래기술은 두 번의 마스크 공정을 사용하여 깊은 P웰(3)과 얕은 P웰(6) 그리고, N웰(4)을 갖는 삼중웰 구조를 형성함으로써 공정이 다소 복잡한 단점이 있다.As such, the prior art has a disadvantage in that the process is rather complicated by forming a triple well structure having a deep P well 3, a shallow P well 6, and an N well 4 using two mask processes.
따라서, 본 발명은 고에너지 이온주입(High Energy Ion Implantation) 기술을 사용하여 공정을 간소화할 수 있는 다중웰을 갖는 반도체 소자 제조방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device having a multi-well that can simplify the process by using a high energy ion implantation technology.
상기 목적을 달성하기 위하여 본 발명은 다중웰을 갖는 반도체 소자 제조방법에 있어서, 반도체 기판상에 하드 마스크를 형성하는 제1 단계 ; 상기 하드 마스크를 이온주입 마스크로 사용하여 제1 도전형 불순물의 고에너지 이온주입을 실시하여 노출된 상기 반도체 기판에 깊은 제1도전형 웰을 형성하고, 동시에 상기 하드 마스크 하부에 얕은 제1 도전형 웰을 형성하는 제2 단계 ; 및 상기 하드 마스크를 이온주입 마스크로 사용하여 상기 깊은 제1 도전형 웰에 제2 도전형 웰을 형성하는 제3 단계를 포함한다.In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device having multiple wells, the method comprising: forming a hard mask on a semiconductor substrate; Using the hard mask as an ion implantation mask, high energy ion implantation of a first conductivity type impurity is performed to form a deep first conductivity type well in the exposed semiconductor substrate, and at the same time, a shallow first conductivity type under the hard mask. Forming a well; And a third step of forming a second conductivity type well in the deep first conductivity type well using the hard mask as an ion implantation mask.
또한, 본 발명은 다중웰을 갖는 반도체 소자 제조방법에 있어서, 반도체 기판상에 내산화성 박막 패턴을 형성하는 제1 단계 ; 상기 내산화성 박막 패턴을 이온주입 마스크로 사용하여 제1 도전형 불순물의 고에너지 이온주입을 실시하여 노출된 상기 반도체 기판에 깊은 제1 도전형 웰을 형성하고, 동시에 상기 내산화성 박막 패턴 하부에 얕은 제1도전형 웰을 형성하는 제2 단계 ; 상기 내산화성 박막 패턴을 이온주입 마스크로 사용하여 상기 깊은 제1 도전형 웰에 제2 도전형 웰을 형성하는 제3 단계 ; 상기 내산화성 박막 패턴을 이온주입 마스크로 사용하여 제2 도전형 웰에 제2 도전형 채널 이온주입을 실시하는 제4 단계 ; 상기 내산화성 박막 패턴을 산화방지 마스크로 사용하여 열산화를 실시함으로써 노출된 상기 반도체 기판상에 열산화막을 형성하는 제5 단계 ; 상기 내산화성 박막 패턴을 제거하는 제6 단계 ; 및 상기 열산화막을 이온주입 마스크로 사용하여 상기 얕은 제1도전형 웰에 제1 도전형 채널 이온주입을 실시하는 제7단계를 포함한다.In addition, the present invention is a semiconductor device manufacturing method having a multi-well, comprising: a first step of forming an oxide resistant thin film pattern on a semiconductor substrate; Using the oxide resistant thin film pattern as an ion implantation mask, high energy ion implantation of a first conductivity type impurity is performed to form a deep first conductive well in the exposed semiconductor substrate, and at the same time, a shallow bottom of the oxide resistant thin film pattern A second step of forming a first conductive well; A third step of forming a second conductivity type well in the deep first conductivity type well using the oxidation resistant thin film pattern as an ion implantation mask; Performing a second conductive channel ion implantation into a second conductive well using the oxidation resistant thin film pattern as an ion implantation mask; A fifth step of forming a thermal oxide film on the exposed semiconductor substrate by thermal oxidation using the oxidation resistant thin film pattern as an anti-oxidation mask; A sixth step of removing the oxidation resistant thin film pattern; And a seventh step of performing a first conductive channel ion implantation into the shallow first conductive well using the thermal oxide film as an ion implantation mask.
이하 본 발명의 용이하고 바람직한 실시예를 위하여 본 발명의 실시예를 소개한다.Hereinafter, embodiments of the present invention will be introduced for easy and preferred embodiments of the present invention.
첨부된 도면 제2a도 내지 제2d도는 본 발명의 일 실시예에 따른 반도체 소자제조 공정도로서, 한 번의 마스크 공정을 사용하여 깊은 P웰과 얕은 P웰 및 N웰을 갖는 삼중웰 구조를 형성하고 N웰 내부에 P채널 문턱전압 조절을 위한 이온주입 공정을 수행하는 과정을 나타낸 것이다.2A to 2D are diagrams illustrating a semiconductor device manufacturing process according to an exemplary embodiment of the present invention, wherein a single well mask process is used to form a triple well structure having a deep P well, a shallow P well, and an N well, and the N well. It shows a process of performing an ion implantation process for controlling the P-channel threshold voltage inside the well.
우선, 제2a도에 도시된 바와 같이 실리콘 기판(21) 상부에 실리콘산화막(22)을 증착하고 그 상부에 통상의 N웰 마스크를 사용하여 감광막 패턴(23)을 형성한다. 이때, 실리콘산화막(22)의 두께는 이후 P웰 형성을 위한 고에너지 이온주입 공정을 수행할 경우에 그 하부에 얕은 P웰이 형성될 수 있는 두께로 조절한다.First, as shown in FIG. 2A, a silicon oxide film 22 is deposited on the silicon substrate 21, and a photoresist pattern 23 is formed on the silicon substrate 21 using a conventional N well mask. In this case, the thickness of the silicon oxide film 22 is adjusted to a thickness at which a shallow P well may be formed below the high energy ion implantation process for P well formation.
이어서, 제2b도에 도시된 바와 같이 감광막 패턴(23)을 식각 마스크로 사용하여 실리콘산화막(22)을 선택식각하고, 패터닝된 실리콘산화막(22)을 이온주입 마스크로 사용하여 P형 불순물 고에너지 이온주입 공정을 수행함으로써 실리콘산화막(22)이 없는 영역은 깊은 P웰(24)을 형성하고, 실리콘산화막(22) 하부에는 얕은 P(25)이 동시에 형성되도록 한다. 여기서 고에너지 이온주입 마스크로 사용된 실리콘산화막(22)은 그 두께 조절이 용이하므로 깊이가 다른 두 P웰(24, 25)을 동시에 적절하게 형성할 수 있다.Subsequently, as shown in FIG. 2B, the silicon oxide film 22 is selectively etched using the photoresist pattern 23 as an etch mask, and the patterned silicon oxide film 22 is used as an ion implantation mask, thereby providing high P-type impurity high energy. By performing the ion implantation process, a region having no silicon oxide film 22 forms a deep P well 24, and a shallow P 25 is simultaneously formed under the silicon oxide film 22. Since the silicon oxide film 22 used as the high energy ion implantation mask can be easily adjusted in thickness, two P wells 24 and 25 having different depths can be appropriately formed simultaneously.
다음으로, 제2c도에 도시된 바와 같이 실리콘산화막(22)을 이온주입 마스크로 사용하여 N웰(26)을 형성한다.Next, as shown in FIG. 2C, the N well 26 is formed using the silicon oxide film 22 as an ion implantation mask.
제2d도는 실리콘산화막(22)을 이온주입 마스크로사용하여 N웰 내부에 P채널 문턱전압 조절(Threshold Adjustment)을 위한 이온주입영역(27)을 수행한 후의 단면도를 나타낸 것이다.FIG. 2D is a cross-sectional view after performing the ion implantation region 27 for P-channel threshold adjustment inside the N well using the silicon oxide film 22 as an ion implantation mask.
이후 통상의 MOS 트랜지스터 제조 공정을 수행한다.After that, a conventional MOS transistor manufacturing process is performed.
한편, 제3a도 내지 제3e도는 본 발명의 다른 실시예에 따른 반도체 소자 제조공정도로서, 한번의 마스크 공정을 사용하여 깊은 P웰과 얕은 P웰 그리고, N웰을 갖는 삼중웰 구조를 형성하고, P채널 문턱전압 조절을 위한 이온주입영역과 N채널 문턱 전압 조절을 위한 이온주입영역을 형성할 수 있는 제조과정을 나타낸 것으로 각 단계를 설명하면 다음과 같다.3A to 3E illustrate a semiconductor device fabrication process according to another exemplary embodiment of the present invention, which uses a single mask process to form a triple well structure having a deep P well, a shallow P well, and an N well, and P The manufacturing process for forming the ion implantation region for the channel threshold voltage control and the ion implantation region for the N channel threshold voltage adjustment is described below.
먼저, 제3a도에 도시된 바와 같이 실리콘 기판(31) 상부에 스트레스 완충용으로 사용되는 실리콘산화막(32)을 형성하고 그 위에 실리콘질화막(33)을 형성한 다음, 통상의 N웰 마스크를 사용한 사진 및 식각공정을 진행하여 이들을 선택식각한다. 이때, 패터닝된 실리콘산화막(32)과 실리콘질화막(33)의 두께는 이후 P웰 형성을 위한 고에너지 이온주입 공정을 수행할 경우에 그 하부에 얕은 P웰이 형성될 수 있는 두께로 조절한다.First, as shown in FIG. 3A, a silicon oxide film 32 used for stress buffer is formed on the silicon substrate 31, and a silicon nitride film 33 is formed thereon. Then, a conventional N well mask is used. Photolithography and etching processes are performed to selectively etch them. In this case, the thicknesses of the patterned silicon oxide layer 32 and the silicon nitride layer 33 are adjusted to a thickness at which a shallow P well may be formed below the high energy ion implantation process for P well formation.
이어서, 제3b도에 도시된 바와 같이 고에너지 이온주입법을 사용하여 P형 불순물을 이온주입하여 실리콘질화막(33)이 없는 영역은 깊은 P웰(34)이 형성되고 실리콘질화막(33) 하부에는 얕은 P웰(35)이 동시에 형성되도록 한다. 여기서 사용된 실리콘산화막(32) 및 실리콘질화막(33)은 그 두께 조절이 용이하므로 깊이가 다른 두 P웰(34, 35)을 동시에 적절하게 형성할 수 있다.Subsequently, as shown in FIG. 3B, the P-type impurity is ion-implanted using high energy ion implantation to form a deep P well 34 in the region where the silicon nitride film 33 is not present and a shallow portion below the silicon nitride film 33. P wells 35 are formed simultaneously. Since the silicon oxide film 32 and the silicon nitride film 33 used herein can be easily adjusted in thickness, two P wells 34 and 35 having different depths can be appropriately formed simultaneously.
계속해서, 제3c도에 도시된 바와 같이 실리콘산화막(32) 및 실리콘질화막(33)을 이온주입 마스크로 사용하여 N웰(36)을 형성한다.Subsequently, as shown in FIG. 3C, the N well 36 is formed by using the silicon oxide film 32 and the silicon nitride film 33 as ion implantation masks.
다음으로, 제3d도에 도시된 바와 같이 역시 실리콘산화막(32) 및 실리콘질화막(33)을 이온주입 마스크로 사용하여 N웰 내부에 P채널 문턱전압 조절을 위한 이온주입영역(37)을 형성한다.Next, as shown in FIG. 3D, the ion implantation region 37 for controlling the P-channel threshold voltage is formed inside the N well by using the silicon oxide film 32 and the silicon nitride film 33 as ion implantation masks. .
끝으로, 제3e도에 도시된 바와 같이 실리콘질화막(33)을 산화방지 마스크로 사용하여 열산화를 실시함으로써 실리콘질화막(33)이 없는 영역에 실리콘산화막(28)을 형성하고, 실리콘질화막(33)을 제거한 다음, 얕은 P웰(35)에 N채널 문턱전압 조절을 위한 이온주입영역(39)을 형성한다.Finally, as shown in FIG. 3E, thermal oxidation is performed using the silicon nitride film 33 as an anti-oxidation mask to form the silicon oxide film 28 in the region where the silicon nitride film 33 is not present, and the silicon nitride film 33 Next, the ion implantation region 39 for N channel threshold voltage control is formed in the shallow P well 35.
이후 통상의 MOS 트랜지스터 제조 공정을 수행한다.After that, a conventional MOS transistor manufacturing process is performed.
이상의 실시예에서는 삼중웰을 일례로 들어 설명하였으나, 본발명은 그 이상의 다중웰에도 적용될 수 있다.In the above embodiment, the triple well has been described as an example, but the present invention can be applied to more than one well.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않은 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은 삼중웰(및 채널 이온주입영역)을 한번의 마스크로 공정을 통해 형성함으로써 공정 간소화 및 생산성 향상 효과를 얻을 수 있다.According to the present invention, the triple well (and the channel ion implantation region) are formed through a single mask process to obtain a process simplification and productivity improvement.
Claims (6)
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| KR1019940037670A KR0150684B1 (en) | 1994-12-28 | 1994-12-28 | A manufacturing method of a semiconductor device with multi-well |
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