JPH06151852A - Thin film transistor - Google Patents

Abstract

PURPOSE:To easily form a minute offset section in a thin film transistor of offset structure with accuracy. CONSTITUTION:A first gate insulating film 13, first gate electrode 14, second gate insulating film 15, and second gate electrode 16 are formed on a polysilicon thin film 12 in this order. The planar distance L1 between the boundary of the channel region 12a and source/drain region 12b and the end of the first gate electrode 14, is slightly larger than the sum of the thickness T1 and T2 of both gate insulating films 13 and 15. Therefore, the portion of both gate insulating films 13 and 15 between the boundary of the channel region 12a and source/drain region 12b and the second gate electrode 16, functions as an offset section. The thickness T1 and T2 of both gate insulating films 13 and 15 is easily controllable with accuracy by controlling such factors as film formation time; accordingly, minute offset sections can be easily formed with accuracy.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an offset structure thin film transistor.

[0002]

2. Description of the Related Art Among thin film transistors, there is one called an offset structure as an element for reducing leak current and preventing punch through. In such a conventional thin film transistor, by making the length of the gate electrode shorter than the length of the channel region between the source / drain regions, the structure has an offset portion between the source / drain region and the gate electrode. There is.

When manufacturing a conventional thin film transistor having such an offset structure, first, as shown in FIG.
As shown in (A), a polysilicon thin film (semiconductor thin film) 2 is patterned on the upper surface of an insulating substrate 1 made of ceramic or glass, and a gate insulating film 3 made of silicon oxide is formed on the entire upper surface. Next, the polysilicon thin film 2
Of the photoresist film 4 on the upper surface of the gate insulating film 3 corresponding to the channel region 2a of
Is patterned, and impurities are implanted using the photoresist film 4 as a mask to form the photoresist film 4
Source / drain regions 2b made of impurity regions are formed in the polysilicon thin film 2 on both sides of the. Then, the photoresist film 4 is removed. Next, as shown in FIG. 4B, a gate electrode forming film 5 made of chromium is formed on the entire upper surface of the gate insulating film 3. Next, a photoresist film 6 is pattern-formed again by photolithography on the upper surface of the gate electrode forming film 5 in the portion corresponding to the central portion of the channel region 2a of the polysilicon thin film 2. Next, the gate electrode forming film 5 is etched using the photoresist film 6 as a mask, and then the photoresist film 6 is removed. As shown in FIG. 4C, a gate electrode shorter than the length of the channel region 2a is formed. 5a is formed. The gate insulating film 3 existing between the boundary surface between the channel region 2a and the source / drain region 2b and the end surface of the gate electrode 5a.
Is the offset portion, and the distance L in the plane direction between them is the distance of the offset portion.

[0004]

However, in such a conventional thin film transistor, the photoresist film 4 as an impurity implantation mask and the photoresist film 6 as an etching mask are patterned by separate photolithography steps. Therefore, in order to equalize the distance L between the two offset portions on both sides of the gate electrode 5a, there is a problem that high alignment accuracy and processing accuracy are required in each photolithography process.
Further, if the distance L of the offset portion is large, the on-current of the transistor is lowered. Therefore, it is desirable that the distance L is as small as 1 μm or less, but it is difficult to form a fine offset portion due to the resolution of the photolithography method. There was a problem. An object of the present invention is to provide a thin film transistor capable of easily forming a fine offset portion without requiring high alignment accuracy and processing accuracy.

[0005]

According to the present invention, in a thin film transistor in which a gate insulating film is provided between a semiconductor thin film having source / drain regions formed on both sides of a channel region and a gate electrode, the gate electrode is the channel. A first gate electrode portion facing the central portion of the region, and a second gate electrode portion facing the boundary portion between the channel region and the source / drain region, and the channel region and the source / drain region. The plane distance between the boundary surface of the drain region and the end surface of the first gate electrode portion is between the portion of the boundary surface between the channel region and the source / drain region and the second gate electrode portion. It is made larger than the film thickness of the gate insulating film.

[0006]

According to the present invention, the distance in the plane direction between the boundary surface between the channel region and the source / drain region and the end surface of the first gate electrode portion is determined by the distance between the boundary surface portion between the channel region and the source / drain region Since it is made thicker than the thickness of the gate insulating film existing between the gate electrode and the gate electrode, the gate insulating film existing between the gate electrode and the interface between the channel region and the source / drain region is offset. Part of the
The film thickness of the gate insulating film becomes the distance of the offset portion. In this case, the film thickness of the gate insulating film, which is the distance of the offset portion, may be controlled by controlling the film forming time, and this control can be performed easily and accurately, and the two offset portions have the same thickness. be able to. Therefore,
The fine offset portion can be easily formed without requiring high alignment accuracy and processing accuracy.

[0007]

FIG. 1 shows an essential part of a thin film transistor according to a first embodiment of the present invention. In this thin film transistor, the insulating substrate 1 made of ceramic or glass is used.
A polysilicon thin film (semiconductor thin film having a source / drain region 12b made of an impurity region is formed on the upper surface of 1 by implanting impurities into the polysilicon thin film deposited on the entire upper surface using an impurity implantation mask (not shown) and then separating the elements. A thin film) 12 is patterned. A first gate insulating film 13 made of silicon oxide is formed on the entire upper surface of the insulating substrate 11 including the polysilicon thin film 12.
A first gate electrode 14 made of chromium is patterned on the upper surface of the first gate insulating film 13 in a portion of the polysilicon thin film 12 corresponding to the center of the channel region 12a. A second gate insulating film (interlayer insulating film) 15 made of silicon oxide is formed on the entire upper surface of the first gate insulating film 13 including the first gate electrode 14. On the upper surface of the second gate insulating film 15 corresponding to the channel region 12a of the polysilicon thin film 12 and parts of the source / drain regions 12b on both sides thereof, a second layer of chromium is formed.
The gate electrode 16 is patterned. The second gate electrode 16 is electrically connected to the first gate electrode 14 outside.

Next, the dimensional relationship of the thin film transistor will be described. As an example, the polysilicon thin film 12 has a film thickness of 500Å, the first gate insulating film 13 has a film thickness T ₁ of 1000Å, and the first gate electrode 14 has a film thickness of 500Å,
The thickness T ₂ of the second gate insulating film 15 is 2000Å,
The gate electrode 16 has a film thickness of 500 Å. Then, the channel region 12a and the source / drain region 12b
Plane direction of the distance L ₁ between the boundary surface and the end surface of the first gate electrode 14 of the sum of the thickness T ₂ of the film thickness T ₁ and the second gate insulating film 15 of the first gate insulating film 13 It is somewhat larger than (T ₁ + T ₂ ). Therefore, the offset portion in this thin film transistor has both gate insulating films 13 existing between the portion of the interface between the channel region 12a and the source / drain region 12b and the second gate insulating film 16,
It becomes the part of 15. As a result, the distance of the offset part is
Sum of film thicknesses T ₁ and T ₂ of both gate insulating films 13 and 15 (T ₁ +
T ₂ ).

By the way, the film thicknesses T ₁ and T ₂ of both gate insulating films 13 and 15 can be easily and accurately controlled by controlling the film forming time, and the first gate electrode 14 can be controlled. Can be the same on both sides of. Therefore, in the case of this example, the sum (T ₁ + T ₂ ) of the film thicknesses T ₁ and T ₂ of both gate insulating films 13 and 15 which is the distance of the offset portion is about 3000 Å, and the fine offset portion has high alignment accuracy and It can be easily formed without requiring processing accuracy. In particular, a photolithography process for implanting impurities and the first gate insulating film 13 are performed.
After the photolithography process for forming the channel, the channel region 12a and the source / drain region 12 are formed.
Even if the distance L _{1 in} the surface direction between the boundary surface of b and the end surface of the first gate electrode 14 is different on both sides, the film thicknesses T ₁ and T _{2 of the} gate insulating films 13 and 15 that are the distances of the offset portions Has nothing to do with the sum (T ₁ + T ₂ ), and thus no problem occurs.

Next, FIG. 2 shows a main part of a thin film transistor in the second embodiment of the present invention. In this thin film transistor, on the upper surface of the insulating substrate 21 made of ceramic, glass or the like, as in the case of the first embodiment,
A polysilicon thin film 22 having source / drain regions 22b formed of impurity regions is patterned. A gate insulating film 23 made of silicon oxide is formed on the entire upper surface of the insulating substrate 21 including the polysilicon thin film 22. In this case, the channel region 2 of the polysilicon thin film 22
The gate insulating film 23 in the portion corresponding to the central portion of 2a
A concave portion 24 is formed on the upper surface of the by removing a part of the portion by etching by photolithography. Channel region 22 of polysilicon thin film 22
A gate electrode 25 made of aluminum is patterned on the upper surface of the gate insulating film 23 in a portion corresponding to a and the source / drain regions 22b on both sides thereof.

Next, the dimensional relationship of the thin film transistor will be described. As an example, the thickness of the polysilicon thin film 22 is 500Å, and the thickness T ₃ of the gate insulating film 23 is 300.
0Å, the depth of the recess 24 is 2000Å (that is, the film thickness of the gate insulating film 23 in this portion is 1000Å), and the film thickness of the gate electrode 25 is 5000Å. The distance L _{2 in} the surface direction between the boundary surface between the channel region 22a and the source / drain region 22b and the end surface of the gate electrode (first gate electrode portion) 25 in the recess 24 is the gate in the portion where the recess 24 does not exist. It is larger than the film thickness T ₃ of the insulating film 23 to some extent. Therefore, the offset portion of this thin film transistor is the channel region 22.
A portion of the boundary surface between a and the source / drain region 22b and a gate insulating film (second gate electrode portion) 25 facing the portion.
Will be the portion of the gate insulating film 23 that exists between and. As a result, the distance of the offset portion becomes the film thickness T ₃ of the gate insulating film 23 in the portion where the recess 24 does not exist. Also in this case, the film thickness T ₃ of the gate insulating film 23 in the portion where the concave portion 24 does not exist is controlled by controlling the film forming time and the like.
It can be easily and accurately controlled and can be the same on both sides of the recess 24. Therefore, in the case of this example, the film thickness T ₃ of the gate insulating film 23 in the portion where the concave portion 24 that is the distance of the offset portion does not exist is
Since it is about 00Å, a fine offset portion can be easily formed without requiring high alignment accuracy and processing accuracy.

Next, FIG. 3 shows an essential part of a thin film transistor according to a third embodiment of the present invention. In this thin film transistor, on the upper surface of the insulating substrate 31 made of ceramic, glass or the like, as in the case of the first embodiment,
A polysilicon thin film 32 having source / drain regions 32b formed of impurity regions is patterned. A first gate insulating film 33 made of silicon oxide is formed on the entire upper surface of the insulating substrate 31 including the polysilicon thin film 32. On the upper surface of the first gate insulating film 33, a predetermined portion of the second gate insulating film made of silicon nitride deposited on the entire upper surface, that is, a portion corresponding to the central portion of the channel region 32a of the polysilicon thin film 32 is photo-processed. A second gate insulating film (interlayer insulating film) 35 having a hole 34 is patterned by etching and removing by a lithography method. A gate electrode 36 made of aluminum is formed on the upper surfaces of the first and second gate insulating films 33, 35 corresponding to the channel region 32a of the polysilicon thin film 32 and the source / drain regions 32b on both sides thereof. It is patterned.

Next, the dimensional relationship of the thin film transistor will be described. As an example, the thickness of the polysilicon thin film 32 is 500Å, the thickness T ₄ of the first gate insulating film 33 is 1000Å, and the thickness T ₅ of the second gate insulating film 35 is 40.
The film thickness of 00Å and the gate electrode 36 is 5000Å. Then, a distance L in the surface direction between the boundary surface between the channel region 32a and the source / drain region 32b and the end surface of the gate electrode (first gate electrode portion) 36 in the hole 34.
₃ has somewhat greater than the sum of the thickness T ₄ of the first gate insulating film 33 and the thickness T ₅ of the second gate insulating film _{35 (T 4 + T 5)} . Therefore, the offset portion in this thin film transistor has both gate insulating films present between the portion of the boundary surface between the channel region 32a and the source / drain region 32b and the gate electrode (second gate electrode portion) 36 facing the portion. It becomes part 33, 35. As a result, the distance of the offset portion is
Is the sum of the film thicknesses T ₄ and T ₅ (T ₄ + T ₅ ). Also in this case,
The film thicknesses T ₄ and T ₅ of both gate insulating films 33 and 35 can be easily and accurately controlled by controlling the film formation time and the like, and can be the same on both sides of the hole 34. Therefore, in this example, the sum (T ₄ + T ₅ ) of the film thicknesses T ₄ and T ₅ of both gate insulating films 33 and 35, which is the distance of the offset portion, is about 5000 Å, and the fine offset portion has high alignment accuracy and It can be easily formed without requiring processing accuracy.

[0014]

As described above, according to the present invention, the gate insulating film existing between the portion of the interface between the channel region and the source / drain region and the gate electrode facing the portion is used as the offset portion. Since the film thickness of the gate insulating film is the distance of the offset portion, the fine offset portion can be easily formed without requiring high alignment accuracy and processing accuracy.

[Brief description of drawings]

FIG. 1 is a sectional view of an essential part of a thin film transistor according to a first embodiment of the present invention.

FIG. 2 is a sectional view of an essential part of a thin film transistor according to a second embodiment of the present invention.

FIG. 3 is a sectional view of an essential part of a thin film transistor according to a third embodiment of the invention.

4A to 4C are cross-sectional views showing respective manufacturing steps of a conventional thin film transistor.

[Explanation of symbols]

 12 polysilicon thin film (semiconductor thin film) 12a channel region 12b source / drain region 13 first gate insulating film 14 first gate electrode 15 second gate insulating film 16 second gate electrode

Claims (3)

[Claims] 1. A thin film transistor having a gate insulating film between a semiconductor thin film having source / drain regions formed on both sides of a channel region and a gate electrode, wherein the gate electrode faces a central portion of the channel region. 1 gate electrode portion, the channel region and the source
A drain region boundary surface portion and a second gate electrode portion facing each other, and a surface distance between the channel region and the source / drain region boundary surface and the end face of the first gate electrode portion. Is greater than the thickness of the gate insulating film existing between the second gate electrode portion and the interface between the channel region and the source / drain region. 2. The first gate electrode portion is provided in the gate insulating film, and the second gate electrode portion is provided on a surface of the gate insulating film opposite to a surface facing the semiconductor thin film. The thin film transistor according to claim 1, wherein the thin film transistor is provided. 3. The thin film transistor according to claim 1, wherein a portion of the gate insulating film facing the central portion of the channel region is thin and other portions are thick.