CN105405866A - Oled display and manufacturing method thereof - Google Patents
Oled display and manufacturing method thereof Download PDFInfo
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- CN105405866A CN105405866A CN201511029765.9A CN201511029765A CN105405866A CN 105405866 A CN105405866 A CN 105405866A CN 201511029765 A CN201511029765 A CN 201511029765A CN 105405866 A CN105405866 A CN 105405866A
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- grid
- oled display
- insulating barrier
- manufacture method
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
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- Microelectronics & Electronic Packaging (AREA)
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- Manufacturing & Machinery (AREA)
- Electroluminescent Light Sources (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention provides a manufacturing method of an OLED display. The manufacturing method of the OLED display includes the following steps that: a substrate is provided, and a source, a drain and a channel are formed on the substrate; a first gate insulating layer is formed on the substrate; a first gate is formed on the first gate insulating layer; with the first gate adopted as a mask, the first gate insulating layer is etched; a second gate insulating layer is formed on the first gate; and a second gate is formed on the second gate insulating layer. According to the manufacturing method, a distance from the first gate to the channel is different from a distance from the second gate to the channel. With the manufacturing method of the OLED display adopted, a pixel region and a peripheral circuit region can adopt gate insulating layers of different thickness, and therefore, the on-state current of the pixel region can be reduced, and high current can be ensured for the peripheral GIP circuit region.
Description
Technical field
The present invention relates to display fabrication techniques field, particularly a kind of OLED display and manufacture method thereof.
Background technology
In recent years, center, monitor market is gradually occupied by flat-panel monitor (FlatPanelDisplay, FPD).FPD is utilized to manufacture large scale and thin and light display device.This kind of FPD comprises liquid crystal display (LiquidCrystalDisplay, LCD), plasma display (PlasmaDisplayPanel, PDP), Organic Light Emitting Diode (OrganicLightEmittingDiode, OLED) display etc.
OLED display is a kind of emerging flat-panel monitor, it possesses self-luminous, do not need that backlight, contrast are high, thickness is thin, visual angle is wide, reaction speed is fast, can be used for flexibility panel, serviceability temperature scope is wide, structure and the processing procedure excellent characteristic such as simpler, therefore there is extraordinary development prospect.
High PPI (number of pixels that per inch has) is the trend of display industry future development, the lifting of PPI makes the area of unit picture element (Pixel) constantly reduce, after elemental area reduces, the area correspondence of luminous zone reduces, required glow current diminishes thereupon, therefore needs again to transform to reduce ON state current to the structure of thin-film transistor (TFT).
But it is existing for reducing in the solution of ON state current, there is the problem that in periphery GIP (GateInPanel) circuit, electric current is inadequate, and high PPI display needs periphery GIP circuit to have larger electric current to ensure transmission and transmission speed, therefore existing solution has some limitations.
Summary of the invention
The object of the present invention is to provide a kind of OLED display and manufacture method thereof, the ON state current of reduction pixel region can not be had concurrently to solve OLED display of the prior art and ensure that periphery GIP circuit region has the problem of larger current.
For solving the problems of the technologies described above, the invention provides a kind of manufacture method of OLED display, the manufacture method of described OLED display comprises:
Substrate is provided, described substrate is formed with source electrode, drain electrode and raceway groove;
Form first grid insulating barrier on the substrate;
Described first grid insulating barrier forms first grid;
With described first grid for mask, etch described first grid insulating barrier;
Described first grid is formed second gate insulating barrier; And
Described second gate insulating barrier forms second grid;
Wherein, described first grid is different to the distance of raceway groove from described second grid to the distance of raceway groove.
Optionally, in the manufacture method of described OLED display, described first grid insulating barrier comprises the first silicon oxide layer be formed on described substrate and the first silicon nitride layer be formed on described first silicon oxide layer.
Optionally, in the manufacture method of described OLED display, with described first grid for mask, etch in described first grid insulating barrier and only described first silicon nitride layer is etched.
Optionally, in the manufacture method of described OLED display, with described first grid for mask, etch in described first grid insulating barrier and described first silicon nitride layer and the first silicon oxide layer are all etched.
Optionally, in the manufacture method of described OLED display, described first grid is the grid in pixel region, and described second grid is the grid in peripheral circuit area.
Optionally, in the manufacture method of described OLED display, described first grid is the part of grid pole in pixel region and/or the part of grid pole in peripheral circuit area, and described second grid is the part of grid pole in pixel region and/or the part of grid pole in peripheral circuit area.
Optionally, in the manufacture method of described OLED display, described in the Thickness Ratio of described second gate insulating barrier, the thickness of first grid insulating barrier is little.
Optionally, in the manufacture method of described OLED display, described second gate insulation comprises the second silicon nitride layer.
Optionally, in the manufacture method of described OLED display, also comprise: on described second grid, form interlayer dielectric layer.
Optionally, in the manufacture method of described OLED display, also comprise: on described interlayer dielectric layer, form anode, organic luminous layer and negative electrode successively.
The present invention also provides a kind of OLED display, and described OLED display comprises:
Substrate, described substrate is formed with source electrode, drain electrode and raceway groove;
Be positioned at the gate insulation layer on described substrate;
Be positioned at the first grid on described gate insulation layer and second grid;
Wherein, described first grid is different to the distance of raceway groove from described second grid to the distance of raceway groove.
Optionally, in described OLED display, described first grid is the grid in pixel region, and described second grid is the grid in peripheral circuit area.
Optionally, in described OLED display, described first grid is the part of grid pole in pixel region and/or the part of grid pole in peripheral circuit area, and described second grid is the part of grid pole in pixel region and/or the part of grid pole in peripheral circuit area.
Optionally, in described OLED display, also comprise:
Be formed at the interlayer dielectric layer on described second grid;
Be formed at the anode on described interlayer dielectric layer;
Be formed at the organic luminous layer on described anode; And
Be formed at the negative electrode on described organic luminous layer.
Inventor finds after have extensively studied prior art, prior art is by increasing the thickness of gate insulation layer or doing dual-gate insulating barrier and reduce ON state current, which can make the ON state current of pixel region and peripheral circuit area reduce simultaneously, but but have ignored this point in prior art, thus result in OLED display of the prior art and can not have concurrently and reduce ON state current and ensure that periphery GIP circuit has the problem of larger current.
Therefore, inventing in the OLED display and manufacture method thereof provided, by forming first grid insulating barrier on substrate; Described first grid insulating barrier forms first grid; With described first grid for mask, etch described first grid insulating barrier; Described first grid is formed second gate insulating barrier; And second grid is formed on described second gate insulating barrier, thus make described first grid different to the distance of raceway groove from described second grid to the distance of raceway groove, namely pixel region and peripheral circuit area can adopt the gate insulation layer of different-thickness, just can have the ON state current of reduction pixel region thus concurrently and ensure that periphery GIP circuit region has larger current.
Accompanying drawing explanation
Fig. 1 ~ Fig. 4 is the generalized section of the structure that the manufacture method of the OLED display of the embodiment of the present invention is formed.
Embodiment
The OLED display proposed the present invention below in conjunction with the drawings and specific embodiments and manufacture method thereof are described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Please refer to Fig. 1 ~ Fig. 4, the generalized section of the structure that the manufacture method of its OLED display being the embodiment of the present invention is formed.
As shown in Figure 1, in the embodiment of the present application, first provide a substrate 10, described substrate 10 is formed with the raceway groove 12 between source electrode 11, drain electrode 13 and source-drain electrode.Preferably, described substrate 10 is glass substrate, further, described glass substrate can also form insulating barrier.Preferably, the material of described raceway groove 12 is polysilicon.
Please continue to refer to Fig. 1, in the embodiment of the present application, then, described substrate 10 forms first grid insulating barrier 14, i.e. described first grid insulating barrier 14 substrate 10 that covers described source electrode 11, drain electrode 13, raceway groove 12 between source-drain electrode and expose.Preferably, described first grid insulating barrier 14 is double-decker, comprises the first silicon oxide layer 14a be formed on described substrate 10 and the first silicon nitride layer 14b be formed on described first silicon oxide layer 14a.
Then, described first grid insulating barrier 14 forms first grid 15.In the embodiment of the present application, only on the first grid insulating barrier 14 of pixel region, grid (i.e. first grid 15) is formed.
Please refer to Fig. 2, then with described first grid 15 for mask, etch described first grid insulating barrier 15.In the embodiment of the present application, only described first silicon nitride layer 14b is etched.Further, only retain the first silicon nitride layer 14b of described first grid 15 protection, eliminate all first silicon nitride layer 14b in all the other regions.
In other embodiments of the application, also all can etch described first silicon nitride layer 14b and the first silicon oxide layer 14a.Concrete, only can retain the first silicon nitride layer 14b and the first silicon oxide layer 14a of the protection of described first grid 15, eliminate the first silicon nitride layer 14b of all first silicon nitride layer 14b in all the other regions and the full depth in all the other regions or segment thickness.
Then, as shown in Figure 3, described first grid 15 forming second gate insulating barrier 16, is the first silicon oxide layer 14a that described second gate insulating barrier 16 covers described first grid 15 and exposes at this.In the embodiment of the present application, to etch the gross thickness of remainder different for thickness and the described second gate insulating barrier 16 of described first grid insulating barrier 14 and (first grid 15 protection zone with exterior domain) first grid insulating barrier 14.Concrete, the gross thickness that second gate insulating barrier 16 described in the Thickness Ratio of described first grid insulating barrier 14 and (first grid 15 protection zone with exterior domain) first grid insulating barrier 14 etch remainder is large.Further, described in the Thickness Ratio of described second gate insulating barrier 16, the thickness of first grid insulating barrier 14 is little.Preferably, described second gate insulating barrier 16 is single layer structure, and it comprises the second silicon nitride layer.
As shown in Figure 4, described second gate insulating barrier 16 forms second grid 17.Preferably, in peripheral circuit area, only form grid (i.e. second grid 17).Namely in the embodiment of the present application, described first grid 15 is the grid in pixel region, and described second grid 17 is the grid in peripheral circuit area.Just can have the ON state current of reduction pixel region thus concurrently and ensure that periphery GIP circuit region has larger current.
In other embodiments of the application, can described first grid be also the part of grid pole in pixel region and/or the part of grid pole in peripheral circuit area, described second grid be the part of grid pole in pixel region and/or the part of grid pole in peripheral circuit area.Namely there are part first grid and/or part second grid in pixel region, in peripheral circuit area, have part first grid and/or part second grid.Namely make the thin-film transistor in whole OLED display have two kinds of different gate insulation layer thickness, thus different design requirements can be met.
Subsequent, then interlayer dielectric layer (ILD) (not shown in Fig. 4) can be formed on described second grid 17, the i.e. described interlayer dielectric layer second gate insulating barrier 16 that covers described second grid 17 and expose, described interlayer dielectric layer can adopt prior art, can continue to adopt prior art to perform subsequent technique simultaneously, specifically be included on described interlayer dielectric layer and form the structures such as anode, organic luminous layer and negative electrode successively, the application repeats no more this.
After above-mentioned technique, just can form OLED display, described OLED display comprises: substrate 10, described substrate 10 is formed with source electrode 11, drain electrode 13 and raceway groove 14; Be positioned at the gate insulation layer on described substrate 10; Be positioned at the first grid 15 on described gate insulation layer and second grid 17; Wherein, the distance of described first grid 15 to raceway groove is different from the distance of described second grid 17 to raceway groove.Further, the distance of described first grid 15 to raceway groove is larger than the distance of described second grid 17 to raceway groove.Further, described OLED display also comprises: be formed at the interlayer dielectric layer on described second grid; Be formed at the anode on described interlayer dielectric layer; Be formed at the organic luminous layer on described anode; And be formed at the structures such as negative electrode on described organic luminous layer.In the embodiment of the present application, described first grid 15 is the grid in pixel region, and described second grid 17 is the grid in peripheral circuit area.In other embodiments of the application, described first grid 15 is the part of grid pole in pixel region and/or the part of grid pole in peripheral circuit area, and described second grid 17 is the part of grid pole in pixel region and/or the part of grid pole in peripheral circuit area.Thus, just can have the ON state current reducing pixel region concurrently and ensure that periphery GIP circuit region has larger current; Or make the thin-film transistor in whole OLED display have two kinds of different gate insulation layer thickness, meet different design requirements.
Foregoing description is only the description to present pre-ferred embodiments, any restriction not to the scope of the invention, and any change that the those of ordinary skill in field of the present invention does according to above-mentioned disclosure, modification, all belong to the protection range of claims.
Claims (14)
1. a manufacture method for OLED display, is characterized in that, comprising:
Substrate is provided, described substrate is formed with source electrode, drain electrode and raceway groove;
Form first grid insulating barrier on the substrate;
Described first grid insulating barrier forms first grid;
With described first grid for mask, etch described first grid insulating barrier;
Described first grid is formed second gate insulating barrier; And
Described second gate insulating barrier forms second grid;
Wherein, described first grid is different to the distance of raceway groove from described second grid to the distance of raceway groove.
2. the manufacture method of OLED display as claimed in claim 1, it is characterized in that, described first grid insulating barrier comprises the first silicon oxide layer be formed on described substrate and the first silicon nitride layer be formed on described first silicon oxide layer.
3. the manufacture method of OLED display as claimed in claim 2, is characterized in that, with described first grid for mask, etch in described first grid insulating barrier and only etch described first silicon nitride layer.
4. the manufacture method of OLED display as claimed in claim 2, is characterized in that, with described first grid for mask, etch in described first grid insulating barrier and all etch described first silicon nitride layer and the first silicon oxide layer.
5. the manufacture method of the OLED display according to any one of Claims 1 to 4, is characterized in that, described first grid is the grid in pixel region, and described second grid is the grid in peripheral circuit area.
6. the manufacture method of the OLED display according to any one of Claims 1 to 4, it is characterized in that, described first grid is the part of grid pole in pixel region and/or the part of grid pole in peripheral circuit area, and described second grid is the part of grid pole in pixel region and/or the part of grid pole in peripheral circuit area.
7. the manufacture method of the OLED display according to any one of Claims 1 to 4, is characterized in that, described in the Thickness Ratio of described second gate insulating barrier, the thickness of first grid insulating barrier is little.
8. the manufacture method of OLED display as claimed in claim 7, is characterized in that, described second gate insulation comprises the second silicon nitride layer.
9. the manufacture method of the OLED display according to any one of Claims 1 to 4, is characterized in that, also comprises: on described second grid, form interlayer dielectric layer.
10. the manufacture method of OLED display as claimed in claim 9, is characterized in that, also comprise: on described interlayer dielectric layer, form anode, organic luminous layer and negative electrode successively.
11. 1 kinds of OLED display, is characterized in that, comprising:
Substrate, described substrate is formed with source electrode, drain electrode and raceway groove;
Be positioned at the gate insulation layer on described substrate;
Be positioned at the first grid on described gate insulation layer and second grid;
Wherein, described first grid is different to the distance of raceway groove from described second grid to the distance of raceway groove.
12. OLED display as claimed in claim 10, it is characterized in that, described first grid is the grid in pixel region, and described second grid is the grid in peripheral circuit area.
13. OLED display as claimed in claim 10, it is characterized in that, described first grid is the part of grid pole in pixel region and/or the part of grid pole in peripheral circuit area, and described second grid is the part of grid pole in pixel region and/or the part of grid pole in peripheral circuit area.
14. OLED display according to any one of claim 11 ~ 13, is characterized in that, also comprise:
Be formed at the interlayer dielectric layer on described second grid;
Be formed at the anode on described interlayer dielectric layer;
Be formed at the organic luminous layer on described anode; And
Be formed at the negative electrode on described organic luminous layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511029765.9A CN105405866B (en) | 2015-12-31 | 2015-12-31 | OLED display and its manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201511029765.9A CN105405866B (en) | 2015-12-31 | 2015-12-31 | OLED display and its manufacturing method |
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| CN105405866A true CN105405866A (en) | 2016-03-16 |
| CN105405866B CN105405866B (en) | 2019-01-04 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110660814A (en) * | 2019-09-29 | 2020-01-07 | 合肥京东方卓印科技有限公司 | Array substrate, display panel and manufacturing method of array substrate |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06151852A (en) * | 1992-11-04 | 1994-05-31 | Casio Comput Co Ltd | Thin film transistor |
| US6452212B1 (en) * | 1993-11-02 | 2002-09-17 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for operating the same |
| CN1691353A (en) * | 2004-04-26 | 2005-11-02 | 统宝光电股份有限公司 | Thin-film transistor and method for making same |
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2015
- 2015-12-31 CN CN201511029765.9A patent/CN105405866B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06151852A (en) * | 1992-11-04 | 1994-05-31 | Casio Comput Co Ltd | Thin film transistor |
| US6452212B1 (en) * | 1993-11-02 | 2002-09-17 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for operating the same |
| CN1691353A (en) * | 2004-04-26 | 2005-11-02 | 统宝光电股份有限公司 | Thin-film transistor and method for making same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110660814A (en) * | 2019-09-29 | 2020-01-07 | 合肥京东方卓印科技有限公司 | Array substrate, display panel and manufacturing method of array substrate |
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| CN105405866B (en) | 2019-01-04 |
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