CN106920753B - Thin film transistor, manufacturing method thereof, array substrate and display - Google Patents
Thin film transistor, manufacturing method thereof, array substrate and display Download PDFInfo
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- CN106920753B CN106920753B CN201710277714.0A CN201710277714A CN106920753B CN 106920753 B CN106920753 B CN 106920753B CN 201710277714 A CN201710277714 A CN 201710277714A CN 106920753 B CN106920753 B CN 106920753B
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- 239000010409 thin film Substances 0.000 title claims abstract description 32
- 239000000758 substrate Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 41
- 239000002184 metal Substances 0.000 claims abstract description 41
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 20
- 239000011737 fluorine Substances 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 11
- 238000009832 plasma treatment Methods 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 8
- 230000003746 surface roughness Effects 0.000 claims abstract description 7
- 238000002161 passivation Methods 0.000 claims description 10
- 229910004014 SiF4 Inorganic materials 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 claims description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 229910052749 magnesium Inorganic materials 0.000 claims description 6
- 239000011777 magnesium Substances 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 6
- 239000004332 silver Substances 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 130
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 14
- 230000003647 oxidation Effects 0.000 abstract description 12
- 238000007254 oxidation reaction Methods 0.000 abstract description 12
- 239000011241 protective layer Substances 0.000 abstract description 6
- 239000002356 single layer Substances 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 16
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 229910001873 dinitrogen Inorganic materials 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- -1 during the treatment Chemical compound 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
Abstract
The invention provides a thin film transistor and a manufacturing method thereof, an array substrate and a display, wherein the manufacturing method of the thin film transistor comprises the following steps: providing a substrate; forming a gate electrode layer, a gate insulating layer and an active layer on the substrate; depositing a metal layer on the active layer, carrying out plasma treatment on the metal layer by adopting fluorine-containing gas, and carrying out etching treatment on the treated metal layer to respectively form a source electrode layer and a drain electrode layer, wherein the source electrode layer and the drain electrode layer are respectively of a single-layer structure. The thin film transistor and the manufacturing method thereof improve the oxidation resistance of the source electrode and the drain electrode, simplify the source electrode layer and the drain electrode layer by a traditional three-layer structure with a protective layer on the upper and lower parts, reduce the contact resistance of the source electrode and the drain electrode and a channel, improve the surface roughness after the source electrode layer and the drain electrode layer are bombarded by plasma, enhance the adhesion between the source electrode layer and the photoresist and prevent the photoresist from being stripped, and improve the yield of the process.
Description
Technical Field
The invention relates to the technical field of display devices, in particular to a thin film transistor, a manufacturing method of the thin film transistor, an array substrate and a display.
Background
TFT-LCDs (thin film transistor liquid crystal displays) have been rapidly developed in recent years due to their advantages of low power consumption, thin and easy use, high brightness, high contrast, and high response speed, and thus have a dominant position in the current flat panel display market. In a TFT, a source and a drain are generally formed of a metal layer excellent in electrical properties. However, due to the characteristic that the metal layer is easily oxidized, a three-layer structure is generally adopted for preparing the source and drain electrodes, namely, a protective layer is respectively added on the upper and lower parts of the metal layer to prevent the source and drain electrodes from being oxidized in the TFT preparation process. Although the method can better avoid the oxidation of the metal layer, the contact resistance between the source and drain electrodes and the active region is also increased. And the adhesion between the source and drain and the photoresist is poor, and the photoresist is easy to strip. How to prepare a source-drain electrode film which has oxidation resistance and is well contacted with a photoresist is an urgent problem to be solved.
Disclosure of Invention
In view of the foregoing problems in the prior art, an object of the present invention is to provide a thin film transistor, a method for manufacturing the thin film transistor, an array substrate, and a display, which can improve the oxidation resistance of a source/drain and prevent the source/drain from peeling off from a photoresist.
In order to achieve the purpose, the invention adopts the following technical scheme.
The embodiment of the invention provides a manufacturing method of a thin film transistor, which comprises the following steps: providing a substrate; forming a gate electrode layer, a gate insulating layer and an active layer on the substrate; and depositing a metal layer on the active layer, carrying out plasma treatment on the metal layer by adopting fluorine-containing gas to improve the surface roughness, and carrying out etching treatment on the treated metal layer to respectively form a source electrode layer and a drain electrode layer.
Wherein the fluorine-containing gas comprises SiF4 and N2.
Wherein the source layer and the drain layer respectively comprise any one or a combination of copper, aluminum, magnesium and silver.
The manufacturing method of the thin film transistor further comprises depositing a passivation insulating layer after forming the source electrode layer and the drain electrode layer, patterning the passivation insulating layer, and then depositing a pixel electrode layer.
An embodiment of the present invention provides a thin film transistor including: a substrate; a gate electrode layer, a gate insulating layer and an active layer formed on the substrate; and a source layer and a drain layer formed over the active layer, wherein the source layer and the drain layer are subjected to plasma treatment of a fluorine-containing gas.
Wherein the fluorine-containing gas comprises SiF4 and N2.
Wherein the source layer and the drain layer respectively comprise any one or a combination of copper, aluminum, magnesium and silver.
The thin film transistor further comprises a passivation insulating layer and a pixel electrode layer formed on the source electrode layer and the drain electrode layer.
The embodiment of the invention also provides an array substrate, which comprises the thin film transistor.
The invention also provides a display, which comprises the array substrate.
The thin film transistor and the manufacturing method thereof improve the oxidation resistance of the source electrode and the drain electrode, simplify the source electrode layer and the drain electrode layer by a traditional three-layer structure with a protective layer on the upper and lower parts, reduce the contact resistance of the source electrode and the drain electrode and a channel, improve the surface roughness after the source electrode layer and the drain electrode layer are bombarded by plasma, enhance the adhesion between the source electrode layer and the photoresist and prevent the photoresist from being stripped, and improve the yield of the process.
Drawings
Fig. 1 shows a flow chart for fabricating a thin film transistor according to an embodiment.
Fig. 2 shows a schematic structural diagram of a source-drain metal layer before processing according to an embodiment.
Fig. 3 shows a process diagram for plasma treatment of a source drain metal layer with a fluorine-containing gas.
Fig. 4 shows a schematic structural diagram of a source-drain metal layer after processing according to an embodiment.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Example one
The embodiment provides a manufacturing method of a thin film transistor. Fig. 1 shows a flow chart for fabricating a thin film transistor according to an embodiment.
The method of manufacturing a thin film transistor according to the present embodiment includes the following steps.
In step S101, a substrate is provided, and a substrate is selected and cleaned.
In step S102, a gate electrode layer, a gate insulating layer, and an active layer are formed on the substrate by deposition, exposure, development, and etching.
Next, in step S103, a metal layer 1 is deposited, and the resulting structure is shown in fig. 2. Fig. 2 shows a schematic structural diagram of a source-drain metal layer before processing. The metal layer 1, i.e., the source layer and the drain layer to be formed later, may include any one or a combination of copper, aluminum, magnesium, and silver, and these metals have excellent electrical conductivity, so that they can provide excellent electrical contact properties to the thin film transistor, but are easily oxidized.
To solve this problem, in step S104, the metal layer 1 is plasma-treated with a fluorine-containing gas mainly including SiF4 gas and nitrogen gas.
Fig. 3 shows a process diagram for plasma treatment of a source drain metal layer with a fluorine-containing gas. As shown in fig. 3, the metal layer 1 is plasma-treated with SiF4 gas and nitrogen gas, during the treatment, SiF4 gas and nitrogen gas are plasma-converted to generate fluorine-containing groups, which are more oxidized than oxygen, and in the presence of the fluorine-containing groups, the metal does not react with oxygen in the air, and the fluorine-containing groups are equivalent to form a protective film on the surface of the metal to prevent the metal from reacting with oxygen in the air, thereby improving the oxidation resistance of the metal.
In the present embodiment, the metal layer is treated with plasma containing fluorine gas to enhance the oxidation resistance, and the source and drain layers do not require a protective layer on the upper and lower portions thereof, so that the structures of the source and drain layers can be simplified.
In addition, as shown in fig. 4, after the bombardment by the plasma, the surface roughness of the metal layer 1 is increased, so that the adhesion between the metal layer and the photoresist in the subsequent process can be enhanced, and the photoresist peeling phenomenon can be prevented.
Then, in step S105, the metal layer after the above-described treatment is subjected to a treatment such as etching, and a source layer and a drain layer are formed, respectively.
Finally, a passivation insulating layer is deposited after the source and drain layers are formed and patterned, the passivation insulating layer having a main component of silicon dioxide, and then an Indium Tin Oxide (ITO) film layer is deposited and patterned to form a pixel electrode layer.
In the embodiment, the metal layer, namely the source electrode layer and the drain electrode layer, is subjected to plasma treatment by adopting fluorine-containing gas, so that the oxidation resistance of the source drain electrode is improved, the source electrode layer and the drain electrode layer are simplified by adopting a traditional three-layer structure with a protective layer respectively arranged on the upper part and the lower part, the contact resistance of the source drain electrode and a channel is reduced, the surface roughness is improved after the source electrode layer and the drain electrode layer are bombarded by plasma, the adhesion force between the source electrode layer and the photoresist and the adhesion force between the drain electrode layer and the photoresist can be enhanced, the photoresist is prevented from being stripped, and the yield of the process is.
Example two
The present embodiment provides a thin film transistor.
The thin film transistor according to the present embodiment includes: a substrate; a gate electrode layer, a gate insulating layer and an active layer formed on the substrate; and a source electrode layer and a drain electrode layer formed over the active layer, wherein the source electrode layer and the drain electrode layer are formed by etching a metal layer deposited on the active layer. The metal layer, i.e., the source and drain layers, respectively comprise any one or a combination of copper, aluminum, magnesium, silver.
Before the metal layer is etched, the metal layer is subjected to oxidation resistance treatment, namely, the metal layer is subjected to plasma treatment by adopting fluorine-containing gas. The fluorine-containing gas composition includes SiF4 gas and nitrogen gas, and after treatment, an oxidation-resistant protective film is formed on the surface of the metal layer, thereby improving oxidation resistance of the metal layer, i.e., the source layer and the drain layer, the principle of which is described in the first embodiment and will not be described again.
After the source layer and the drain layer are subjected to plasma treatment with a fluorine-containing gas, the oxidation resistance is improved without protective layers respectively disposed on the upper and lower portions of the source layer and the drain layer in the conventional structure. Thus, the structures of the source layer and the drain layer can be simplified. The simplified structure of the source and drain layers can reduce the contact resistance of the source and drain layers with the channel. And after the source electrode layer and the drain electrode layer are bombarded by plasma, the surface roughness is improved, the adhesion between the source electrode layer and the photoresist is enhanced in the subsequent process, and the yield of the process is improved.
The thin film transistor according to the present embodiment further includes a passivation insulating layer and a pixel electrode layer formed on the source and drain layers, the passivation insulating layer having a main component of silicon dioxide, and the pixel electrode layer having a main component of Indium Tin Oxide (ITO).
An embodiment of the present invention further provides an array substrate including the thin film transistor as described above, and a liquid crystal display including the array substrate.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the principles of the technology employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the appended claims.
Claims (8)
1. A method for preparing a thin film transistor comprises the following steps:
providing a substrate;
forming a gate electrode layer, a gate insulating layer and an active layer on the substrate;
depositing a metal layer on the active layer, carrying out plasma treatment on the metal layer by adopting fluorine-containing gas to improve the surface roughness, and carrying out etching treatment on the treated metal layer to respectively form a source electrode layer and a drain electrode layer;
wherein the fluorine-containing gas is SiF4And N2And (4) forming.
2. The method of manufacturing a thin film transistor according to claim 1, wherein the source layer and the drain layer respectively comprise any one or a combination of copper, aluminum, magnesium, and silver.
3. The method of manufacturing a thin film transistor according to claim 1, further comprising depositing a passivation insulating layer after forming the source and drain layers, and patterning the passivation insulating layer, followed by depositing a pixel electrode layer.
4. A thin film transistor, comprising:
a substrate;
a gate electrode layer, a gate insulating layer and an active layer formed on the substrate;
a source layer and a drain layer formed over the active layer; wherein the source layer and the drain layer are formed by etching a metal layer formed on the active layer, and the metal layer is subjected to plasma treatment with a fluorine-containing gas before the etching treatment;
wherein the fluorine-containing gas is SiF4And N2And (4) forming.
5. The thin film transistor of claim 4, wherein the source and drain layers each comprise any one or a combination of copper, aluminum, magnesium, silver.
6. The thin film transistor of claim 4, further comprising a passivation insulating layer and a pixel electrode layer formed over the source and drain layers.
7. An array substrate comprising the thin film transistor according to any one of claims 4 to 6.
8. A display comprising the array substrate of claim 7.
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| CN201710277714.0A CN106920753B (en) | 2017-04-25 | 2017-04-25 | Thin film transistor, manufacturing method thereof, array substrate and display |
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| CN201710277714.0A CN106920753B (en) | 2017-04-25 | 2017-04-25 | Thin film transistor, manufacturing method thereof, array substrate and display |
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| CN106920753B true CN106920753B (en) | 2020-04-03 |
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| CN109727911A (en) * | 2018-12-10 | 2019-05-07 | 昆山龙腾光电有限公司 | Method for manufacturing thin film transistor array substrate |
| CN110335849B (en) * | 2019-06-25 | 2021-11-02 | 深圳市华星光电半导体显示技术有限公司 | Display device, array substrate and manufacturing method thereof |
| CN112002754A (en) * | 2020-08-11 | 2020-11-27 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, preparation method thereof and display panel |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1954413A (en) * | 2004-05-20 | 2007-04-25 | Psk有限公司 | Method for cleaning substrate surface |
| CN203423187U (en) * | 2013-04-10 | 2014-02-05 | 合肥京东方光电科技有限公司 | Thin film transistor, array substrate, and display device |
| CN106257618A (en) * | 2015-06-19 | 2016-12-28 | 东京毅力科创株式会社 | Use the film build method of plasma |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1954413A (en) * | 2004-05-20 | 2007-04-25 | Psk有限公司 | Method for cleaning substrate surface |
| CN203423187U (en) * | 2013-04-10 | 2014-02-05 | 合肥京东方光电科技有限公司 | Thin film transistor, array substrate, and display device |
| CN106257618A (en) * | 2015-06-19 | 2016-12-28 | 东京毅力科创株式会社 | Use the film build method of plasma |
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