CN106920753A - Thin film transistor (TFT) and preparation method thereof, array base palte and display - Google Patents
Thin film transistor (TFT) and preparation method thereof, array base palte and display Download PDFInfo
- Publication number
- CN106920753A CN106920753A CN201710277714.0A CN201710277714A CN106920753A CN 106920753 A CN106920753 A CN 106920753A CN 201710277714 A CN201710277714 A CN 201710277714A CN 106920753 A CN106920753 A CN 106920753A
- Authority
- CN
- China
- Prior art keywords
- layer
- drain electrode
- tft
- thin film
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 31
- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 39
- 239000002184 metal Substances 0.000 claims abstract description 39
- 238000009413 insulation Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000003851 corona treatment Methods 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000002161 passivation Methods 0.000 claims description 11
- 229910004014 SiF4 Inorganic materials 0.000 claims description 8
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 claims description 6
- 239000004411 aluminium Substances 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000011777 magnesium Substances 0.000 claims description 6
- 229910052749 magnesium Inorganic materials 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 6
- 239000004332 silver Substances 0.000 claims description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 4
- 239000010410 layer Substances 0.000 abstract description 112
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 13
- 238000000034 method Methods 0.000 abstract description 11
- 239000011241 protective layer Substances 0.000 abstract description 7
- 230000003746 surface roughness Effects 0.000 abstract description 5
- 239000002356 single layer Substances 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 18
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- 125000001153 fluoro group Chemical group F* 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 230000003026 anti-oxygenic effect Effects 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 239000003963 antioxidant agent Substances 0.000 description 1
- 230000003078 antioxidant effect Effects 0.000 description 1
- 235000006708 antioxidants Nutrition 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
Abstract
A kind of thin film transistor (TFT) of present invention offer and preparation method thereof, array base palte and display, the preparation method of the thin film transistor (TFT), including：Substrate is provided；Grid layer, gate insulation layer and active layer are formed on the substrate；Deposited metal layer, corona treatment is carried out using fluoro-gas to the metal level on the active layer, and treatment is performed etching to the metal level after treatment, and source layer and the drain electrode layer are formed respectively, and the source layer and the drain electrode layer are respectively single layer structure.Thin film transistor (TFT) that the present invention is provided and preparation method thereof; improve the inoxidizability of source-drain electrode; source layer and drain electrode layer are by traditional three-decker for respectively having layer protective layer up and down; it is simplified, reduces the contact resistance of source-drain electrode and raceway groove, and after source layer and drain electrode layer are by plasma bombardment; surface roughness is improved; the adhesion between source layer and drain electrode layer and photoresist can be strengthened, the stripping of photoresist is prevented, the yield of technique is improved.
Description
Technical field
The present invention relates to display device technology field, more particularly to a kind of thin film transistor (TFT) and preparation method thereof, array base
Plate and display.
Background technology
TFT-LCD (Thin Film Transistor-LCD) is due to possessing low-power consumption, frivolous easy-to-use, high brightness, high-contrast
With many merits such as high response speed, developed by leaps and bounds in recent years, occupied in current flat panel display market
Leading position.In TFT, source-drain electrode is generally made up of the excellent metal level of electric property.But easily aoxidized due to metal level
Characteristic, prepares source-drain electrode typically using three-decker, i.e., in the addition layer protective layer each up and down of metal level, to prevent source-drain electrode
Aoxidized in TFT preparation process.Although the above method can preferably avoid the oxidation of metal level, can also increase source and drain
Pole and the contact resistance of active area.And the adhesion between source-drain electrode and photoresist can be caused poor, photoresist lift off easily occurs
Phenomenon.How to prepare with inoxidizability and good source and drain very thin films are contacted with photoresist is problem demanding prompt solution.
The content of the invention
In view of above mentioned problem of the prior art, it is an object of the invention to provide a kind of thin film transistor (TFT) and its making side
Method, array base palte and display, improve the inoxidizability of source-drain electrode, and can avoid the stripping of source-drain electrode and photoresist.
It is that, up to above-mentioned purpose, the present invention uses following technical scheme.
Embodiments of the invention provide a kind of preparation method of thin film transistor (TFT), including：Substrate is provided；On the substrate
Form grid layer, gate insulation layer and active layer；The deposited metal layer on the active layer, using fluoro-gas to the metal level
Corona treatment is carried out to improve surface roughness, treatment is performed etching to the metal level after treatment, source layer is formed respectively
And drain electrode layer.
Wherein, the composition of the fluoro-gas includes SiF4 and N2.
Wherein, the source layer and the drain electrode layer are respectively including any one in copper, aluminium, magnesium, silver or its combination.
It is exhausted that the preparation method of the thin film transistor (TFT) is additionally included in deposition passivation after forming the source layer and drain electrode layer
Edge layer, and being patterned to the passivation insulation, then pixel deposition electrode layer.
Embodiments of the invention provide a kind of thin film transistor (TFT), including：Substrate；Grid layer, gate insulation layer and active layer, shape
Into on the substrate；Source layer and drain electrode layer, are formed in the active layer, wherein, the source layer and drain electrode layer
By the corona treatment of fluoro-gas.
Wherein, the composition of the fluoro-gas includes SiF4 and N2.
Wherein, the source layer and the drain electrode layer are respectively including any one in copper, aluminium, magnesium, silver or its combination.
Described thin film transistor (TFT) also includes being formed in the passivation insulation and pixel on the source layer and drain electrode layer
Electrode layer.
Embodiments of the invention also provide a kind of array base palte, including foregoing thin film transistor (TFT).
The present invention also provides a kind of display, including foregoing array base palte.
Thin film transistor (TFT) and preparation method thereof that the present invention is provided, improves the inoxidizability of source-drain electrode, source layer and
Drain electrode layer is simplified by traditional three-decker for respectively having layer protective layer up and down, reduces source-drain electrode with raceway groove
Contact resistance, and after source layer and drain electrode layer are by plasma bombardment, surface roughness is improved, and can strengthen source
Pole layer and the adhesion between drain electrode layer and photoresist, prevent the stripping of photoresist, improve the yield of technique.
Brief description of the drawings
Fig. 1 shows the flow chart of the making thin film transistor (TFT) according to embodiment.
Fig. 2 shows the structural representation of the source-drain electrode metal level before the treatment according to embodiment.
Fig. 3 shows to carry out Source and drain metal level using fluoro-gas the artwork of corona treatment.
Fig. 4 shows the structural representation of the source-drain electrode metal level after the treatment according to embodiment.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is only used for explaining the present invention, rather than limitation of the invention.It also should be noted that, for the ease of
Description, illustrate only part rather than entire infrastructure related to the present invention in accompanying drawing.
Embodiment one
The present embodiment provides a kind of preparation method of thin film transistor (TFT).Fig. 1 shows the making film crystal according to embodiment
The flow chart of pipe.
The method of the making thin film transistor (TFT) according to the present embodiment comprises the following steps.
In step S101, there is provided substrate, choose a substrate and clean up.
In step s 102, grid layer, grid are produced by techniques such as deposition, exposure, development, etchings on the substrate
Insulating barrier and active layer.
Next, in step S103, deposited metal layer 1, the structure for obtaining is as shown in Figure 2.Fig. 2 shows the source before treatment
The structural representation of drain metal layer.Here metal level 1 be the follow-up source layer and drain electrode layer to be formed, can include copper,
Any one in aluminium, magnesium, silver or its combination, because these metals have excellent electric conductivity, it is possible to for film is brilliant
Body pipe provides excellent electrical contact performance, but these metals are easily aoxidized.
To solve this problem, in step S104, corona treatment is carried out to metal level 1 using fluoro-gas, it is fluorine-containing
Gas mainly includes SiF4 gases and nitrogen.
Fig. 3 shows to carry out Source and drain metal level using fluoro-gas the artwork of corona treatment.As shown in figure 3, adopting
Corona treatment is carried out to metal level 1 with SiF4 gases and nitrogen, in processing procedure, SiF4 gases and nitrogen are by plasma
Bodyization can produce fluoro-containing group, and the oxidisability of these fluoro-containing groups is more stronger than oxygen, in the presence of these fluoro-containing groups, gold
Category will not react with the oxygen in air, and fluoro-containing group blocks metal with sky equivalent to diaphragm is formd on the metal surface
Oxygen in gas reacts, so as to improve the antioxygenic property of metal.
Traditional source layer and drain electrode layer respectively have layer protective layer up and down, are three-decker, in the present embodiment, metal
Layer have passed through the corona treatment of fluoro-gas, enhance antioxygenic property, and source layer and drain electrode layer upper and lower part are no longer
Need protective layer, the structure of source layer and drain electrode layer can be simplified.
Additionally, as shown in figure 4, after by the bombardment of plasma, the surface roughness of metal level 1 is improved, and so may be used
With the adhesion between the photoresist during strengthening metal level and subsequent process, prevent the phenomenon of photoresist lift off from occurring.
Then, source electrode is formed respectively to the treatment such as performing etching by the metal level after above-mentioned treatment in step S105
Layer and drain electrode layer.
Finally, passivation insulation is deposited after the source layer and drain electrode layer is formed, and passivation insulation is carried out
Patterning, the main component of passivation insulation is silica, then redeposited tin indium oxide (ITO) film layer, and carries out figure
Case, to form pixel electrode layer.
In the present embodiment, metal level i.e. source layer and drain electrode layer are carried out at plasma using fluoro-gas
Reason, improves the inoxidizability of source-drain electrode, and source layer and drain electrode layer are by traditional three-layered node for respectively having layer protective layer up and down
Structure, is simplified, and reduces the contact resistance of source-drain electrode and raceway groove, and source layer and drain electrode layer by plasma bombardment
Afterwards, surface roughness is improved, and can strengthen the adhesion between source layer and drain electrode layer and photoresist, prevents photoresist
Stripping, improve technique yield.
Embodiment two
The present embodiment provides a kind of thin film transistor (TFT).
Thin film transistor (TFT) according to the present embodiment includes：Substrate；Grid layer, gate insulation layer and active layer, are formed in described
On substrate；Source layer and drain electrode layer, are formed in the active layer, wherein, the source layer and drain electrode layer are by having
The metal level deposited in active layer performs etching treatment and is formed.The metal level i.e. the source layer and drain electrode layer are wrapped respectively
Include any one or its combination in copper, aluminium, magnesium, silver.
Before treatment is performed etching to metal level, anti-oxidant treatment is first carried out to metal level, that is, using containing fluorine gas
Body carries out corona treatment to metal level.The composition of the fluoro-gas include SiF4 gases and nitrogen, by treatment after,
Anti-oxidation protection film is formed in layer on surface of metal, the inoxidizability of metal level i.e. source layer and drain electrode layer is improve, it is former
Reason has been described above in embodiment one, and description is not repeated herein.
After the source layer and drain electrode layer are by the corona treatment of fluoro-gas, antioxygenic property is improved,
Do not need traditional structure in, in the protective layer that the upper and lower part of source layer and drain electrode layer is respectively provided with.So, source layer and leakage
The structure of pole layer can be simplified.The structure simplification of source layer and drain electrode layer can reduce source layer and drain electrode layer with raceway groove
Contact resistance.And source layer and drain electrode layer, after by plasma bombardment, the roughness on surface is improved, follow-up
Technical process in, the adhesion between source layer and drain electrode layer and photoresist is enhanced, and improves the yield of technique.
Thin film transistor (TFT) according to the present embodiment also includes being formed in the passivation insulation on the source layer and drain electrode layer
Layer and pixel electrode layer, the main component of the passivation insulation is silica, and the main component of the pixel electrode layer is
Tin indium oxide (ITO).
Embodiments of the invention also provide a kind of array base palte, including foregoing thin film transistor (TFT), and a kind of liquid
Crystal display, including described array base palte.
Note, above are only the principle of presently preferred embodiments of the present invention and institute's application technology.Those skilled in the art should
Understand, the invention is not restricted to specific embodiment described here, can carry out for a person skilled in the art various obvious
Change, readjust and substitute without departing from protection scope of the present invention.Therefore, although by above example to the present invention
It is described in further detail, but the present invention is not limited only to above example, is not departing from the situation of present inventive concept
Under, more other Equivalent embodiments can also be included, and the scope of the present invention is determined by appended claim.
Claims (10)
1. a kind of preparation method of thin film transistor (TFT), including：
Substrate is provided；
Grid layer, gate insulation layer and active layer are formed on the substrate；
Deposited metal layer, uses fluoro-gas to carry out corona treatment to improve table to the metal level on the active layer
The roughness in face, to treatment after the metal level perform etching treatment, respectively formed source layer and drain electrode layer.
2. the preparation method of thin film transistor (TFT) as claimed in claim 1, wherein, the composition of the fluoro-gas include SiF4 and
N2。
3. the preparation method of thin film transistor (TFT) as claimed in claim 1, wherein, the source layer and the drain electrode layer are wrapped respectively
Include any one or its combination in copper, aluminium, magnesium, silver.
4. the preparation method of thin film transistor (TFT) as claimed in claim 1, be additionally included in be formed the source layer and drain electrode layer it
After deposit passivation insulation, and the passivation insulation is patterned, then pixel deposition electrode layer.
5. a kind of thin film transistor (TFT), including：
Substrate；
Grid layer, gate insulation layer and active layer, are formed on the substrate；
Source layer and drain electrode layer, are formed in the active layer, wherein, the source layer and drain electrode layer are by fluoro-gas
Corona treatment.
6. thin film transistor (TFT) as claimed in claim 5, wherein, the composition of the fluoro-gas includes SiF4 and N2.
7. thin film transistor (TFT) as claimed in claim 5, wherein, the source layer and the drain electrode layer include respectively copper, aluminium,
Any one in magnesium, silver or its combination.
8. thin film transistor (TFT) as claimed in claim 5, it is also exhausted including being formed in passivation on the source layer and drain electrode layer
Edge layer and pixel electrode layer.
9. a kind of array base palte, including the thin film transistor (TFT) as described in any in claim 5-8.
10. a kind of display, including array base palte as claimed in claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710277714.0A CN106920753B (en) | 2017-04-25 | 2017-04-25 | Thin film transistor, manufacturing method thereof, array substrate and display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710277714.0A CN106920753B (en) | 2017-04-25 | 2017-04-25 | Thin film transistor, manufacturing method thereof, array substrate and display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106920753A true CN106920753A (en) | 2017-07-04 |
| CN106920753B CN106920753B (en) | 2020-04-03 |
Family
ID=59567369
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710277714.0A Active CN106920753B (en) | 2017-04-25 | 2017-04-25 | Thin film transistor, manufacturing method thereof, array substrate and display |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106920753B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109727911A (en) * | 2018-12-10 | 2019-05-07 | 昆山龙腾光电有限公司 | Method for manufacturing thin film transistor array substrate |
| CN110335849A (en) * | 2019-06-25 | 2019-10-15 | 深圳市华星光电半导体显示技术有限公司 | Display device, array substrate and preparation method thereof |
| CN112002754A (en) * | 2020-08-11 | 2020-11-27 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, preparation method thereof and display panel |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1954413A (en) * | 2004-05-20 | 2007-04-25 | Psk有限公司 | Method for cleaning substrate surface |
| CN203423187U (en) * | 2013-04-10 | 2014-02-05 | 合肥京东方光电科技有限公司 | Thin film transistor, array substrate, and display device |
| CN106257618A (en) * | 2015-06-19 | 2016-12-28 | 东京毅力科创株式会社 | Use the film build method of plasma |
-
2017
- 2017-04-25 CN CN201710277714.0A patent/CN106920753B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1954413A (en) * | 2004-05-20 | 2007-04-25 | Psk有限公司 | Method for cleaning substrate surface |
| CN203423187U (en) * | 2013-04-10 | 2014-02-05 | 合肥京东方光电科技有限公司 | Thin film transistor, array substrate, and display device |
| CN106257618A (en) * | 2015-06-19 | 2016-12-28 | 东京毅力科创株式会社 | Use the film build method of plasma |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109727911A (en) * | 2018-12-10 | 2019-05-07 | 昆山龙腾光电有限公司 | Method for manufacturing thin film transistor array substrate |
| CN110335849A (en) * | 2019-06-25 | 2019-10-15 | 深圳市华星光电半导体显示技术有限公司 | Display device, array substrate and preparation method thereof |
| CN110335849B (en) * | 2019-06-25 | 2021-11-02 | 深圳市华星光电半导体显示技术有限公司 | Display device, array substrate and manufacturing method thereof |
| CN112002754A (en) * | 2020-08-11 | 2020-11-27 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, preparation method thereof and display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106920753B (en) | 2020-04-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107481934B (en) | A kind of production method of thin film transistor (TFT) | |
| CN102646632B (en) | Array substrate, manufacturing method thereof and display device | |
| CN105914183B (en) | The manufacturing method of TFT substrate | |
| US9761616B2 (en) | Manufacturing method of array substrate with reduced number of patterning processes array substrate and display device | |
| US9455324B2 (en) | Thin film transistor and method of fabricating the same, array substrate and method of fabricating the same, and display device | |
| US20190181161A1 (en) | Array substrate and preparation method therefor, and display device | |
| WO2017008497A1 (en) | Method of manufacturing oxide thin film transistor | |
| CN107464820A (en) | ESL type TFT substrates and preparation method thereof | |
| CN104576523A (en) | Array substrate, production method of array substrate and display device | |
| CN103715137A (en) | Array substrate, manufacturing method thereof and display device | |
| US20200343329A1 (en) | Array substrate, manufacturing method therefor, and display device | |
| CN107369715A (en) | A kind of manufacture method of thin film transistor (TFT) | |
| CN107658345A (en) | Oxide thin film transistor and preparation method thereof, array base palte and display device | |
| CN106920753A (en) | Thin film transistor (TFT) and preparation method thereof, array base palte and display | |
| CN107799466A (en) | TFT substrate and preparation method thereof | |
| WO2020232964A1 (en) | Method for preparing thin film transistor substrate | |
| CN106887379A (en) | A kind of semi-transparent mask patterning process and array base palte, display device | |
| CN105140234B (en) | Array base palte and its manufacture method, display device | |
| US9508762B2 (en) | Array substrate, method of manufacturing array substrate and display device | |
| WO2020140750A1 (en) | Thin film transistor, thin film transistor manufacturing method and display device | |
| WO2017012292A1 (en) | Array substrate, preparation method thereof, display panel and display device | |
| CN106340543A (en) | Thin film transistor, array substrate, manufacturing method of array substrate and display panel | |
| CN104617049A (en) | Array substrate and manufacturing method thereof as well as display device | |
| CN208738252U (en) | Dot structure and array substrate | |
| CN102655116B (en) | Manufacturing method for array substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |