CN107369715A - A kind of manufacture method of thin film transistor (TFT) - Google Patents
A kind of manufacture method of thin film transistor (TFT) Download PDFInfo
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- CN107369715A CN107369715A CN201710569319.XA CN201710569319A CN107369715A CN 107369715 A CN107369715 A CN 107369715A CN 201710569319 A CN201710569319 A CN 201710569319A CN 107369715 A CN107369715 A CN 107369715A
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 239000010409 thin film Substances 0.000 title claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 69
- 229910052751 metal Inorganic materials 0.000 claims abstract description 63
- 239000002184 metal Substances 0.000 claims abstract description 63
- 239000004065 semiconductor Substances 0.000 claims abstract description 63
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 35
- 238000012545 processing Methods 0.000 claims abstract description 11
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 239000011248 coating agent Substances 0.000 claims abstract 2
- 238000000576 coating method Methods 0.000 claims abstract 2
- 239000000463 material Substances 0.000 claims description 29
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 28
- 229910052802 copper Inorganic materials 0.000 claims description 28
- 239000010949 copper Substances 0.000 claims description 28
- MUBZPKHOEPUJKR-UHFFFAOYSA-N Oxalic acid Chemical compound OC(=O)C(O)=O MUBZPKHOEPUJKR-UHFFFAOYSA-N 0.000 claims description 18
- 239000002253 acid Substances 0.000 claims description 16
- 239000003795 chemical substances by application Substances 0.000 claims description 10
- 238000001039 wet etching Methods 0.000 claims description 10
- 238000001312 dry etching Methods 0.000 claims description 6
- 235000006408 oxalic acid Nutrition 0.000 claims description 6
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 5
- 229910052801 chlorine Inorganic materials 0.000 claims description 5
- 239000000460 chlorine Substances 0.000 claims description 5
- 230000003247 decreasing effect Effects 0.000 claims description 5
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 4
- 229910052731 fluorine Inorganic materials 0.000 claims description 4
- 239000011737 fluorine Substances 0.000 claims description 4
- 230000008569 process Effects 0.000 abstract description 11
- 239000010410 layer Substances 0.000 description 133
- 238000005516 engineering process Methods 0.000 description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 8
- 239000010936 titanium Substances 0.000 description 8
- 229910052719 titanium Inorganic materials 0.000 description 8
- 238000001259 photo etching Methods 0.000 description 6
- 229910021419 crystalline silicon Inorganic materials 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 239000007788 liquid Substances 0.000 description 5
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- 239000011733 molybdenum Substances 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000005111 flow chemistry technique Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention provides a kind of manufacture method of type thin film transistor (TFT), and method comprises the following steps：It is sequentially depositing semiconductor layer, metal level；Side's coating photoresist layer on the metal layer；Processing is exposed to photoresist layer, patterns photoresist layer, a portion forms glimmer resistance layer, and remainder forms thick photoresist layer or without photoresist layer；Etch for the first time, etching sheet metal and semiconductor layer, remove the part of no photoresist layer covering；Photoresist layer is ashed, glimmer resistance layer is removed, exposes the metal level below glimmer resistance layer；Second of etching, etching sheet metal, forms source electrode, drain electrode and channel region, exposes the semiconductor layer positioned at channel region；Remove removing photoresistance layer.The present invention reduces one of light shield number, reduces the manufacturing cost of thin film transistor (TFT), optimize technological process by proposing a kind of manufacture method.
Description
Technical field
The invention belongs to the technical field of thin film transistor (TFT), more particularly to a kind of manufacture method of thin film transistor (TFT).
Background technology
In panel display apparatus, Thin Film Transistor-LCD (Thin Film Transistor Liquid
Crystal Display, abbreviation TFT-LCD) have the characteristics that small volume, low in energy consumption, manufacturing cost be relatively low and Low emissivity.
And in order to form TFT (Thin Film Transistor, thin film transistor (TFT)) array on the transparent substrate, in TFT
In array production technique, it is necessary to using a number of photomask blank (Photo Mask) surface be repeated film forming,
The photoetching processes such as exposure, etching, to form the lead of tft array, electrode, terminal, each insulating film layer etc..From TFT- in 1993
Since LCD mass production starts, in order to reduce production cost, the yields of product is improved, each manufacturer is not open close
The structure design for changing TFT is crossed, makes great efforts to reduce the photoetching process number in array processes.It has been difficult by TFT structure at present
Change to reduce the number of photoetching process, existing photoetching process can only be improved in itself.
In the TFT processing procedures of existing non-crystalline silicon, PEP (Photo Etching Process, the photoetching work of 5 times are generally carried out
Skill) to realize, production cost is high, process number is more.Maturely use MTM (Multi-Tone Mask, multisection type at present
Light shield is adjusted, there are the different penetrances in addition to full impregnated light/light tight), and BCE (Back Channel Etching,
Carry on the back channel etching) technology, script is needed to the PEP of 5 times light shield number, is reduced to 4 times.
Specifically, exactly channel layer and metal level by channel region and source electrode and are drained using 1 MTM gold-tinteds processing procedure
Image is disposably exposed on the deposited substrate of gate insulator and grid excessively, recycles etching technics to complete whole thin
The back of the body raceway groove of film transistor.
However, therefore non-crystalline silicon, uses IGZO as the semiconductor layer shortcoming such as have short life, electricity conversion low
(indium gallium zinc oxide) material has the advantages of cost is low, load electron mobility is high, efficiency is more preferable as semiconductor layer, is a kind of
New panel technology.IGZO TFT processing procedures in recent years, have been widely used in the liquid crystal display of large, medium and small size, still
The IPS (In-Plane Switching, plane conversion) of high-end applications technology, still at least need the PEP of 9 times light shield
Number；Wherein again with ESL (Etching Stop Layer, etching barrier layer) technology be current IGZO main flow processing procedure.It is but every
Often have more 1 PEP, it is meant that the increase of cost of manufacture, therefore reduce the task of top priority that PEP numbers are current IGZO TFT technologies.
But different from non-crystalline silicon tft, except semi-conducting material is different, the selection of source electrode and drain material is also different.Cause
This, IGZO TFT process parameter and process conditions also will not be identical with non-crystalline silicon tft, that is to say, that IGZO processing procedures
TFT techniques must have a set of flow of oneself, can not replicate the processing procedure of non-crystalline silicon tft completely.
Therefore, in this case, in order to solve above-mentioned technical problem present in prior art, the present invention proposes a kind of
New type thin film transistor (TFT) and its manufacture method, so as to effectively reduce PEP quantity, reduce production cost.
The content of the invention
It is an object of the invention to provide a kind of manufacture method for the thin film transistor (TFT) that can reduce production cost.
The present invention provides a kind of manufacture method of thin film transistor (TFT), and this method includes：
The first step, it is sequentially depositing semiconductor layer, source-drain electrode metal level；
Second step, photoresist layer is coated with the metal layer；
3rd step, processing is exposed to the photoresist layer, patterns the photoresist layer, a portion forms glimmer resistance
Layer, remainder form thick photoresist layer or without photoresist layers；
4th step, etch for the first time, etch the metal level and semiconductor layer, remove the part of no photoresist layer covering；
5th step, the photoresist layer is ashed, removes the glimmer resistance layer, expose the gold below the glimmer resistance layer
Belong to layer；
6th step, second of etching, etches the metal level, forms source electrode, drain electrode and channel region, exposes positioned at institute
State the semiconductor layer of channel region；
7th step, removes removing photoresistance layer.
Preferably, the first time etching is disposably to etch the metal level and semiconductor layer.
Preferably, the first time etching is divided into two steps：
The first step, the metal level is etched, remove the part of no photoresist layer covering, add dry etching using wet etching or wet etching；
Second step, the semiconductor layer is etched, remove the part of no photoresist layer covering.
Preferably, the metal level is double layer of metal structure, and the etching rate of primer is less than the etching rate of quilting material.
Preferably, the semiconductor layer is IGZO semiconductor layers or IGZTO semiconductor layers.
Preferably, the semiconductor layer has two layers or more than two layers structure.
Preferably, the semiconductor layer is the double-layer structure that bottom is IGZO materials, top layer is IGZTO materials
Preferably for the metal level and semiconductor layer, from the etching rate of quilting material to the etching rate of primer,
It is monotone decreasing from large to small that it, which changes,.
Preferably, fluorine-containing copper acid is selected to be used as etching agent.
Preferably, floride-free copper acid and oxalic acid is selected to be used as and carve as etching agent or selection floride-free copper acid, chlorine and oxalic acid
Lose agent.
Brief description of the drawings
Fig. 1-Fig. 6 is the step schematic diagram of the manufacture method of thin film transistor (TFT) of the present invention.
Embodiment
Below in conjunction with the accompanying drawings and specific embodiment, the present invention is furture elucidated, it should be understood that these embodiments are merely to illustrate
The present invention rather than limitation the scope of the present invention, after the present invention has been read, those skilled in the art are each to the present invention's
The modification of the kind equivalent form of value falls within the application appended claims limited range.
Fig. 1-Fig. 6 is the step schematic diagram of the manufacture method of thin film transistor (TFT) of the present invention, wherein (a) is pixel portion/GDM
Portion, (b) are portion of terminal.
The manufacture method of thin film transistor (TFT) of the present invention includes：
The first step, it is sequentially depositing semiconductor layer 2, source-drain electrode metal level 3.
Second step, is coated with photoresist layer 4 above metal level 3, and photoresist layer 4 is covered in the surface of metal level 3.3rd step, such as
Shown in Fig. 1, processing is exposed to photoresist layer 4, using one of MTM gold-tinted processing procedure, by corresponding light shield, completes photoresist layer
Pattern makes, wherein, a part for photoresist layer 4 is glimmer resistance layer 5, and glimmer resistance layer 5 is located at the position for being subsequently formed channel region, its
Remaining part is divided into thick photoresist layer or without photoresist layer
4th step, first time etching, etching sheet metal 3 and semiconductor layer 2 are carried out, the two is located at without photoresist layer covering
Part removes.
Specifically, first, as shown in Fig. 2 first carrying out first time etching to metal level 3, metal level 3 is located at without photoresist layer
Part remove.
Secondly, as shown in figure 3, carrying out first time etching to semiconductor layer 2 again, same be located at semiconductor layer 2 is unglazed
The part of resistance layer removes.
Thus, complete to etch for the first time.
5th step, photoresist layer 4 is ashed, as shown in figure 4, using pure oxygen either oxygen containing mixed gas, passes through grey chemical industry
Skill, glimmer resistance layer 4 is removed, expose the metal level 3 positioned at the lower section of glimmer resistance layer 4.
6th step, carry out second and etch, as shown in figure 5, the metal level 4 exposed in etching previous step, completes source electrode
Made with the pattern of drain electrode, and form channel region 6, expose the semiconductor layer positioned at channel region 6.
7th step, as shown in fig. 6, removing removing photoresistance layer 4.
Metal level 3 can be any structure, it is preferable that metal level 3 is double-layer structure.Semiconductor layer can be metal oxidation
Thing material, it is preferable that be IGZO materials.
In the 4th step, etching is carried out in two steps for the first time, when to metal level 3 etch for the first time, for gold
Belong to the different overlapping shelf structures of layer 3, it is necessary to using different etching modes.For example, metal level 3 is bottom molybdenum layer, top layer layers of copper
Overlapping shelf structure when, etching liquid can select floride-free copper acid, and metal level 3 is disposably etched；Metal level 3 is bottom titanium
Layer, top layer layers of copper overlapping shelf structure when, first using the layers of copper of floride-free copper acid etch metal level 3, recycle chlorine dry etching metal level 3
Titanium layer.And when to semiconductor layer 2 etch for the first time, for example, when semiconductor layer 2 is IGZO materials, oxalic acid can be used,
Complete the etching to semiconductor layer 2.Therefore, it is necessary to using two or more etching mode, completion pair in the 4th step
The etching of metal level 3 and semiconductor layer 2.
As the 4th step of the invention or disposable being completed to metal level 3 and half with alternative embodiment
The etching of conductor layer 2.For example, metal level 3 is bottom titanium layer, the overlapping shelf structure of top layer layers of copper, semiconductor layer 2 is IGZO materials
When, fluorine-containing copper acid can be selected to be used as etching liquid, disposable etching copper layer, titanium layer and IGZO semiconductor layers, a step is just completed
To the etching of metal level 3 and semiconductor layer 2.Thus, compared to previous embodiment, the step of changing etching liquid can be saved,
It is effective to simplify etch process flow, reduce manufacturing cost.
It is worth noting that, no matter metal level 3 and semiconductor layer 2 use which kind of material and which kind of framework, from top layer material
For the etching rate of material to the etching rate of primer, the change of its etching rate must be monotone decreasing from large to small.For example, layers of copper
＞ titanium layers ＞ IGZO semiconductor layers or layers of copper ＞ molybdenum layer ＞ IGZO semiconductor layers.
Likewise, the 6th step of the present invention, can select fluorine-containing copper acid to be used as etching liquid, but for the choosing of etching agent
Select, it is necessary to meet that the etching rate for getting over primer is smaller, this is due to after first time etching technics the half of all image districts
The side of conductor layer has been exposed through, so when etching for second, the etching agent of semiconductor layer will not be damaged by being only capable of use
Etching sheet metal 3, avoid causing to undercut (Under Cut) phenomenon, cause the line width distortion of figure, and then influence IGZO TFT's
Characteristic.It is an option that adding Sn (tin) in the IGZO for forming semiconductor layer, IGZTO is formed, so as to improve anticorrosive energy
Power.
The present invention the 6th step, its main purpose is to form BCE result, therefore, to semiconductor layer in itself and need not
Etching.Therefore, for the etching mode of the metal level in channel region, wet etching either wet etching can be selected to add dry etching, this is
Determined according to the metal material of metal level., can be with for example, if metal level 3 is bottom molybdenum layer, the overlapping shelf structure of top layer layers of copper
Floride-free copper acid is selected, disposable etching is done and the semiconductor layer positioned at channel region and all figures for exposing will not be hurt
As the side of the semiconductor layer in area.Metal level 3 be bottom titanium layer, top layer layers of copper overlapping shelf structure when, then can select floride-free copper
Acid does the etching of layers of copper, reuses chlorine dry etching titanium layer.In a word, no matter the metal material of metal level is how to select, its is final
For the purpose of not injuring semiconductor layer.
The semiconductor layer of the present invention is the IGZO materials of individual layer, and in other embodiments, the structure of semiconductor layer is not only
Single layer structure is limited to, has the stacked architecture more than double-deck or double-deck for semiconductor layer, is equally applicable to the film of the present invention
The manufacture method of transistor.For example, semiconductor layer is bottom is IGZO materials, the double-layer structure that top layer is IGZTO materials.But
Be, it should be noted that from the metal material of the superiors of metal level to the IGZO materials of the bottom of semiconductor layer, each other it
Between etching rate relation must monotone decreasing from large to small.The purpose so done be exactly in order to form good gentle slope, so as to
Be advantageous to the stepcoverage (Step Coverage) of the making technology of rear layer.
In addition, because present invention uses MTM and BCE techniques, therefore have semiconductor layer under source electrode and drain electrode, then
Source electrode and the metal wiring of drain electrode will be unable to be directed through the next direct turn-on grid electrode of contact hole (Contact hole), it is necessary to thoroughly
Later the conductive material layer of layer, such as the figure of public electrode either pixel electrode bridge.It is simply that source electrode and
Drain electrode can not be directed through contact hole and directly contact grid, and the conductive layer all necessarily continued rearward bridges.
The pellicle area for the MTM that the present invention uses, can be that single seam can also be semipermeable membrane material, the transmitance of pellicle
For 20%~60%, as long as the photoresistance thickness that collocation is suitable.
In addition, in order to reduce existing IGZO semiconductor layers etching rate, can be with the new copper of etching liquid supplier joint development
Acid, adjustment wherein HF content；IGZO materials that can be stronger with target supplier development resistance to corrosion, as containing Sn
IGZTO materials；The total time disposably etched can be adjusted in etching technics；The annealing temperature of IGZO materials can also be improved
Degree.
In addition, the first step of the present invention can also be：Gate pattern is formed by metal level in surface, above grid
Gate insulator 1 is formed, semiconductor layer 2, metal level 3 are sequentially depositing on gate insulator 1.Wherein grid can be any knot
Structure, it is preferable that be double-layer structure, it is preferable that identical with the material of metal level 3.
In addition, the present invention can also include the 8th step：Gate insulator is formed above source electrode and drain electrode, in gate insulator
Layer top forms gate pattern by metal level.Wherein grid can be any structure, it is preferable that be double-layer structure, it is preferable that with
The material of metal level 3 is identical.
The first time etching of the present invention, both it can disposably complete to metal level and partly to lead in a manner of wet etching (copper acid)
The etching of body layer, etching flow stage by stage can also be performed：Such as floride-free copper acid wet etching layers of copper and chlorine dry etching can be used
Titanium layer, or using the disposable wet etching layers of copper of floride-free copper acid and molybdenum layer, then recycle oxalic acid wet etching semiconductor layer.But
No matter which kind of scheme is used, because after first time etching technics, the side of semiconductor layer has been exposed through, therefore to metal level
Second of etching when, the etching agent of semiconductor layer will not be damaged by being only capable of use, to avoid semiconductor layer from forming the disconnected of undercutting
Face structure, and then yield and the reliability issues such as source-drain electrode broken string occur.Meanwhile in first time etching and second etch,
In selective etching agent, for metal level and semiconductor layer, from the etching rate of quilting material to the etching rate of primer, it becomes
Change is monotone decreasing from large to small.
The present invention is based on BCE technologies, for IGZO TFT processing procedure, using MTM technologies, reduces one of light shield number, so as to
Simplification of flowsheet, the technique effect for reducing manufacturing cost is reached.
Claims (10)
1. a kind of manufacture method of thin film transistor (TFT), it is characterised in that this method includes：
The first step, it is sequentially depositing semiconductor layer (2) and metal level (3)；
Second step, the coating photoresist layer (4) above the metal level (3)；
3rd step, processing is exposed to the photoresist layer (4), patterns the photoresist layer (4), a portion forms glimmer
Resistance layer (5), remainder form thick photoresist layer or without photoresist layers；
4th step, the metal level (3) and semiconductor layer (2) are etched, remove the part of no photoresist layer covering；
5th step, the photoresist layer is ashed, removes the glimmer resistance layer (5), exposed below the glimmer resistance layer (5)
Metal level；
6th step, the metal level is etched, form source electrode, drain electrode and channel region (6), expose positioned at the channel region (6)
Semiconductor layer；
7th step, remove removing photoresistance layer (4).
2. manufacture method according to claim 1, it is characterised in that the 4th step is disposably to etch the metal
Layer (3) and semiconductor layer (2).
3. manufacture method according to claim 1, it is characterised in that the 4th step is specifically divided into two steps：
The first step, the metal level (3) is etched, remove the part of no photoresist layer covering, add dry etching using wet etching or wet etching；
Second step, the semiconductor layer (2) is etched, remove the part of no photoresist layer covering.
4. manufacture method according to claim 1, it is characterised in that the metal level (3) is double layer of metal structure, bottom
The etching rate of material is less than the etching rate of quilting material.
5. manufacture method according to claim 1, it is characterised in that the semiconductor layer (2) be IGZO semiconductor layers or
IGZTO semiconductor layers.
6. manufacture method according to claim 1, it is characterised in that the semiconductor layer (2) have two layers or two layers with
Upper structure.
7. manufacture method according to claim 6, it is characterised in that the semiconductor layer (2) be bottom for IGZO materials,
Top layer is the double-layer structure of IGZTO materials.
8. manufacture method according to claim 1, it is characterised in that for the metal level (3) and semiconductor layer (2),
From the etching rate of quilting material to the etching rate of primer, it is monotone decreasing from large to small that it, which changes,.
9. manufacture method according to claim 2, it is characterised in that select fluorine-containing copper acid to be used as etching agent.
10. manufacture method according to claim 3, it is characterised in that select floride-free copper acid and oxalic acid as etching agent or
Person selects floride-free copper acid, chlorine and oxalic acid as etching agent.
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| CN201710569319.XA CN107369715A (en) | 2017-07-13 | 2017-07-13 | A kind of manufacture method of thin film transistor (TFT) |
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| CN201710569319.XA CN107369715A (en) | 2017-07-13 | 2017-07-13 | A kind of manufacture method of thin film transistor (TFT) |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109087953A (en) * | 2018-08-16 | 2018-12-25 | 南京中电熊猫液晶显示科技有限公司 | A kind of thin film transistor (TFT) and its manufacturing method |
| WO2019104849A1 (en) * | 2017-11-30 | 2019-06-06 | 武汉华星光电半导体显示技术有限公司 | Method for manufacturing thin film transistor and method for manufacturing array substrate |
| WO2019127724A1 (en) * | 2017-12-28 | 2019-07-04 | 深圳市华星光电半导体显示技术有限公司 | Manufacturing method of thin film transistor, and manufacturing method of array substrate |
| CN110098259A (en) * | 2019-04-10 | 2019-08-06 | 深圳市华星光电技术有限公司 | Amorphous silicon film transistor and preparation method thereof |
| CN110120426A (en) * | 2018-02-07 | 2019-08-13 | 南京中电熊猫平板显示科技有限公司 | A kind of manufacturing method and thin film transistor (TFT) of thin film transistor (TFT) |
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