CN110190065A - The production method of array substrate - Google Patents
The production method of array substrate Download PDFInfo
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- CN110190065A CN110190065A CN201910396335.2A CN201910396335A CN110190065A CN 110190065 A CN110190065 A CN 110190065A CN 201910396335 A CN201910396335 A CN 201910396335A CN 110190065 A CN110190065 A CN 110190065A
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- layer
- metal
- production method
- array substrate
- drain electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
Abstract
Present applicant proposes a kind of production methods of array substrate.The production method includes: to provide a substrate；The first film layer is formed on the substrate；Passivation layer is formed in first film layer；The first metal layer is formed on the passivation layer；Patterned process is being carried out to first film layer and the first metal layer in etch process with along with, to form active layer and source-drain electrode metal.The application by using with along with etch process active layer and source-drain electrode metal patterned, simplify the manufacture craft of array substrate, saved the cost of product.
Description
Technical field
This application involves field of display technology, in particular to a kind of production method of array substrate.
Background technique
Display panel is the display product being most widely used currently on the market, and production technology is very mature, is produced
Product yield is high, and production cost is relatively low, and market acceptance is high.
Known, display panel includes array substrate and color membrane substrates, and array substrate includes active layer and source-drain electrode metal.?
It needs to etch active layer and source-drain electrode metal respectively in the processing procedure of array substrate, so that active layer and source-drain electrode metal needs are each
It uses one of light shield technique and etch process to realize the patterning of active layer and source-drain electrode metal, leads to the preparation of array substrate
Technique is relatively cumbersome, and production cost is higher.
Therefore, a kind of production method of array substrate is needed at present to solve the above problems.
Summary of the invention
This application provides a kind of production methods of array substrate, to solve the pattern chemical industry of active layer and source-drain electrode metal
The problem of skill is complicated, higher cost.
To solve the above problems, technical solution provided by the present application is as follows:
This application provides a kind of production methods of array substrate, comprising steps of
S10, a substrate is provided；
S20, the first film layer is formed on the substrate；
S30, passivation layer is formed in first film layer；
S40, the first metal layer is formed on the passivation layer；
S50, patterned process is being carried out to first film layer and the first metal layer in etch process with along with, with
Form active layer and source-drain electrode metal.
In the production method of the application, the material for preparing of first film layer includes indium gallium zinc oxide.
In the production method of the application, the material for preparing of first film layer includes amorphous silicon.
In the production method of the application, the S30 includes: to form the second film layer on the active layer, to described
Two film layers carry out patterned process, to form passivation layer.
In the production method of the application, second film layer prepare material include in silicon nitride and silica wherein
One.
In the production method of the application, the S50 includes:
S501, photoresist layer is formed on the first metal layer；
S502, the photoresist layer is exposed and is developed using target light shield, to form the first photoresist design layer；
S503, the first etching is carried out to first film layer and the first metal layer using the first etching solution, to be formed
First pattern film and the first metal pattern layer；
S504, cineration technics is used to carry out patterned process to first photoresist design layer to form the second photoresist pattern
Layer；
S505, the second etching is carried out to first pattern film and the first metal pattern layer using the second etching solution, with
Form active layer and source-drain electrode metal；
S506, removing second photoresist design layer.
In the production method of the application, first etching solution and second etching solution include fluorine-containing copper acid.
In the production method of the application, the target light shield is halftone mask.
In the production method of the application, the active layer includes that the source-drain electrode at both ends corresponds to area and source-drain electrode corresponds to area
Between channel region, the production method further include:
S507, in a nitrogen environment corresponds to area to the source-drain electrode using annealing process and carries out conductor processing.
In the production method of the application, the substrate includes:
Substrate；
Gate metal over the substrate is set；
Gate insulation layer on the gate metal is set.
The utility model has the advantages that the application by using with along with etch process active layer and source-drain electrode metal patterned,
The manufacture craft for simplifying array substrate has saved the cost of product.
Detailed description of the invention
It, below will be to embodiment or the prior art in order to illustrate more clearly of embodiment or technical solution in the prior art
Attached drawing needed in description is briefly described, it should be apparent that, the accompanying drawings in the following description is only some of invention
Embodiment for those of ordinary skill in the art without creative efforts, can also be attached according to these
Figure obtains other attached drawings.
The step of Fig. 1 is a kind of production method of array substrate of the application is schemed；
Fig. 2A~2D is a kind of artwork of display panel production method of the application；
Fig. 3 is the structural schematic diagram of array substrate in step S507.
Specific embodiment
The explanation of following embodiment is referred to the additional illustration, the particular implementation that can be used to implement to illustrate the application
Example.The direction term that the application is previously mentioned, such as [on], [under], [preceding], [rear], [left side], [right side], [interior], [outer], [side]
Deng being only the direction with reference to annexed drawings.Therefore, the direction term used be to illustrate and understand the application, rather than to
Limit the application.The similar unit of structure is with being given the same reference numerals in the figure.
This application provides a kind of production methods of array substrate, to solve the pattern chemical industry of active layer and source-drain electrode metal
The problem of skill is complicated, higher cost.
Referring to Fig. 1, Fig. 1 schemes the step of being a kind of production method of array substrate 10 of the application.
According to the one aspect of the application, a kind of production method of array substrate 10 is provided, comprising steps of
Fig. 2A is please referred to, S10, provides a substrate.
The substrate includes the substrate 101, gate metal 102 and gate insulation layer 103 set gradually.
The S10 includes:
S101, a substrate 101 is provided；
S102, second metal layer is formed on the substrate 101, the second metal layer is carried out by figure using moist etching
Case is to form gate metal 102；
S103, gate insulation layer 103 is formed on the gate metal 102.
In one embodiment, the substrate 101 is the one of them in flexible substrate and rigid substrate.
When the substrate 101 is flexible substrate, the material for preparing of the flexible substrate includes polyimides；When the lining
When bottom 101 is rigid substrate, the rigid substrate uses glass preparation.
In one embodiment, the material for preparing of the gate metal 102 includes at least one of copper and molybdenum.
In one embodiment, the material for preparing of the gate insulation layer 103 includes wherein one in silicon nitride and silica
Person.
The second metal layer is formed on the substrate 101 by sputtering technology.
The gate insulation layer 103 is formed on the gate metal 102 by physical gas phase deposition technology, to by grid
Metal 102 and active layer 107 insulate.
In one embodiment, the gate insulation layer 103 is double-layer structure, i.e., the described gate insulation layer 103 includes silicon nitride
Layer and silicon oxide layer.
S20, the first film layer 104 is formed on the substrate.
The array substrate 10 includes the thin film transistor (TFT) of array distribution.
Thin film transistor (TFT) includes gate metal 102, gate insulation layer 103, has edge layer, passivation layer 105 and source-drain electrode metal
108。
In one embodiment, the material for preparing of first film layer 104 is indium gallium zinc oxide.It is corresponding, it is described
Thin film transistor (TFT) in array substrate 10 is IGZO thin film transistor (TFT).
In one embodiment, the material for preparing of first film layer 104 is amorphous silicon.It is corresponding, the array base
Thin film transistor (TFT) in plate 10 is LTPS thin film transistor (TFT).
Compared to LTPS thin film transistor (TFT), IGZO thin film transistor (TFT) has carrier mobility height, cost bottom, occupied space
Small advantage.
The present embodiment deposits the first film layer 104 by physical gas phase deposition technology on the substrate 101, to be subsequent
The preparation of active layer 107 provides basis.
Fig. 2 B is please referred to, S30, forms passivation layer 105 in first film layer 104.
Specifically, the S30 includes: to form the second film layer on the active layer 107, figure is carried out to second film layer
Caseization processing, to form passivation layer 105.
The material for preparing of second film layer includes the one of them in silica and silicon nitride.
Second film layer is deposited on the active layer 107 using physical gas phase deposition technology.
Patterned process is carried out to second film layer by using light shield technique, to form passivation layer 105, and then is realized
Insulation between active layer 107 and source-drain electrode metal 108.
Fig. 2 C is please referred to, S40, forms the first metal layer 106 on the passivation layer 105.
Preferably, the first metal layer 106 is deposited on the passivation layer 105 using sputtering technology.
The material for preparing of the first metal layer 106 includes copper and molybdenum.
Please refer to Fig. 2 D, S50, with along in etch process to first film layer 104 and the first metal layer 106
Patterned process is carried out, to form active layer 107 and source-drain electrode metal 108.
In one embodiment, the S50 includes:
S501, photoresist layer is formed on the first metal layer 106.
S502, the photoresist layer is exposed and is developed using target light shield, to form the first photoresist design layer.
The target light shield is halftone mask.When source-drain electrode metal 108 shape and active layer 107 shape have compared with
It, can be in the figure for realizing active layer 107 and source-drain electrode metal 108 in etch process with along with using halftone mask when big difference
Case.
S503, the first etching is carried out to first film layer 104 and the first metal layer 106 using the first etching solution,
To form the first pattern film and the first metal pattern layer.
In one embodiment, the first film layer 104 and the first metal layer 106 are etched to using the first etching solution
First wet etch.
S504, cineration technics is used to carry out patterned process to first photoresist design layer to form the second photoresist pattern
Layer.
In one embodiment, the processing for using cineration technics to carry out the first photoresist design layer is the first dry etch.
S505, the second etching is carried out to first pattern film and the first metal pattern layer using the second etching solution, with
Form active layer 107 and source-drain electrode metal 108.
Preferably, first etching solution and second etching solution include fluorine-containing copper acid.Due to fluorine-containing copper acid solution
Source-drain electrode metal 108 and metal oxide can be etched simultaneously, and then active layer 107 and source-drain electrode metal can be reached
108 layers are carrying out patterned purpose with along in etch process.
In one embodiment, fluorine-containing copper acid solution is less than to source-drain electrode metal the etch-rate of indium gallium zinc oxide
108 etch-rate can prevent active layer 107 from generating undercutting (undercut).
In one embodiment, the active layer 107 corresponds to area 109 including the source-drain electrode at both ends and source-drain electrode corresponds to area
Channel region 110 between 109, the source-drain electrode correspond to area 109 and are oppositely arranged with source-drain electrode metal 108, the channel region 110 with
The gate metal 102 is oppositely arranged.
S506, removing second photoresist design layer.
Referring to Fig. 3, Fig. 3 is the structural schematic diagram of array substrate 10 in step S507.
The production method further include: S507, in a nitrogen environment corresponds to area to the source-drain electrode using annealing process
109 carry out conductor processing.
In the high temperature environment, high temperature is spread since 101 side of substrate, since source-drain electrode corresponds to area 109 not by gate metal
102 block, therefore the oxonium ion in indium gallium zinc oxide can be in conjunction with the hydrogen ion in gate insulation layer 103, and then promotes the area
The electric conductivity in domain, to realize that source-drain electrode corresponds to the conductor in area 109.
According to another side of the application, a kind of production method of display panel, the system of the display panel are additionally provided
It include the production method of array substrate 10 and the production method of color membrane substrates, the production method of the array substrate 10 as method
Comprising steps of
S10, a substrate is provided.
In one embodiment, the substrate includes the substrate 101, gate metal 102 and gate insulation layer set gradually
103。
The S10 includes:
S101, a substrate 101 is provided；
S102, second metal layer is formed on the substrate 101, the second metal layer is carried out by figure using moist etching
Case is to form gate metal 102；
S103, gate insulation layer 103 is formed on the gate metal 102.
In one embodiment, the substrate 101 is the one of them in flexible substrate and rigid substrate.
When the substrate 101 is flexible substrate, the material for preparing of the flexible substrate 101 includes polyimides；Work as institute
State substrate 101 be rigid substrate when, the rigid substrate use glass preparation.
In one embodiment, the material for preparing of the gate metal 102 includes at least one of copper and molybdenum.
In one embodiment, the material for preparing of the gate insulation layer 103 includes wherein one in silicon nitride and silica
Person.
In one embodiment, the second metal layer is formed on the substrate 101 by sputtering technology.
In one embodiment, the gate insulation layer 103 is by physical gas phase deposition technology on the gate metal 102
It is formed, gate metal 102 and active layer 107 to insulate.
In one embodiment, the gate insulation layer 103 is double-layer structure, i.e., the described gate insulation layer 103 includes silicon nitride
Layer and silicon oxide layer.
S20, the first film layer 104 is formed on the substrate.
In one embodiment, the array substrate 10 includes the thin film transistor (TFT) of array distribution.
In one embodiment, thin film transistor (TFT) includes gate metal 102, gate insulation layer 103, has edge layer, passivation layer 105
With source-drain electrode metal 108.
In one embodiment, the material for preparing of first film layer 104 is indium gallium zinc oxide.
Corresponding, the thin film transistor (TFT) in the array substrate 10 is IGZO thin film transistor (TFT).
In one embodiment, the material for preparing of first film layer 104 is amorphous silicon.It is corresponding, the array base
Thin film transistor (TFT) in plate 10 is LTPS thin film transistor (TFT).
Compared to LTPS thin film transistor (TFT), IGZO thin film transistor (TFT) has carrier mobility height, cost bottom, occupied space
Small advantage.
In one embodiment, the first film layer 104 is deposited on the substrate 101 by physical gas phase deposition technology, used
Basis is provided with the preparation for subsequent active layer 107.
S30, passivation layer 105 is formed in first film layer 104.
In one embodiment, the S30 includes: to form the second film layer on the active layer 107, to second film
Layer carries out patterned process, to form passivation layer 105.
In one embodiment, the material for preparing of second film layer includes the one of them in silica and silicon nitride.
In one embodiment, the second film layer is deposited on the active layer 107 using physical gas phase deposition technology.
In one embodiment, patterned process is carried out to second film layer by using light shield technique, it is blunt to be formed
Change layer 105, and then realizes the insulation between active layer 107 and source-drain electrode metal 108.
S40, the first metal layer 106 is formed on the passivation layer 105.
In one embodiment, the first metal layer 106 is deposited on the passivation layer 105 using sputtering technology.
In one embodiment, the material for preparing of the first metal layer 106 includes copper and molybdenum.
S50, first film layer 104 and the first metal layer 106 are patterned in etch process with along with
Processing, to form active layer 107 and source-drain electrode metal 108.
In one embodiment, the S50 includes:
S501, photoresist layer is formed on the first metal layer 106.
S502, the photoresist layer is exposed and is developed using target light shield, to form the first photoresist design layer.
In one embodiment, the target light shield is halftone mask.When the shape and active layer of source-drain electrode metal 108
When 107 shape has larger difference, active layer 107 and source can realized with along with using halftone mask in etch process
The patterning of drain metal 108.
S503, the first etching is carried out to first film layer 104 and the first metal layer 106 using the first etching solution,
To form the first pattern film and the first metal pattern layer.
In one embodiment, the first film layer 104 and the first metal layer 106 are etched to using the first etching solution
First wet etch.
S504, cineration technics is used to carry out patterned process to first photoresist design layer to form the second photoresist pattern
Layer.
In one embodiment, the processing for using cineration technics to carry out the first photoresist design layer is the first dry etch.
S505, the second etching is carried out to first pattern film and the first metal pattern layer using the second etching solution, with
Form active layer 107 and source-drain electrode metal 108.
In one embodiment, first etching solution and second etching solution include fluorine-containing copper acid.Due to fluorine-containing
Copper acid solution can simultaneously be etched source-drain electrode metal 108 and metal oxide, and then can reach active layer 107 and source
108 layers of drain metal are carrying out patterned purpose with along in etch process.
In one embodiment, fluorine-containing copper acid solution is less than to source-drain electrode metal the etch-rate of indium gallium zinc oxide
108 etch-rate can prevent active layer 107 from generating undercutting (undercut) phenomenon.
In one embodiment, the active layer 107 corresponds to area 109 including the source-drain electrode at both ends and source-drain electrode corresponds to area
Channel region 110 between 109, the source-drain electrode correspond to area 109 and are oppositely arranged with source-drain electrode metal 108, the channel region 110 with
The gate metal 102 is oppositely arranged.
S506, removing second photoresist design layer.
In one embodiment, the production method further include: S507, in a nitrogen environment, using annealing process to institute
It states source-drain electrode and corresponds to the progress conductor processing of area 109.
In the high temperature environment, high temperature is spread since substrate side, is not blocked by gate metal since source-drain electrode corresponds to area, because
Oxonium ion in this indium gallium zinc oxide can be in conjunction with the hydrogen ion in gate insulation layer, and then promotes the electric conductivity in the region, with
Realize that source-drain electrode corresponds to the conductor in area.
The utility model has the advantages that the application by using with along with etch process active layer and source-drain electrode metal patterned,
The manufacture craft for simplifying array substrate has saved the cost of product.
Although above preferred embodiment is not to limit in conclusion the application is disclosed above with preferred embodiment
The application processed, those skilled in the art are not departing from spirit and scope, can make various changes and profit
Decorations, therefore the protection scope of the application subjects to the scope of the claims.
Claims (10)
1. a kind of production method of array substrate, which is characterized in that comprising steps of
S10, a substrate is provided；
S20, the first film layer is formed on the substrate；
S30, passivation layer is formed in first film layer；
S40, the first metal layer is formed on the passivation layer；
S50, patterned process is being carried out to first film layer and the first metal layer in etch process with along with, to be formed
Active layer and source-drain electrode metal.
2. the production method of array substrate according to claim 1, which is characterized in that first film layer prepares material
Including indium gallium zinc oxide.
3. the production method of array substrate according to claim 1, which is characterized in that first film layer prepares material
Including amorphous silicon.
4. the production method of array substrate according to claim 1, which is characterized in that the S30 includes: described active
The second film layer is formed on layer, patterned process is carried out to second film layer, to form passivation layer.
5. the production method of array substrate according to claim 4, which is characterized in that second film layer prepares material
Including the one of them in silicon nitride and silica.
6. the production method of array substrate according to claim 1, which is characterized in that the S50 includes:
S501, photoresist layer is formed on the first metal layer；
S502, the photoresist layer is exposed and is developed using target light shield, to form the first photoresist design layer；
S503, the first etching is carried out to first film layer and the first metal layer using the first etching solution, to form first
Pattern film and the first metal pattern layer；
S504, cineration technics is used to carry out patterned process to first photoresist design layer to form the second photoresist design layer；
S505, the second etching is carried out to first pattern film and the first metal pattern layer using the second etching solution, to be formed
Active layer and source-drain electrode metal；
S506, removing second photoresist design layer.
7. the production method of array substrate according to claim 6, which is characterized in that first etching solution and described
Two etching solutions include fluorine-containing copper acid.
8. the production method of array substrate according to claim 6, which is characterized in that the target light shield is halftoning light
Cover.
9. the production method of array substrate according to claim 6, which is characterized in that the active layer includes the source at both ends
The corresponding area of drain electrode and source-drain electrode correspond to the channel region between area, the production method further include:
S507, in a nitrogen environment corresponds to area to the source-drain electrode using annealing process and carries out conductor processing.
10. the production method of array substrate according to claim 1, which is characterized in that the substrate includes:
Substrate；
Gate metal over the substrate is set；
Gate insulation layer on the gate metal is set.
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| CN201910396335.2A CN110190065A (en) | 2019-05-14 | 2019-05-14 | The production method of array substrate |
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| CN201910396335.2A CN110190065A (en) | 2019-05-14 | 2019-05-14 | The production method of array substrate |
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- 2019-05-14 CN CN201910396335.2A patent/CN110190065A/en active Pending
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| CN102566148A (en) * | 2010-11-04 | 2012-07-11 | 乐金显示有限公司 | Liquid crystal display panel and method for fabricating the same |
| CN105514127A (en) * | 2016-02-25 | 2016-04-20 | 昆山龙腾光电有限公司 | Oxide thin-film transistor array substrate, production method thereof and liquid crystal display panel |
| CN106920754A (en) * | 2017-02-17 | 2017-07-04 | 深圳市华星光电技术有限公司 | A kind of thin film transistor (TFT) and preparation method thereof |
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Application publication date: 20190830 |