CN109712993A - Array substrate and manufacturing method and display device - Google Patents
Array substrate and manufacturing method and display device Download PDFInfo
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- CN109712993A CN109712993A CN201910001744.8A CN201910001744A CN109712993A CN 109712993 A CN109712993 A CN 109712993A CN 201910001744 A CN201910001744 A CN 201910001744A CN 109712993 A CN109712993 A CN 109712993A
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Abstract
The present invention relates to field of liquid crystal display, disclose a kind of array substrate, comprising: thin film transistor (TFT)；The thin film transistor (TFT) includes: substrate；Grid is formed over the substrate；Gate insulating layer is formed on the grid and the substrate；Form the active layer and pixel electrode layer of same layer setting on the gate insulating layer；The channel region of the active layer is formed by metal conductive oxide layer semiconductor transformation processing；The pixel electrode layer is formed by metal conductive oxide layer；Source drain metal layer is formed on the active layer and the pixel electrode layer, including source electrode and drain electrode, and the source electrode and the drain electrode are electrically connected with the active layer respectively, and the drain electrode is electrically connected with the pixel electrode layer.Active layer and the same stratification of pixel electrode layer can be achieved in the present invention, in original arraying bread board structure basis, reduces light shield, greatly reduces production cost.
Description
Technical field
The present invention relates to field of liquid crystal display more particularly to array substrates and manufacturing method and display device.
Background technique
Liquid crystal display includes array substrate, opposite substrate and the liquid crystal layer between the two substrates, in array base
Plate face has thin film transistor (TFT) and pixel electrode etc. to the side of liquid crystal layer.Wherein, thin film transistor (TFT) generally comprises grid, active
Layer, source electrode and drain electrode.Specifically, the structure of thin film transistor (TFT) can be bottom gate type or top gate type, with the battle array of bottom-gate type configuration
For column substrate, as shown in Figure 1, include substrate 01, be sequentially located at grid 02 on substrate, gate insulating layer 03, active layer 04,
Source electrode 06, drain electrode 07, passivation layer 08 and pixel electrode 05.
No matter the array substrate of bottom-gate type configuration or the array substrate of top-gate type structure, needed in the preparation using mask plate
The component being patterned includes at least: the figure of grid, the figure of active layer, the figure of source electrode and drain electrode, passivation layer figure
And the figure of pixel electrode.Therefore, the preparation of above-mentioned array substrate is there are preparation process complexity, and manufacturing process is various, cost
The problems such as height, time-consuming.
Therefore, the technical issues of manufacture craft for how simplifying array substrate is those skilled in the art's urgent need to resolve.
Summary of the invention
In order to solve the above technical problems, the present invention provides a kind of array substrate and manufacturing method, light shield number can be reduced,
Save the cost.
Technical solution provided by the invention is as follows:
The invention discloses a kind of array substrates, comprising: thin film transistor (TFT)；The thin film transistor (TFT) includes:
Substrate；
Grid is formed over the substrate；
Gate insulating layer is formed on the grid and the substrate；
Form the active layer and pixel electrode layer of same layer setting on the gate insulating layer；The ditch of the active layer
Road area is formed by metal conductive oxide floor semiconductor transformation processing；The pixel electrode layer is by metal conductive oxide layer shape
At；
Source drain metal layer is formed on the active layer and the pixel electrode layer, including source electrode and drain electrode, the source
Pole and the drain electrode are electrically connected with the active layer respectively, and the drain electrode is electrically connected with the pixel electrode layer.
Preferably, further includes: the passivation layer in the source drain metal layer.
Preferably, further includes: the public electrode with the pixel electrode mutually insulated.
The invention also discloses a kind of manufacturing methods of array substrate, comprising:
Grid is formed on the substrate；
Gate insulating layer is formed on the substrate and the grid, to cover the grid and the substrate；
Depositing metal oxide conductive layer on the gate insulating layer etches the metal conductive oxide by exposure
Layer forms active layer and pixel electrode layer；
Source drain metal layer is formed on the metal conductive oxide layer, it is described active to etch removal part by exposure
Source drain metal layer on layer carries out semiconductor transformation processing to the part, forms the channel region of active layer；
The source drain metal layer is etched by exposure and obtains the source electrode and drain electrode of TFT device, and exposes the pixel electricity
Pole layer, the source electrode and the drain electrode are electrically connected with the active layer respectively, and the drain electrode is also electrically connected with the pixel electrode layer
It connects.
Preferably, further includes:
Passivation layer is formed in the source drain metal layer.
Preferably, further includes:
The common electrode layer with pixel electrode layer insulation is formed on the passivation layer.
Invention additionally discloses a kind of manufacturing methods of array substrate, comprising:
Grid is formed on the substrate；
Gate insulating layer is formed on the substrate and the grid, to cover the grid and the substrate；
Depositing metal oxide conductive layer on the gate insulating layer etches the metal conductive oxide by exposure
Layer forms active layer and pixel electrode layer；
Source drain metal layer is formed on the metal conductive oxide layer, full impregnated is formed by the light shield of different transmitances
Area, impermeable area and semi-transparent area；
The corresponding active layer in exposure etching full impregnated area, removes the source drain metal layer on the active layer of part, to this
Part carries out semiconductor transformation processing, forms the channel region of active layer；
It is ashed photoresist, exposes the corresponding source drain metal layer in semi-transparent area；
The corresponding source drain metal layer in semi-transparent area exposed is etched away, the source electrode and drain electrode of TFT device, and exposure are obtained
The pixel electrode layer out, the source electrode and it is described drain electrode be electrically connected respectively with the active layer, it is described drain also with the picture
Plain electrode layer electrical connection.
Preferably, further includes:
Passivation layer is formed in the source drain metal layer.
Preferably, further includes:
The common electrode layer with pixel electrode layer insulation is formed on the passivation layer.
Invention additionally discloses a kind of display devices, including the array substrate.
Compared with prior art, active layer of the invention and pixel electrode layer are same layer metal oxide, film forming annealing
It is afterwards conductor, active layer becomes semiconductor after treatment, forms film transistor device.Active layer and picture can be achieved in the present invention
The plain same stratification of electrode layer reduces light shield, greatly reduces production cost in original arraying bread board structure basis.
Detailed description of the invention
Below by clearly understandable mode, preferred embodiment is described with reference to the drawings, the present invention is given furtherly
It is bright.
Fig. 1 is back channel etching device architecture schematic diagram；
Fig. 2 is a kind of structural schematic diagram of array substrate of the present invention；
Fig. 3 a-3f is a kind of step schematic diagram of the manufacturing method of array substrate of the present invention；
Fig. 4 a-4e is the step schematic diagram of the manufacturing method of another array substrate of the present invention.
Specific embodiment
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, Detailed description of the invention will be compareed below
A specific embodiment of the invention.It should be evident that drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing, and obtain other embodiments.
To make simplified form, part related to the present invention is only schematically shown in each figure, they are not represented
Its practical structures as product.In addition, there is identical structure or function in some figures so that simplified form is easy to understand
Component only symbolically depicts one of those, or has only marked one of those.Herein, "one" is not only indicated
" only this ", can also indicate the situation of " more than one ".
For the problems of the prior art, the embodiment of the invention provides a kind of array substrates and manufacturing method, to solve
The problem.
Embodiment one
Fig. 2 is a kind of structural schematic diagram of array substrate of the present invention, as shown in Fig. 2, oxide film transistor array base
Plate includes: thin film transistor (TFT)；The thin film transistor (TFT) includes:
Substrate 01；
Grid 02 is formed on the substrate 01；
Gate insulating layer 03 is formed on the grid 01 and the substrate 02；
It is formed in the active layer 04 and pixel electrode layer 05 of the same layer setting on the gate insulating layer 03；It is described active
The channel region 041 of layer 04 is formed by metal conductive oxide layer semiconductor transformation processing；The pixel electrode layer 05 is by metal oxygen
Compound conductive layer is formed；
Source drain metal layer is formed on the active layer 04 and the pixel electrode layer 05, including source electrode 06 and drain electrode
07, the source electrode 06 and the drain electrode 07 are electrically connected with the active layer 04 respectively, the drain electrode 07 and the pixel electrode layer
05 electrical connection.
Preferably, further includes: the passivation layer 08 in the source drain metal layer.
Preferably, further includes: the common electrode layer 09 with 05 mutually insulated of pixel electrode layer.
It should be noted that active layer 04 and pixel electrode layer 05 are metal oxide materials, packet in the embodiment of the present invention
Include but be not limited to IGZO, IGZTO, IZO etc..Source drain metal layer is Ti/Cu lamination, includes but are not limited to this, can be single
Layer, or lamination can be metal, or non-metallic conducting material etc..
Specifically, the different and different selections according to material of the semiconductor transformation processing method of metal conductive oxide layer, than
Such as gas ions processing, ion implanting, the present invention are not especially limited.
In structure as shown in Figure 2, grid 02 connects grid line, scanning signal of the conduction from grid line, makes active layer 04
Middle formation current channel is connected, the grayscale that source electrode 06 will receive between the source electrode 06 being connected with active layer 04 and drain electrode 07
Signal is conducted to drain electrode 07 by active layer 04, and drain electrode 07 is electrically connected with pixel electrode layer 05, grayscale signal is conducted to pixel
Electrode layer, to form electric field between pixel electrode layer and common electrode layer.
The embodiment of the present invention passes through oxide conducting layer for the pixel of active layer 04 and pixel region in thin film transistor (TFT)
The setting of 05 same layer of electrode layer, the oxide conducting layer of 04 channel region 041 of active layer handle as semiconductor, source drain metal layer with
Passivation layer exposes pixel electrode layer 05, and source electrode 06 and drain electrode 07 are electrically connected with active layer 04 respectively, and drain electrode 07 is gone back and pixel
Electrode layer 05 be electrically connected, compared with the prior art in oxide TFT array substrate, reduce pixel ITO layer, can reduce thin
The production cost of film transistor array substrate.
Based on identical inventive concept, the embodiment of the invention also provides a kind of manufacturing methods of array substrate, such as Fig. 3 a-
Shown in 3f, this method comprises:
Step 301, as shown in Figure 3a, the formation grid 02 on substrate 01；
Step 302, as shown in Figure 3b, the formation gate insulating layer 03 on the substrate 01 and the grid 02, with covering
The grid 02 and the substrate 01；
Step 303, as shown in Figure 3b, the depositing metal oxide conductive layer on the gate insulating layer 03 passes through exposure
It etches the metal conductive oxide layer and forms active layer 04 and pixel electrode layer 05；
Step 304, as shown in Figure 3c, form source drain metal layer on the metal conductive oxide layer, pass through exposure carve
Etching off carries out semiconductor transformation processing except the source drain metal layer on the active layer 04 of part, to the part, forms active layer 04
Channel region 041；
Step 305, as shown in Figure 3d, etches the source drain metal layer by exposure and obtains source electrode 06 and the leakage of TFT device
Pole 07, and the pixel electrode layer 05 is exposed, the source electrode 06 and the drain electrode 07 are electrically connected with the active layer 04 respectively,
The drain electrode 07 is also electrically connected with the pixel electrode layer 05.
Preferably, further include step 306, as shown in Figure 3 e, form passivation layer 08 in the source drain metal layer.
Preferably, further include step 307, as illustrated in figure 3f, formed on the passivation layer 08 exhausted with pixel electrode layer 05
The common electrode layer 09 of edge.
Specifically, the different and different selections according to material of the semiconductor transformation processing method of metal conductive oxide layer, than
Such as gas ions processing, ion implanting, the present invention are not especially limited.
Based on identical inventive concept, the embodiment of the invention also provides the manufacturing methods of another array substrate, such as Fig. 4
It is shown, this method comprises:
Step 401, as shown in fig. 4 a forms grid 02 on substrate 01；
Step 402, as shown in Figure 4 b, the formation gate insulating layer 03 on the substrate 01 and the grid 02, with covering
The grid 02 and the substrate 01；
Step 403, as shown in Figure 4 b, the depositing metal oxide conductive layer on the gate insulating layer 03 passes through exposure
It etches the metal conductive oxide layer and forms active layer 04 and pixel electrode layer 05；
Step 404, as illustrated in fig. 4 c, forms source drain metal layer on the metal conductive oxide layer, by it is different thoroughly
The light shield for crossing rate forms full impregnated area, impermeable area and semi-transparent area；
Step 405, as illustrated in fig. 4 c, the corresponding active layer 04 in exposure etching full impregnated area, removal part are described active
Source drain metal layer on layer 04 carries out semiconductor transformation processing to the part, forms the channel region 041 of active layer 04；
Step 406, as illustrated in fig. 4 c is ashed photoresist, exposes the corresponding source drain metal layer in semi-transparent area；
Step 407, as illustrated in fig. 4 c, etches away the corresponding source drain metal layer in semi-transparent area exposed, obtains TFT device
Source electrode 06 and drain electrode 07, and expose the pixel electrode layer 05, the source electrode 06 and the drain electrode 07 have with described respectively
Active layer 04 is electrically connected, and the drain electrode 07 is also electrically connected with the pixel electrode layer 05.
Preferably, further include step 408, as shown in figure 4d, form passivation layer 08 in the source drain metal layer.
Preferably, further include step 409, as shown in fig 4e, formed on the passivation layer 08 exhausted with pixel electrode layer 05
The common electrode layer 09 of edge.
By using HTM mask technique in the embodiment of the present invention, need to only it use a light shield can be by active layer 04 and picture
The same stratification of plain electrode layer 05, only needs 5 light shields in total.
In conclusion in array substrate provided in an embodiment of the present invention, by metal conductive oxide layer by TFT device
In active layer 04 and pixel region the setting of 05 same layer of pixel electrode layer, the metal conductive oxide layer of active layer 04 is handled
For semiconductor, compared with the prior art in oxide TFT array substrate, reduce pixel ITO layer, can reduce oxide
The production cost of tft array substrate.
It should be noted that above-described embodiment can be freely combined as needed.The above is only of the invention preferred
Embodiment, it is noted that for those skilled in the art, in the premise for not departing from the principle of the invention
Under, several improvements and modifications can also be made, these modifications and embellishments should also be considered as the scope of protection of the present invention.
Claims (10)
1. a kind of array substrate characterized by comprising thin film transistor (TFT)；The thin film transistor (TFT) includes:
Substrate；
Grid is formed over the substrate；
Gate insulating layer is formed on the grid and the substrate；
Form the active layer and pixel electrode layer of same layer setting on the gate insulating layer；The channel region of the active layer
It is formed by metal conductive oxide layer semiconductor transformation processing；The pixel electrode layer is formed by metal conductive oxide layer；
Source drain metal layer is formed on the active layer and the pixel electrode layer, including source electrode and drain electrode, the source electrode and
The drain electrode is electrically connected with the active layer respectively, and the drain electrode is electrically connected with the pixel electrode layer.
2. array substrate as described in claim 1, which is characterized in that further include: the passivation in the source drain metal layer
Layer.
3. array substrate as claimed in claim 2, which is characterized in that further include: the public affairs with the pixel electrode mutually insulated
Common electrode.
4. a kind of manufacturing method of array substrate characterized by comprising
Grid is formed on the substrate；
Gate insulating layer is formed on the substrate and the grid, to cover the grid and the substrate；
Depositing metal oxide conductive layer on the gate insulating layer etches the metal conductive oxide layer shape by exposure
At active layer and pixel electrode layer；
Source drain metal layer is formed on the metal conductive oxide layer, is etched on the removal part active layer by exposure
Source drain metal layer, to the part carry out semiconductor transformation processing, form the channel region of active layer；
The source drain metal layer is etched by exposure and obtains the source electrode and drain electrode of TFT device, and exposes the pixel electrode
Layer, the source electrode and the drain electrode are electrically connected with the active layer respectively, and the drain electrode is also electrically connected with the pixel electrode layer.
5. the manufacturing method of array substrate as claimed in claim 4, which is characterized in that further include:
Passivation layer is formed in the source drain metal layer.
6. the manufacturing method of array substrate as claimed in claim 5, which is characterized in that further include:
The common electrode layer with pixel electrode layer insulation is formed on the passivation layer.
7. a kind of manufacturing method of array substrate characterized by comprising
Grid is formed on the substrate；
Gate insulating layer is formed on the substrate and the grid, to cover the grid and the substrate；
Depositing metal oxide conductive layer on the gate insulating layer etches the metal conductive oxide layer shape by exposure
At active layer and pixel electrode layer；
Source drain metal layer is formed on the metal conductive oxide layer, by the light shield formation full impregnated area of different transmitances, no
Saturating area and semi-transparent area；
The corresponding active layer in exposure etching full impregnated area, removes the source drain metal layer on the active layer of part, to the part
Semiconductor transformation processing is carried out, the channel region of active layer is formed；
It is ashed photoresist, exposes the corresponding source drain metal layer in semi-transparent area；
The corresponding source drain metal layer in semi-transparent area exposed is etched away, obtains the source electrode and drain electrode of TFT device, and expose institute
Pixel electrode layer is stated, the source electrode and the drain electrode are electrically connected with the active layer respectively, and the drain electrode is also electric with the pixel
Pole layer electrical connection.
8. the manufacturing method of array substrate as claimed in claim 7, which is characterized in that further include:
Passivation layer is formed in the source drain metal layer.
9. the manufacturing method of array substrate as claimed in claim 8, which is characterized in that further include:
The common electrode layer with pixel electrode layer insulation is formed on the passivation layer.
10. a kind of display device, which is characterized in that including array substrate as claimed in any one of claims 1-3.
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| CN201910001744.8A CN109712993A (en) | 2019-01-02 | 2019-01-02 | Array substrate and manufacturing method and display device |
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| CN110634793A (en) * | 2019-09-26 | 2019-12-31 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and display panel |
| CN111584520A (en) * | 2020-05-25 | 2020-08-25 | 成都中电熊猫显示科技有限公司 | Array substrate, display panel and manufacturing method of array substrate |
| CN111584521A (en) * | 2020-05-25 | 2020-08-25 | 成都中电熊猫显示科技有限公司 | Array substrate, manufacturing method thereof and display panel |
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Effective date of registration: 20200910 Address after: No.7 Tianyou Road, Qixia District, Nanjing City, Jiangsu Province Applicant after: NANJING CEC PANDA FPD TECHNOLOGY Co.,Ltd. Address before: Nanjing Crystal Valley Road in Qixia District of Nanjing City Tianyou 210033 Jiangsu province No. 7 Applicant before: NANJING CEC PANDA FPD TECHNOLOGY Co.,Ltd. Applicant before: NANJING CEC PANDA LCD TECHNOLOGY Co.,Ltd. Applicant before: NANJING HUADONG ELECTRONICS INFORMATION & TECHNOLOGY Co.,Ltd. |
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Application publication date: 20190503 |