CN105870169A - Thin-film transistor and manufacturing method thereof, array substrate and display device - Google Patents
Thin-film transistor and manufacturing method thereof, array substrate and display device Download PDFInfo
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- CN105870169A CN105870169A CN201610244601.6A CN201610244601A CN105870169A CN 105870169 A CN105870169 A CN 105870169A CN 201610244601 A CN201610244601 A CN 201610244601A CN 105870169 A CN105870169 A CN 105870169A
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- 239000012212 insulator Substances 0.000 claims description 112
- 238000000034 method Methods 0.000 claims description 53
- 238000002360 preparation method Methods 0.000 claims description 33
- 230000008569 process Effects 0.000 claims description 28
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- 230000015572 biosynthetic process Effects 0.000 claims description 3
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- 238000005286 illumination Methods 0.000 description 3
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- 239000010703 silicon Substances 0.000 description 3
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- 229910000838 Al alloy Inorganic materials 0.000 description 1
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- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L2029/42388—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor characterised by the shape of the insulating material
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- Thin Film Transistor (AREA)
Abstract
The invention discloses a thin-film transistor and a manufacturing method thereof, an array substrate and a display device, and belongs to the technical field of display devices. The thin-film transistor comprises a substrate, an active layer, a gate insulating layer, a gate, a source and a drain, wherein the active layer is arranged on the substrate; the gate insulating layer is arranged on the active layer; the length of the gate insulating layer is smaller than or equal to that of the active layer; the gate is arranged on the gate insulating layer; the source and the drain are arranged on the substrate and are connected with two opposite sides of the active layer respectively; the length of the gate insulating layer is the size of the gate insulating layer along the direction parallel to a connection line of the source and the drain; and the length of the active layer is the size of the active layer along the direction parallel to the connection line of the source and the drain. By the thin-film transistor, connection of the source and the active layer, and the drain and the active layer is achieved without arranging a via hole, so that the thin-film transistor has a relatively large channel width-to-length ratio W/L; and the electrical properties of the thin-film transistor are improved.
Description
Technical field
The present invention relates to display device technology field, particularly to a kind of thin film transistor (TFT) and preparation method thereof,
Array base palte, display device.
Background technology
Thin film transistor (TFT) (Thin Film Transistor is called for short " TFT ") is the pass in liquid crystal indicator
Key device, plays highly important effect to the service behaviour of liquid crystal indicator.
Seeing Fig. 1, existing thin film transistor (TFT) specifically includes that the active layer 3a being arranged on substrate base 1a, covers
It is stamped etching barrier layer 2a and the grid 4a being arranged on etching barrier layer 2a, the source electrode 5a of active layer 3a
With drain electrode 6a.Wherein, etching barrier layer 2a is provided with via, source electrode 5a and drain electrode 6a and all passes through via
It is connected with active layer 3a.The preparation method of existing thin film transistor (TFT) specifically includes that with patterning processes at substrate
Active layer 3a figure it is formed with on substrate 1a；Deposition-etch barrier layer 2a on above-mentioned underlay substrate 1a, and right
The etching barrier layer 2a obtained is patterned technique thus forms via；Above-mentioned etching barrier layer 2a deposits
Gate/source/drain metal layer, forms grid 4a, source electrode 5a and drain electrode 6a by patterning processes.
During realizing the present invention, it is existing that inventor finds that prior art at least there is problems in that
Thin film transistor (TFT) need on etching barrier layer formed via so that source electrode and drain electrode are connected with active layer, mistake
The existence in hole makes the channel width-over-length ratio (W/L) of thin film transistor (TFT) less, thus affects the electricity of thin film transistor (TFT)
Learn performance.
Summary of the invention
In order to solve problem of the prior art, a kind of channel width-over-length ratio of embodiment of the present invention offer is relatively big, electricity
Thin film transistor (TFT) of good performance and preparation method thereof, and array base palte based on this thin film transistor (TFT) is with aobvious
Showing device.
Specifically, including following technical scheme:
First aspect, embodiments provides a kind of thin film transistor (TFT), and described thin film transistor (TFT) includes:
Underlay substrate, active layer, gate insulator, grid, source electrode and drain electrode；Described active layer is arranged on institute
State on underlay substrate；Described gate insulator is arranged on described active layer, and described gate insulator
Length is less than or equal to the length of described active layer；Described grid is arranged on described gate insulator, institute
State source electrode to be arranged on described underlay substrate with drain electrode and both sides relative with described active layer respectively company
Connect.
Further, described thin film transistor (TFT) also includes: passivation layer；Described passivation layer covers described substrate base
Plate, source electrode, drain electrode and grid.
Second aspect, embodiments provides the preparation method of a kind of thin film transistor (TFT), described making side
Method includes:
Underlay substrate is formed the figure of active layer and the figure of gate insulator；Described gate insulator
It is positioned on described active layer and the length of described gate insulator is less than or equal to the length of described active layer
Degree；
On described gate insulator formed grid, described underlay substrate is formed respectively with described active layer
The source electrode that connects of relative both sides and drain electrode.
Further, when the length of described gate insulator is less than the length of described active layer, described at lining
The figure of the figure and gate insulator that are formed with active layer on substrate specifically includes:
Described underlay substrate is formed with active layer, described active layer is formed described gate insulator；
Described gate insulator coats photoresist, utilizes intermediate tone mask version or gray tone mask plate pair
Described photoresist is exposed and develops, formed photoresist be fully retained district, photoresist part reserved area with
And photoresist removes district completely；Wherein, described photoresist is fully retained district's correspondence and there is described active layer and institute
Stating the region of gate insulator, described photoresist part reserved area correspondence only exists the region of described active layer,
The region beyond the corresponding described active layer in district removed completely by described photoresist；
Removal is positioned at described photoresist and removes the described active layer in district and described gate insulator completely；
Remove the photoresist of described photoresist part reserved area；
Remove the described gate insulator being positioned at described photoresist part reserved area；
Remove described photoresist and the photoresist in district is fully retained.
Further, use dry etch process removal to be positioned at described photoresist and remove district and described light completely
The described gate insulator of photoresist part reserved area；Wet-etching technology removal is used to be positioned at described photoresist complete
The complete described active layer removing district.
Further, the photoresist of described removal described photoresist part reserved area, specifically include:
The ultraviolet light using preset strength irradiates the photoresist of described photoresist part reserved area and described photoetching
Glue is fully retained the photoresist in district, makes the photoresist of described photoresist part reserved area all decompose, and makes described
Photoresist is fully retained the photoresist decomposed in district, thus removes the photoetching of described photoresist part reserved area
Glue, retains described photoresist simultaneously and the part photoresist in district is fully retained.
Further, when the length of described gate insulator is equal with the length of described active layer, described
The figure of the figure and gate insulator that are formed with active layer on underlay substrate specifically includes:
Described underlay substrate is formed with active layer, described active layer is formed described gate insulator；
Figure and the figure of described active layer of described gate insulator is concurrently formed by patterning processes.
Further, described formation grid on described gate insulator, described underlay substrate is formed and divides
The source electrode of the both sides connection the most relative with described active layer and drain electrode, specifically include:
Forming source/drain/gate layer on described underlay substrate, described source/drain/gate layer covers described
Underlay substrate, described gate insulator and described active layer；
Described source electrode, described drain electrode and described grid is formed by a patterning processes.
Further, described preparation method also includes:
Described underlay substrate is formed and covers described underlay substrate, source electrode, drain electrode and the passivation layer of grid.
The third aspect, embodiments provides a kind of array base palte, and described array base palte includes above-mentioned
Thin film transistor (TFT).
Fourth aspect, embodiments provides a kind of display device, and described display device includes above-mentioned
Array base palte.
The technical scheme that the embodiment of the present invention provides has the benefit that
In the thin film transistor (TFT) that the embodiment of the present invention provides, owing to source electrode is relative with active layer respectively with drain electrode
Both sides directly contact connection, from without arranging via and i.e. achieve the connection of source/drain and active layer,
Solve the problem that the thin film transistor channel breadth length ratio caused owing to arranging via is less, be effectively increased
The electric property of thin film transistor (TFT).
Additionally, the figure of active layer in the thin film transistor (TFT) that provides of the embodiment of the present invention and gate insulator
Figure can be formed by a patterning processes, simplifies the manufacture craft of thin film transistor (TFT), improves and make effect
Rate, reduction cost.
Accompanying drawing explanation
For the technical scheme being illustrated more clearly that in the embodiment of the present invention, institute in embodiment being described below
The accompanying drawing used is needed to be briefly described, it should be apparent that, the accompanying drawing in describing below is only the present invention
Some embodiments, for those of ordinary skill in the art, on the premise of not paying creative work,
Other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the structural representation of existing thin film transistor (TFT)；
The structural representation of a kind of thin film transistor (TFT) that Fig. 2 provides for one embodiment of the invention；
The structural representation of a kind of thin film transistor (TFT) that Fig. 3 provides for further embodiment of this invention；
The flow chart of the preparation method of a kind of thin film transistor (TFT) that Fig. 4 provides for one embodiment of the invention；
The flow chart of the preparation method of a kind of thin film transistor (TFT) that Fig. 5 provides for further embodiment of this invention；
Showing of the preparation method of a kind of thin film transistor (TFT) that Fig. 6-1～Fig. 6-10 provides for further embodiment of this invention
It is intended to；
The flow chart of the preparation method of a kind of thin film transistor (TFT) that Fig. 7 provides for further embodiment of this invention；
Showing of the preparation method of a kind of thin film transistor (TFT) that Fig. 8-1～Fig. 8-7 provides for further embodiment of this invention
It is intended to.
Reference represents respectively:
The underlay substrate of the existing thin film transistor (TFT) of 1a-；
The etching barrier layer of the existing thin film transistor (TFT) of 2a-；
The active layer of the existing thin film transistor (TFT) of 3a-；
The grid of the existing thin film transistor (TFT) of 4a-；
The source electrode of the existing thin film transistor (TFT) of 5a-；
The drain electrode of the existing thin film transistor (TFT) of 6a-；
The passivation layer of the existing thin film transistor (TFT) of 7a-；
1-underlay substrate；
2-gate insulator；
3-active layer；
4-grid；
5-source electrode；
6-drains；
7-passivation layer；
8-photoresist；
9-gate/source/drain electrode layer；
A-photoresist is fully retained district；
District removed completely by B-photoresist；
C-photoresist part reserved area.
Solid arrow in Fig. 6-2 and Fig. 8-2 represents light.
Detailed description of the invention
For making the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to the present invention
Embodiment is described in further detail.Unless otherwise defined, all technology used by the embodiment of the present invention
Term is respectively provided with the identical implication being generally understood that with those skilled in the art.
Embodiment one
The present embodiment provides a kind of thin film transistor (TFT), sees Fig. 2, it is possible to see Fig. 3, this thin film transistor (TFT) bag
Include underlay substrate 1, active layer 3, gate insulator 2, grid 4, source electrode 5 and drain electrode 6；Active layer 3
It is arranged on underlay substrate 1；Gate insulator 2 is arranged on active layer 3, and gate insulator 2
Length is less than or equal to the length of active layer 3；Grid 4 is arranged on gate insulator 2, source electrode 5 He
Drain electrode 6 is arranged on underlay substrate and both sides relative with active layer 3 respectively connect；Wherein, grid
The a length of gate insulator 2 of insulating barrier 2 is along being parallel to the size in source electrode 5 and drain electrode 6 line directions (i.e.
Along the size in OO ' direction in Fig. 2 and Fig. 3), a length of active layer 3 of active layer 3 along be parallel to source electrode and
The size (i.e. along the size in OO ' direction in Fig. 2 and Fig. 3) in drain electrode line direction.
In the thin film transistor (TFT) that the present embodiment provides, source electrode 5 and drain electrode 6 are arranged on underlay substrate 1, by
Length in gate insulator 2 is less than or equal to the length of active layer 3 so that source electrode 5 and drain electrode 6 points
Directly do not contact connection with the relative both sides of active layer 3, from i.e. achieving source electrode 5 without arranging via
With the connection of drain electrode 6 with active layer 3, solve the thin film transistor channel width caused owing to arranging via
Long smaller problem, is effectively increased the electric property of thin film transistor (TFT).
Further, in the present embodiment, when the length of gate insulator 2 is less than the length of active layer 3,
See Fig. 2, two side surfaces that active layer 3 is relative two side surfaces relative relative to gate insulator 2 to
Outer protrusion, in step-like；Preferably gate insulator 2 is arranged on the middle part of active layer 3, i.e. gate insulator
The layer symmetry axis of 2 overlaps with the symmetry axis of active layer 3；The position that source electrode 5 and drain electrode 6 are connected with active layer 3
Put and include two relative side surfaces of active layer 3 and active layer 3 is outwardly relative to gate insulator 2
The upper surface of part.When the length of gate insulator 2 is equal with the length of active layer 3, see Fig. 3, grid
Two side surfaces that two side surfaces that pole insulating barrier 2 is relative are relative with active layer 3 align respectively, source electrode 5
The position connected with active layer 3 with drain electrode 6 is only two side surfaces that active layer 3 is relative.As can be seen here,
When the length of gate insulator 2 is less than the length of active layer 3, source electrode 5 and drain electrode 6 and active layer 3
Contact area is bigger, beneficially source electrode 5 and the connection of drain 6 and active layer 3.It should be noted that work as
When the length of gate insulator 2 is less than the length of active layer 3, ensureing source electrode 5 and drain electrode 6 and active layer 3
In the case of effectively connecting, active layer 3 can be reduced as far as possible relative to the outwardly portion of gate insulator 2
The length divided, to increase channel width-over-length ratio, thus improves the electric property of film crystal.
Further, seeing Fig. 2, it is possible to see Fig. 3, the thin film transistor (TFT) of the present embodiment also includes: passivation
Layer 7.Passivation layer 7 covers underlay substrate 1, source electrode 5, drain electrode 6 and grid 4.
In the thin film transistor (TFT) of the present embodiment, underlay substrate 1, gate insulator 2, active layer 3, grid 4,
The material of source electrode 5, drain electrode 6 and passivation layer 7 is not particularly limited, material commonly used in the art.Example
As, the material of underlay substrate 1 includes but not limited to glass, transparent plastic etc.；The material of gate insulator 2
Include but not limited to the oxide (SiO of siliconx)；The material of active layer 3 includes but not limited to non-crystalline silicon, polycrystalline
Silicon, metal-oxide semiconductor (MOS), organic semiconductor compound etc.；Grid 4, source electrode 5 and the material of drain electrode 6
Material includes but not limited to aluminium, aluminium alloy etc.；The material of passivation layer 7 includes but not limited to the oxide (SiO of siliconx)、
Nitride (the SiN of siliconx) etc..
Embodiment two
The present embodiment provides the preparation method of a kind of thin film transistor (TFT), sees Fig. 4, and this preparation method includes:
Step 201, is formed with figure and the figure of gate insulator 2 of active layer 3 on underlay substrate 1；
Gate insulator 2 is positioned on active layer 3 and the length of gate insulator 2 is less than or equal to active layer 3
Length.
Step 202, forms grid 4 on gate insulator 2, is formed respectively with active on underlay substrate 1
The source electrode 5 that the relative both sides of layer 3 connect and drain electrode 6.
Wherein, a length of gate insulator 2 of gate insulator 2 is along being parallel to source electrode 5 and drain electrode 6 lines
The size (i.e. along the size in OO ' direction in Fig. 2 and Fig. 3) in direction, a length of active layer 3 of active layer 3
Along being parallel to source electrode and the size (i.e. along the size in OO ' direction in Fig. 2 and Fig. 3) in drain electrode line direction.
The preparation method using the present embodiment makes in the thin film transistor (TFT) obtained, source electrode 5 and drain electrode 6 setting
On underlay substrate 1, owing to the length of gate insulator 2 is less than or equal to the length of active layer 3, make
Obtain source electrode 5 and directly contact connection with the relative both sides of active layer 3 respectively, from without setting with drain electrode 6
Put via and i.e. achieve source electrode 5 and drain electrode 6 and the connection of active layer 3, solve and lead owing to arranging via
The less problem of thin film transistor channel breadth length ratio caused, is effectively increased the electric property of thin film transistor (TFT).
Meanwhile, the preparation method technological process that the present embodiment provides is simple, it is simple to controls, thus improves film crystal
The make efficiency of pipe, reduction cost of manufacture.
Embodiment three
The present embodiment provides the preparation method of a kind of thin film transistor (TFT), and this preparation method is for making such as Fig. 2 institute
The thin film transistor (TFT) shown.
Owing in the thin film transistor (TFT) shown in Fig. 2, the length of gate insulator 2 is less than the length of active layer 3,
I.e. gate insulator 2 is smaller in size than the active layer 3 size along OO ' direction along OO ' direction, and active
Two side surfaces that relative two side surfaces of layer 3 are relative relative to gate insulator 2 are outwardly in step
Shape, therefore this thin film transistor (TFT) includes three below region: there are active layer 3 and gate insulator 2 simultaneously
Region, only exist beyond the region of active layer 3 and active layer 3, the most both without active layer 3 also non-grid
The region of insulating barrier 2.
For the structure of this thin film transistor (TFT), the present embodiment provides that a kind of technological process is simple, photoetching number of times relatively
Less, be easy to control preparation method, see Fig. 5, and combine Fig. 6-1～Fig. 6-10, this preparation method is concrete
Comprise the following steps:
Step 301, is formed with active layer 3 on underlay substrate 1, forms gate insulator 2 on active layer 3.
As in Figure 6-1, in this step, active layer 3 covers underlay substrate 1, and gate insulator 2 covers
Active layer 3.It will be appreciated by persons skilled in the art that the method being formed with active layer 3 on underlay substrate 1
Include but not limited to deposit, apply, sputtering etc., active layer 3 is formed the method for gate insulator 2 with
Sample includes but not limited to deposit, applies, sputtering etc., and those skilled in the art can be according to active layer 3 and grid
The concrete material of pole insulating barrier 2 selects suitable method.
Step 302, coats photoresist 8 on gate insulator 2, utilizes intermediate tone mask version or gray tone
Photoresist 8 is exposed and develops by mask plate, forms photoresist and district A, photoresist part are fully retained
District B removed completely by reserved area C and photoresist；Wherein, photoresist is fully retained district's A correspondence and exists active
Layer 3 and the region of gate insulator 2, photoresist part reserved area C correspondence only exists the region of active layer 3,
The region beyond district B correspondence active layer 3 removed completely by photoresist.
As shown in Fig. 6-2 and Fig. 6-3, after gate insulator 2 coats photoresist 8, halftoning is utilized to cover
Photoresist 8 is exposed by film version or gray tone mask plate, is positioned at photoresist and the photoetching of district A is fully retained
Glue 8 does not the most decompose owing to being not affected by illumination, is fully retained after development；It is positioned at photoresist part to retain
The photoresist 8 of district C is more weak due to the intensity of illumination being subject to, and there occurs decomposed, the part decomposed
It is removed after development, and the part do not decomposed is retained；It is positioned at photoresist and removes the light of district B completely
Photoresist 8 is decomposed more by force and all due to the intensity of illumination being subject to, and is completely removed after development.
Step 303, removal is positioned at photoresist and removes gate insulator 2 and the active layer 3 of district B completely.
As shown in Fig. 6-4 and Fig. 6-5, after photoresist 8 is exposed and develops, remove successively and be positioned at
Gate insulator 2 and the active layer 3 of district B removed completely by photoresist, thus forms gate insulator 2 and active
The figure of layer 3.Those skilled in the art can select according to the material of gate insulator 2 and active layer 3
Suitably method removes gate insulator 2 and active layer 3, such as, dry etch process can be used to remove grid
Insulating barrier 2, uses wet-etching technology to remove active layer 3.
Step 304, removes the photoresist 8 of photoresist part reserved area C.
The specific implementation of the photoresist 8 removing photoresist part reserved area C is: use preset strength
The photoresist 8 of ultraviolet light irradiation photoresist part reserved area C and photoresist are fully retained the photoresist of district A
8, make the photoresist 8 of photoresist part reserved area C all decompose, make photoresist that the photoetching of district A is fully retained
Glue 8 decomposed.After utilizing developing solution to develop further, remove the photoetching of photoresist part reserved area C
Glue 8, retains photoresist simultaneously and the part photoresist 8 (as shown in Fig. 6-6) of district A is fully retained.This step
Used by, the intensity of ultraviolet light does not has considered critical, but is to ensure that the ultraviolet light through this intensity irradiates and develops
Rear photoresist is fully retained the remaining photoresist of district A 8 and can play a protective role gate insulator 2, has
It is beneficial to the follow-up further process to gate insulator 2.
Step 305, removes the gate insulator 2 being positioned at photoresist part reserved area C.
As shown in fig. 6-7, after being removed by the photoresist 8 of photoresist part reserved area C, will be located in light
The gate insulator 2 of photoresist part reserved area C is removed, thus forms the pattern of gate insulator 2.Permissible
Dry etch process is used to remove gate insulator 2.
Step 306, removes photoresist and the photoresist 8 of district A is fully retained.
As shown in figs 6-8, it is possible to use photoresist is fully retained the remaining photoresist of district A 8 by the method for stripping
Remove.
It should be noted that those skilled in the art can use additive method to substitute above-mentioned steps 301～306
It is formed with active layer 3 and the figure of gate insulator 2, for example, it is also possible to first pass through on underlay substrate 1
Deposition, apply or the method such as sputtering is formed with active layer 3, then utilize patterning processes to be formed with the figure of active layer 3
Shape, then on underlay substrate 1 by deposition, apply or the method such as sputtering is formed and is coated with the grid of active layer 3
Pole insulating barrier 2, recycling patterning processes forms the figure of gate insulator 2.But said method and this enforcement
The step 301 of example～the method for 306 are compared, and required photoetching number of times is more, and technological process is relatively complicated.
Step 307, forms source/drain/gate layer 9 on underlay substrate 1, and source/drain/gate layer 9 covers
Lid underlay substrate 1, gate insulator 2 and active layer 3.
As Figure 6-9, after the figure of active layer 3 and the figure of gate insulator 2 are formed, at substrate
Formed on substrate 1 and cover underlay substrate 1, gate insulator 2 and the source/drain/gate layer of active layer 3
9.Deposition can be used, apply or the method such as sputtering forms source/drain/gate layer 9.
Step 308, forms source electrode 5, drain electrode 6 and grid 4 by a patterning processes.
As illustrated in figures 6-10, after forming source/drain/gate layer 9, by a patterning processes at grid
Form grid 4 on insulating barrier 2, on underlay substrate 1, form both sides connection relative with active layer 3 respectively
Source electrode 5 and drain electrode 6.An above-mentioned patterning processes uses this area routine techniques means, specifically includes
The steps such as photoresist applies, exposes, develops, etches, photoresist lift off.
Step 309, is formed on underlay substrate 1 and covers underlay substrate 1, source electrode 5, drain electrode 6 and grid
The passivation layer 7 of 4.
After forming source electrode 5, drain electrode 6 and grid 4, by deposition, apply or the method shape such as sputtering
Become to cover underlay substrate 1, source electrode 5, drain electrode 6 and the passivation layer 7 of grid 4, thus obtain shown in Fig. 2
Thin film transistor (TFT).
To sum up, source electrode 5 and drain electrode 6 in the thin film transistor (TFT) that the preparation method using the present embodiment to provide obtains
Directly it is connected with active layer 3, overcomes the thin film transistor channel breadth length ratio caused owing to arranging via relatively
Little problem, makes this thin film transistor (TFT) have good electric property.Meanwhile, the making that the present embodiment provides
In method, utilize intermediate tone mask technique, be formed with figure and the grid of active layer 3 by patterning processes
The figure of insulating barrier 2, simplifies the manufacture craft of thin film transistor (TFT), improves make efficiency, reduces cost.
Embodiment four
The present embodiment provides the preparation method of a kind of thin film transistor (TFT), and this preparation method is for making such as Fig. 3 institute
The thin film transistor (TFT) shown.
Owing in the thin film transistor (TFT) shown in Fig. 3, the length of gate insulator 2 is equal to the length of active layer 3,
I.e. gate insulator 2 is equal to the active layer 3 size along OO ' direction along the size in OO ' direction, and therefore this is thin
Film transistor includes following two region: there are active layer 3 and the region of gate insulator 2 simultaneously, with
And both without the region of active layer 3 also non-grid insulating barrier 2.
For the structure of this thin film transistor (TFT), the present embodiment provides that a kind of technological process is simple, photoetching number of times relatively
Less, be easy to control preparation method, see Fig. 7, and combine Fig. 8-1～Fig. 8-7, this preparation method include with
Lower step:
Step 401, is formed with active layer 3 on underlay substrate 1, forms gate insulator 2 on active layer 3.
As shown in Fig. 8-1, the specific implementation of this step is with the step 301 of embodiment three, the most superfluous at this
State.
Step 402, concurrently forms figure and the figure of active layer 3 of gate insulator 2 by patterning processes
Shape.
Specifically, first, as shown in Fig. 8-2 and Fig. 8-3, gate insulator 2 coats photoresist 8,
After utilizing mask plate to be exposed and developing, district A is fully retained for formation photoresist and photoresist is complete
Remove district B；Wherein, photoresist is fully retained district's A correspondence and there are active layer 3 and the district of gate insulator 2
Territory, it is corresponding both without the region of active layer 3 also non-grid insulating barrier 2 that district B removed completely by photoresist.
Afterwards, as shown in fig. 8-4, remove successively and be positioned at photoresist and remove the gate insulator 2 of district B completely
With active layer 3, thus it is formed with figure and the figure of gate insulator 2 of active layer 3.Those skilled in the art
Suitable method can be selected to remove active layer 3 and grid according to the material of active layer 3 and gate insulator 2
Pole insulating barrier 2, such as, can use dry etch process to remove gate insulator 2, use wet-etching technology
Remove active layer 3.
Afterwards, as shown in Fig. 8-5, removal is positioned at photoresist and the photoresist of district A is fully retained.Can utilize
The method peeled off is removed photoresist and the photoresist 8 of district A is fully retained.
It should be noted that those skilled in the art can use additive method to substitute above-mentioned steps 401～402
It is formed with active layer 3 and the figure of gate insulator 2, for example, it is also possible to first pass through on underlay substrate 1
Deposition, apply or the method such as sputtering is formed with active layer 3, then utilize patterning processes to be formed with the figure of active layer 3
Shape, then on underlay substrate 1 by deposition, apply or the method such as sputtering is formed and is coated with the grid of active layer 3
Pole insulating barrier 2, recycling patterning processes forms the figure of gate insulator 2.But said method and this enforcement
The step 401 of example～the method for 402 are compared, and required photoetching number of times is more, and technological process is relatively complicated.
Step 403, forms source/drain/gate layer 9 on underlay substrate 1, and source/drain/gate layer 9 covers
Lid underlay substrate 1, gate insulator 2 and active layer 3.
As shown in Fig. 8-6, the specific implementation of this step is with the step 307 of embodiment three, the most superfluous at this
State.
Step 404, forms source electrode 5, drain electrode 6 and grid 4 by a patterning processes.
As shown in Fig. 8-7, the specific implementation of this step is with the step 308 of embodiment three, the most superfluous at this
State.
Step 405, is formed on underlay substrate 1 and covers underlay substrate 1, source electrode 5, drain electrode 6 and grid
The passivation layer 7 of 4.
The specific implementation of this step, with the step 309 of embodiment three, does not repeats them here.Complete this step
After i.e. obtain the thin film transistor (TFT) shown in Fig. 3.
To sum up, source electrode 5 and drain electrode 6 in the thin film transistor (TFT) that the preparation method using the present embodiment to provide obtains
Directly it is connected with active layer 3, overcomes the thin film transistor channel breadth length ratio caused owing to arranging via relatively
Little problem, makes this thin film transistor (TFT) have good electric property.Meanwhile, the making that the present embodiment provides
In method, it is formed with figure and the figure of gate insulator 2 of active layer 3 by patterning processes, simplifies
The manufacture craft of thin film transistor (TFT), improves make efficiency, reduces cost.
Embodiment five
The present embodiment provides a kind of array base palte, and this array base palte includes the film that any of the above-described embodiment provides
Transistor.
Owing in the thin film transistor (TFT) that above-described embodiment provides, source electrode and drain electrode are directly connected with active layer, overcome
The problem that the thin film transistor channel breadth length ratio that causes owing to arranging via is less so that this film crystal
Pipe has good electric property, therefore, utilizes the array base palte of this thin film transistor (TFT) to have good equally
Electric property.
Embodiment six
The present embodiment provides a kind of display device, and this display device includes the array base palte that embodiment five provides.
The thin film transistor (TFT) used due to the array base palte of embodiment five offer has bigger channel width-over-length ratio
And good electric property, therefore, utilize the display device of this array base palte to have good electricity equally
Performance.
In the specific implementation, the display device that the present embodiment provides can be liquid crystal panel, Electronic Paper, OLED
Panel, mobile phone, panel computer, television set, display, notebook computer, DPF, navigator etc.
Any product with display function or parts.
The invention described above embodiment sequence number, just to describing, does not represent the quality of embodiment.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the scope of the invention, all
Within the spirit and principles in the present invention, any modification, equivalent substitution and improvement etc. made, all should comprise
Within protection scope of the present invention.
Claims (10)
1. a thin film transistor (TFT), it is characterised in that described thin film transistor (TFT) includes: underlay substrate, active
Layer, gate insulator, grid, source electrode and drain electrode；Described active layer is arranged on described underlay substrate；
Described gate insulator is arranged on described active layer, and the length of described gate insulator less than or etc.
Length in described active layer；Described grid is arranged on described gate insulator, and described source electrode and drain electrode set
Put on described underlay substrate and both sides relative with described active layer respectively connect；
The a length of gate insulator of described gate insulator is along being parallel to source electrode and the chi in drain electrode line direction
Very little, a length of active layer of described active layer is along being parallel to source electrode and the size in drain electrode line direction.
Thin film transistor (TFT) the most according to claim 1, it is characterised in that described thin film transistor (TFT) also wraps
Include: passivation layer；Described passivation layer covers described underlay substrate, source electrode, drain electrode and grid.
3. the preparation method of a thin film transistor (TFT), it is characterised in that described preparation method includes:
Underlay substrate is formed the figure of active layer and the figure of gate insulator；Described gate insulator
It is positioned on described active layer and the length of described gate insulator is less than or equal to the length of described active layer
Degree；On described gate insulator formed grid, described underlay substrate is formed respectively with described active layer
The source electrode that connects of relative both sides and drain electrode；
The a length of gate insulator of described gate insulator is along being parallel to source electrode and the chi in drain electrode line direction
Very little, a length of active layer of described active layer is along being parallel to source electrode and the size in drain electrode line direction.
Preparation method the most according to claim 3, it is characterised in that when the length of described gate insulator
When degree is less than the length of described active layer, the described figure being formed with active layer on underlay substrate and grid are exhausted
The figure of edge layer specifically includes:
Described underlay substrate is formed with active layer, described active layer is formed described gate insulator；
Described gate insulator coats photoresist, utilizes intermediate tone mask version or gray tone mask plate pair
Described photoresist is exposed and develops, formed photoresist be fully retained district, photoresist part reserved area with
And photoresist removes district completely；Wherein, described photoresist is fully retained district's correspondence and there is described active layer and institute
Stating the region of gate insulator, described photoresist part reserved area correspondence only exists the region of described active layer,
The region beyond the corresponding described active layer in district removed completely by described photoresist；
Removal is positioned at described photoresist and removes the described active layer in district and described gate insulator completely；
Remove the photoresist of described photoresist part reserved area；
Remove the described gate insulator being positioned at described photoresist part reserved area；
Remove described photoresist and the photoresist in district is fully retained.
Preparation method the most according to claim 4, it is characterised in that described removal described photoresist portion
Divide the photoresist of reserved area, specifically include:
The ultraviolet light using preset strength irradiates the photoresist of described photoresist part reserved area and described photoetching
Glue is fully retained the photoresist in district, makes the photoresist of described photoresist part reserved area all decompose, and makes described
Photoresist is fully retained the photoresist decomposed in district, thus removes the photoetching of described photoresist part reserved area
Glue, retains described photoresist simultaneously and the part photoresist in district is fully retained.
Preparation method the most according to claim 3, it is characterised in that when the length of described gate insulator
When spending equal with the length of described active layer, the described figure being formed with active layer on underlay substrate and grid
The figure of insulating barrier specifically includes:
Described underlay substrate is formed with active layer, described active layer is formed described gate insulator；
Figure and the figure of described active layer of described gate insulator is concurrently formed by patterning processes.
Preparation method the most according to claim 3, it is characterised in that described at described gate insulator
Upper formation grid, forms the source that both sides relative with described active layer respectively connect on described underlay substrate
Pole and drain electrode, specifically include:
Forming source/drain/gate layer on described underlay substrate, described source/drain/gate layer covers described
Underlay substrate, described gate insulator and described active layer；
Described source electrode, described drain electrode and described grid is formed by a patterning processes.
8. according to the preparation method described in any one of claim 3～7, it is characterised in that described preparation method
Also include:
Described underlay substrate is formed and covers described underlay substrate, source electrode, drain electrode and the passivation layer of grid.
9. an array base palte, it is characterised in that described array base palte includes that claim 1 or right are wanted
Seek the thin film transistor (TFT) described in 2.
10. a display device, it is characterised in that described display device includes the battle array described in claim 9
Row substrate.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107330400A (en) * | 2017-06-29 | 2017-11-07 | 京东方科技集团股份有限公司 | A kind of vein device for identifying |
| CN107331708A (en) * | 2017-06-30 | 2017-11-07 | 京东方科技集团股份有限公司 | The preparation method of thin film transistor (TFT), the preparation method of array base palte and array base palte, display device |
| CN107910375A (en) * | 2017-11-02 | 2018-04-13 | 京东方科技集团股份有限公司 | A kind of thin film transistor (TFT) and preparation method thereof, array base palte and display device |
| CN108122733A (en) * | 2016-11-29 | 2018-06-05 | 台湾积体电路制造股份有限公司 | Semiconductor device manufacturing method |
| WO2018169024A1 (en) * | 2017-03-17 | 2018-09-20 | Ricoh Company, Ltd. | Field-effect transistor, method for producing same, display element, display device, and system |
| JP2018157206A (en) * | 2017-03-17 | 2018-10-04 | 株式会社リコー | Field-effect transistor and method of manufacturing the same, display element, display device, and system |
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| WO2022267554A1 (en) * | 2021-06-24 | 2022-12-29 | 京东方科技集团股份有限公司 | Preparation method for thin film transistor and thin film transistor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050009249A1 (en) * | 2003-06-27 | 2005-01-13 | Oh Jae-Young | Method for fabricating polycrystalline silicon liquid crystal display device |
| US20080142804A1 (en) * | 2004-04-06 | 2008-06-19 | Kum-Mi Oh | Liquid crystal display device including driving circuit and method of fabricating the same |
| CN103730512A (en) * | 2013-12-31 | 2014-04-16 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method of thin film transistor and display device |
| CN104253159A (en) * | 2014-08-19 | 2014-12-31 | 京东方科技集团股份有限公司 | Thin film transistor and preparation method thereof, array substrate and preparation method thereof and display device |
-
2016
- 2016-04-18 CN CN201610244601.6A patent/CN105870169A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050009249A1 (en) * | 2003-06-27 | 2005-01-13 | Oh Jae-Young | Method for fabricating polycrystalline silicon liquid crystal display device |
| US20080142804A1 (en) * | 2004-04-06 | 2008-06-19 | Kum-Mi Oh | Liquid crystal display device including driving circuit and method of fabricating the same |
| CN103730512A (en) * | 2013-12-31 | 2014-04-16 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method of thin film transistor and display device |
| CN104253159A (en) * | 2014-08-19 | 2014-12-31 | 京东方科技集团股份有限公司 | Thin film transistor and preparation method thereof, array substrate and preparation method thereof and display device |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108122733B (en) * | 2016-11-29 | 2022-04-08 | 台湾积体电路制造股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN108122733A (en) * | 2016-11-29 | 2018-06-05 | 台湾积体电路制造股份有限公司 | Semiconductor device manufacturing method |
| KR102363115B1 (en) * | 2017-03-17 | 2022-02-15 | 가부시키가이샤 리코 | Field effect transistor, manufacturing method thereof, display element, display device and system |
| US11315961B2 (en) | 2017-03-17 | 2022-04-26 | Ricoh Company, Ltd. | Field-effect transistor, method for producing same, display element, display device, and system |
| WO2018169024A1 (en) * | 2017-03-17 | 2018-09-20 | Ricoh Company, Ltd. | Field-effect transistor, method for producing same, display element, display device, and system |
| JP2018157206A (en) * | 2017-03-17 | 2018-10-04 | 株式会社リコー | Field-effect transistor and method of manufacturing the same, display element, display device, and system |
| KR20190117655A (en) * | 2017-03-17 | 2019-10-16 | 가부시키가이샤 리코 | Field-effect transistors, manufacturing methods thereof, display elements, display devices and systems |
| CN107330400A (en) * | 2017-06-29 | 2017-11-07 | 京东方科技集团股份有限公司 | A kind of vein device for identifying |
| CN107330400B (en) * | 2017-06-29 | 2020-05-19 | 京东方科技集团股份有限公司 | Vein identification device |
| US10431611B2 (en) | 2017-06-30 | 2019-10-01 | Boe Technology Group Co., Ltd. | Method for manufacturing thin film transistor, method for manufacturing array substrate, array substrate and display device |
| CN107331708B (en) * | 2017-06-30 | 2020-06-16 | 京东方科技集团股份有限公司 | Manufacturing method of thin film transistor, manufacturing method of array substrate, array substrate and display device |
| CN107331708A (en) * | 2017-06-30 | 2017-11-07 | 京东方科技集团股份有限公司 | The preparation method of thin film transistor (TFT), the preparation method of array base palte and array base palte, display device |
| CN107910375A (en) * | 2017-11-02 | 2018-04-13 | 京东方科技集团股份有限公司 | A kind of thin film transistor (TFT) and preparation method thereof, array base palte and display device |
| CN111554580A (en) * | 2020-05-14 | 2020-08-18 | 京东方科技集团股份有限公司 | Thin film transistor, manufacturing method thereof, display substrate and display device |
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