CN104952934A - Thin film transistor, manufacturing method, array substrate and display panel - Google Patents

Thin film transistor, manufacturing method, array substrate and display panel Download PDF

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Publication number
CN104952934A
CN104952934A CN201510359405.9A CN201510359405A CN104952934A CN 104952934 A CN104952934 A CN 104952934A CN 201510359405 A CN201510359405 A CN 201510359405A CN 104952934 A CN104952934 A CN 104952934A
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China
Prior art keywords
drain
source electrode
source
active layer
film transistor
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CN201510359405.9A
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CN104952934B (en
Inventor
李良坚
左岳平
马应海
许晓伟
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to CN201510359405.9A priority Critical patent/CN104952934B/en
Publication of CN104952934A publication Critical patent/CN104952934A/en
Priority to PCT/CN2016/074216 priority patent/WO2016206394A1/en
Priority to US15/116,195 priority patent/US9711602B2/en
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
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    • H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys

Abstract

The invention provides a thin film transistor. The thin film transistor comprises an active layer, a gate insulated and spaced with the active layer, an insulating layer, a source contacted with the active layer through a source via hole penetrating through the insulating layer as well as a drain contacted with the active layer through a drain via hole penetrating through the insulating layer, wherein the source via hole forms a stepped hole, and the drain via hole forms a stepped hole. The invention further provides an array substrate used for a display panel, the display panel and a manufacturing method of the thin film transistor. Compared with the prior art, a mask plate is used one less time less when the thin film transistor is manufactured, and accordingly, the manufacturing cost of the thin film transistor is reduced.

Description

Thin-film transistor and manufacture method, array base palte, display floater
Technical field
The present invention relates to field of display devices, particularly, relate to a kind of thin-film transistor, this thin-film transistor manufacture method, a kind ofly comprise the display floater of described thin-film transistor and the array base palte of this display floater.
Background technology
Diode displaying product, due to advantages such as high brightness, high-contrast, wide viewing angle, self-luminouss, receives people and more and more payes attention to.
Shown in Fig. 1 (a) to Fig. 1 (f) is the step of the thin-film transistor manufactured in prior art in light emitting display device, and as can be seen from the figure, in prior art, the method manufacturing thin-film transistor comprises the following steps:
As shown in Fig. 1 (a), substrate 500 forms resilient coating 600, active layer 100, gate insulator 210, grid 400 and interlayer insulating film 220 successively, gate insulator 210 and interlayer insulating film 220 form insulating barrier 200 jointly;
As shown in Fig. 1 (b), mask plate is utilized to carry out patterning processes to interlayer insulating film 220, to form source electrode via hole 410 and drain via 420 on interlayer insulating film 220;
As shown in Fig. 1 (c), form source and drain metal layer A;
As shown in Fig. 1 (d), source and drain metal layer A forms the first photoresist layer B;
As shown in Fig. 1 (e), mask plate is utilized to carry out photoetching process, to form mask pattern to the first photoresist layer B;
As shown in Fig. 1 (f), take mask pattern as mask, source and drain metal level is etched, to obtain source electrode 310 and drain electrode 320.
There is foregoing description known, after defining interlayer insulating film, still need use twice mask plate just can obtain final thin-film transistor.Therefore, manufacture thin-film transistor and need higher cost.
Therefore, how to reduce the cost manufacturing thin-film transistor and become this area technical problem urgently to be resolved hurrily.
Summary of the invention
The object of the present invention is to provide the manufacture method of a kind of thin-film transistor, this thin-film transistor, a kind ofly comprise the array base palte of described thin-film transistor and comprise the display floater of this array base palte.Manufacture method provided by the present invention is utilized to manufacture cost needed for thin-film transistor provided by the present invention lower.
To achieve these goals, as one aspect of the present invention, a kind of thin-film transistor is provided, described thin-film transistor includes active layer, the grid arranged with described active layer insulation gap, be arranged on the insulating barrier above described active layer, the drain electrode that the source electrode contacted with described active layer by the source electrode via hole running through described insulating barrier is contacted with described active layer with the drain via by running through described insulating barrier, wherein, described source electrode via hole comprises source portion and is formed in source electrode via portion through with this source portion below described source portion, the width of described source portion is greater than the width of described source electrode via portion, shoulder hole is formed as to make described source electrode via hole, described source electrode is formed in described source portion, the source conductive material connecting described active layer and described source electrode is filled with in described source electrode via portion, described drain via comprises drain portion and is formed in drain via portion through with this drain portion below described drain portion, the width of described drain portion is greater than the width in described drain via portion, shoulder hole is formed as to make described drain via, described drain electrode is formed in described drain portion, the Drain Electrodes Conductive materials connecting described active layer and described drain electrode is filled with in described drain via portion.
Preferably, described active layer is made up of polycrystalline silicon material.
Preferably, described insulating barrier comprises gate insulator and interlayer insulating film, described gate insulator covers described active layer, described grid is formed on described gate insulator, described interlayer insulating film covers described gate insulator, and described source portion and described drain portion are formed on described interlayer insulating film.
Preferably, described thin-film transistor comprises substrate and is arranged on the resilient coating between described active layer and described substrate.
As another aspect of the present invention, provide a kind of array base palte of display floater, described array base palte comprises thin-film transistor, and wherein, described thin-film transistor is above-mentioned thin-film transistor provided by the present invention.
As an also aspect of the present invention, provide a kind of display floater, described display floater comprises array base palte, and wherein, described array base palte is above-mentioned array base palte provided by the present invention.
Have an aspect as of the present invention, provide a kind of manufacture method of thin-film transistor, wherein, described manufacture method comprises:
Formation includes active layer;
Form gate insulator;
Form grid, described grid and described active layer insulation gap;
Form interlayer insulating film, described interlayer insulating film covers described grid and described gate insulator;
Form source electrode via hole and drain via, described source electrode via hole comprises source portion and source electrode via portion, described source electrode via portion is positioned at below described source portion, and it is through with described source portion, described source electrode via portion runs through described insulating barrier and arrives described active layer, the width of described source portion is greater than the width of described source electrode via portion, shoulder hole is formed as to make described source electrode via hole, described drain via portion is positioned at below described drain portion, and it is through with described drain portion, described drain via portion runs through described insulating barrier and arrives described active layer, the width of described drain portion is greater than the width in described drain via portion, shoulder hole is formed as to make described drain via,
Form source-drain electrode metal level, the metal material forming described source-drain electrode metal level is filled in described source electrode via hole and described drain via;
Form the first photoresist layer, described first photoresist layer covers described source-drain electrode metal level, and the upper surface of described first photoresist layer is plane;
Ashing is carried out to described first photoresist layer, removes the Other substrate materials of other parts except above described source electrode via hole and above described drain via in described first photoresist layer;
Be not coated with the metal material of the part of Other substrate materials in source-drain electrode metal level described in ablation, to obtain source electrode and drain electrode, described source electrode and drain electrode lay respectively in described source portion and described drain portion.
Preferably, the step forming source electrode via hole and drain via comprises:
Described insulating barrier is formed the second photoresist layer;
Intermediate tone mask plate is utilized to expose described second photoresist layer;
The second photoresist layer after exposure is developed;
Described insulating barrier is etched.
Preferably, described manufacture method is carried out before being also included in the step being formed with active layer:
Form resilient coating.
Preferably, the step being formed with active layer comprises:
Form amorphous silicon layer;
Amorphous silicon layer is annealed, to obtain polysilicon layer;
Patterning processes is carried out to polysilicon layer, to obtain described active layer.
In manufacture method provided by the present invention, when formed the substrate by source electrode via hole and drain via deposits source and drain metal level time, the surface of the source and drain metal level formed not is smooth, after source and drain metal material fills up source electrode via portion and drain via portion, one deck source and drain metal level is formed in source portion and drain portion, and, after defining source and drain metal level, source portion is still formed with depressed part, drain portion is still formed with depression.
Need subsequently to form one deck first photoresist layer at source and drain metal layer, the surface of the first photoresist layer can be arranged layer plane, therefore, the thickness of the first photoresist layer is not equal everywhere.Segment thickness corresponding to source electrode via hole and drain via is comparatively large, and the thickness corresponding to the part between source electrode via hole and drain via is less.Therefore, carry out the photoresist that a step cineration technics can remove the upper between source electrode via hole and drain via again after irradiating the first photoresist layer by mask plate, and the photoresist above source electrode via hole and drain via is retained, as shown in the figure.Now, then carry out a step etching technics and the metal material between source electrode via portion and drain via portion can be removed, to obtain source electrode and drain electrode, do not need to introduce mask plate again.Known by foregoing description, compared with prior art, when manufacturing thin-film transistor provided by the present invention, using a mask plate less, reducing the cost manufacturing described thin-film transistor.
Accompanying drawing explanation
Accompanying drawing is used to provide a further understanding of the present invention, and forms a part for specification, is used from explanation the present invention, but is not construed as limiting the invention with embodiment one below.In the accompanying drawings:
Fig. 1 (a), when making thin-film transistor, substrate is formed with the schematic diagram after active layer, gate insulator, grid and interlayer insulating film;
Fig. 1 (b) is in prior art, defines the schematic diagram after via hole;
Fig. 1 (c) is in prior art, defines the schematic diagram after source and drain metal level;
Fig. 1 (d) is in prior art, the schematic diagram after source and drain metal level defines photoresist;
Fig. 1 (e) is in prior art, the schematic diagram after utilizing photoresist to form mask pattern;
Fig. 1 (f) forms the schematic diagram of source-drain electrode figure after being through etching;
Fig. 2 (a) is in method provided by the present invention, defines the schematic diagram after via hole;
Fig. 2 (b) is in method provided by the present invention, defines the schematic diagram after source and drain metal level;
Fig. 2 (c) is in method provided by the present invention, the schematic diagram after source and drain metal level defines photoresist;
Fig. 2 (d) is in method provided by the present invention, the schematic diagram after utilizing photoresist to form mask pattern;
Fig. 2 (e) forms the schematic diagram of source-drain electrode after being through etching.
Description of reference numerals
100: active layer 200: insulating barrier
210: gate insulator 220: interlayer insulating film
310: source electrode 320: drain electrode
400: grid 410: source electrode via hole
411: source portion 412: source electrode via portion
420: drain via 421: drain portion
422: drain via portion 500: substrate
600: resilient coating A: source and drain metal level
B: the first photoresist layer
Embodiment
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.Should be understood that, embodiment described herein, only for instruction and explanation of the present invention, is not limited to the present invention.
As shown in Fig. 2 (e), as one aspect of the present invention, the grid 400 a kind of thin-film transistor is provided, this thin-film transistor includes active layer 100, arranging with this active layer 100 insulation gap, be arranged on insulating barrier 200 above active layer 100, drain electrode 320 that the source electrode 310 that contacted with active layer 100 by the source electrode via hole running through insulating barrier 200 is contacted with active layer 100 with the drain via by running through insulating barrier 200.Wherein, described source electrode via hole comprises source portion and is formed in source electrode via portion through with this source portion below described source portion, the width of described source portion is greater than the width of described source electrode via portion, shoulder hole is formed as to make described source electrode via hole, source electrode 310 is formed in described source portion, is filled with the source conductive material being connected with active layer 100 and source electrode 310 in described source electrode via portion.Described drain via comprises drain portion and is formed in drain via portion through with this drain portion below described drain portion, the width of described drain portion is greater than the width in described drain via portion, shoulder hole is formed as to make described drain via, drain electrode 320 is formed in described drain portion, is filled with the Drain Electrodes Conductive materials being connected with active layer 100 and drain electrode 320 in described drain via portion.
In the present invention, width measures along the left and right directions of Fig. 2 (e) size obtained.
Fig. 1 (a), Fig. 2 (a) illustrate the step manufacturing thin-film transistor provided by the present invention to Fig. 2 (e).By finding out in Fig. 2 (a), the source electrode via hole 410 being formed as shoulder hole comprises source portion 411 and source electrode via portion 412, and the width of source portion 411 is greater than the width of source electrode via portion 412.The drain via 420 being formed as shoulder hole comprises drain portion 421 and drain via portion 422.When formed the substrate by source electrode via hole 410 and drain via 420 deposits source and drain metal layer A time, the surface of the source and drain metal layer A formed not is smooth, after source and drain metal material fills up source electrode via portion 412 and drain via portion 422, one deck source and drain metal level is formed in source portion 411 and drain portion 421, and, after defining source and drain metal level, source portion is still formed with depressed part a, drain portion is still formed with depression b.
Need subsequently above source and drain metal layer A, form one deck first photoresist layer B, the surface of the first photoresist layer B can be arranged layer plane, therefore, the thickness of the first photoresist layer B is not equal everywhere.Segment thickness corresponding to source electrode via hole and drain via is comparatively large, and the thickness corresponding to the part between source electrode via hole and drain via is less, as shown in Fig. 2 (c).Therefore, the photoresist that a step cineration technics can remove the upper between source electrode via hole and drain via is carried out again after irradiating the first photoresist layer B by mask plate, and the photoresist above source electrode via hole and drain via is retained, as shown in Fig. 2 (d).Now, then carry out a step etching technics and the metal material between source electrode via portion and drain via portion can be removed, to obtain source electrode 310 and drain electrode 320, do not need to introduce mask plate again.
Known by foregoing description, compared with prior art, when manufacturing thin-film transistor provided by the present invention, using a mask plate less, reducing the cost manufacturing described thin-film transistor.
In the present invention, concrete restriction is not done to the material of active layer 100, such as, oxide can be utilized to make active layer 100, polycrystalline silicon material also can be utilized to make active layer 100.
Thin-film transistor shown in Fig. 2 (e) is a kind of top gate type thin film transistor, therefore, insulating barrier 200 comprises gate insulator 210 and interlayer insulating film 220, gate insulator 210 is coated with active layer 100, grid 400 is formed on gate insulator 210, interlayer insulating film 220 cover gate insulating barrier 210, described source portion and described drain portion are formed on interlayer insulating film 220.
It is easily understood that the major function of gate insulator 210 is by grid 400 and active layer 100 insulation gap, interlayer insulating film 220 Main Function be then by grid 410 and source electrode 310 insulation gap, and by grid 410 and drain electrode 320 insulation gaps.The material of interlayer insulating film can be silica, silicon nitride, silicon oxynitride etc., and the material of gate insulator can be silica, silicon nitride, silicon oxynitride, aluminium oxide etc.
It is easily understood that described thin-film transistor all comprises substrate 500, substrate 500 can be made up of glass usually.In order to prevent the Impurity Diffusion in glass to be with active layer 100, preferably, resilient coating 600 can be set between substrate 500 and active layer 100.Usually, the material of resilient coating 600 can be silica, silicon nitride, silicon oxynitride etc.
As another aspect of the present invention, provide a kind of array base palte of display floater, described array base palte comprises thin-film transistor, and wherein, described thin-film transistor is above-mentioned thin-film transistor provided by the present invention.
Because the technique manufacturing thin-film transistor provided by the present invention is comparatively simple, cost is lower, therefore, manufactures the cost also corresponding reduction comprising the array base palte of the display floater of described thin-film transistor.
Those skilled in the art are it is easily understood that when described array base palte is used for LED display panel, described array base palte comprises tft layer and light emitting element layer, and tft layer is arranged on the below of light emitting element layer.
As another aspect of the present invention, provide a kind of display floater, described display floater comprises array base palte, and wherein, described array base palte is above-mentioned array base palte provided by the present invention.
In the present invention, special restriction is not done to the particular type of display floater.Such as, described display floater can be display panels.In this situation, described display floater also comprise and described array base palte to box arrange to box substrate and be arranged on described to the liquid crystal material between box substrate and described array base palte.Again such as, described display floater can also be LED display panel, in this situation, described array base palte is provided with light-emitting diode, described display floater also comprise with described array base palte to box arrange to box substrate.
Similarly, because the cost manufacturing array base palte provided by the present invention reduces, therefore, the overall cost manufacturing display floater provided by the present invention is also lowered.
As another aspect of the invention, provide the manufacture method of above-mentioned thin-film transistor provided by the present invention, wherein, described manufacture method comprises:
Formation includes active layer 100;
Form gate insulator 210;
Form grid 300, this grid 300 is by gate insulator and active layer 100 insulation gap;
Form interlayer insulating film 220, this interlayer insulating film cover gate and gate insulator;
Form source electrode via hole 410 and drain via 420 (as Suo Shi Fig. 2 (a)), source electrode via hole 410 comprises source portion 411 and source electrode via portion 412, source electrode via portion 412 is positioned at below source portion 411, and it is through with this source portion 411, source electrode via portion 412 runs through insulating barrier 200 and arrives active layer 100, the width of source portion 411 is greater than the width of source electrode via portion 412, shoulder hole is formed as to make source electrode via hole 410, drain via portion 422 is positioned at below drain portion 421, and it is through with drain portion 421, drain via portion 422 runs through insulating barrier 200 and arrives active layer 100, the width of drain portion 421 is greater than the width in drain via portion 422, shoulder hole is formed as to make drain via 420,
Form source-drain electrode metal layer A (as Suo Shi Fig. 2 (b)), the metal material forming source-drain electrode metal layer A is filled in described source electrode via hole and described drain via;
Form the first photoresist layer B (as Fig. 2 (c)), this first photoresist layer B covers source-drain electrode metal layer A, and the upper surface of the first photoresist layer B is plane;
Ashing is carried out to the first photoresist layer B, removes the Other substrate materials (as Suo Shi Fig. 2 (d)) of other parts except above source electrode via hole and above drain via in the first photoresist layer B;
Be not coated with the metal material of the part of Other substrate materials in source-drain electrode metal level described in ablation, to obtain source electrode 310 and drain electrode 320, source electrode 310 and drain electrode 320 lay respectively in described source portion and described drain portion.
After cineration technics is carried out to the first photoresist layer B, only have above source electrode via hole 410 and drain via 420 and be coated with Other substrate materials.The metal material of the part not being coated with Other substrate materials in source-drain electrode metal level described in wet etching ablation can be utilized, namely utilize etching liquid will not to be coated with the metal material ablation of the part of Other substrate materials in described source-drain electrode metal level, remaining metal just defines source electrode and drain electrode.Certainly, also the metal material of the part not being coated with Other substrate materials in source-drain electrode metal level described in dry etching ablation can be utilized, when utilizing dry etching, strictly to control the time of dry etching, to guarantee to etch away the metal material and remaining photoresist that are not coated with the part of Other substrate materials in described source-drain electrode metal level, source electrode and drain electrode can be retained again.
When carrying out ashing to the first photoresist layer, need to pass into plasma in the process cavity of carrying out cineration technics.It is known in those skilled in the art for how carrying out cineration technics, repeats no more here.
It is easily understood that gate insulator 210 and interlayer insulating film 220 constitute the insulating barrier 200 be positioned at above active layer jointly.
As noted before, in manufacture method provided by the present invention, when formed the substrate by source electrode via hole 410 and drain via 420 deposits source and drain metal layer A time, the surface of the source and drain metal layer A formed not is smooth, after source and drain metal material fills up source electrode via portion 412 and drain via portion 422, one deck source and drain metal level is formed in source portion 411 and drain portion 421, and, after defining source and drain metal level, source portion is still formed with depressed part a, drain portion is still formed with depression b.
Need subsequently above source and drain metal layer A, form one deck first photoresist layer B, plane can be arranged in the surface of the first photoresist layer B, therefore, the thickness of the first photoresist layer B is not equal everywhere.Be coated with Other substrate materials above source and drain metal layer A after, scraper plate can be utilized to be struck off on the surface of photoresist, be formed as plane to make the surface of the first photoresist layer B.Segment thickness corresponding to source electrode via hole and drain via is comparatively large, and the thickness corresponding to the part between source electrode via hole and drain via is less, as shown in Fig. 2 (c).Therefore, the photoresist that a step cineration technics can remove the upper between source electrode via hole and drain via is carried out again after irradiating the first photoresist layer B by mask plate, and the photoresist above source electrode via hole and drain via is retained, as shown in Fig. 2 (d).Now, then carry out a step etching technics and the metal material between source electrode via portion and drain via portion can be removed, to obtain source electrode 310 and drain electrode 320, do not need to introduce mask plate again.
Known by foregoing description, compared with prior art, when manufacturing thin-film transistor provided by the present invention, using a mask plate less, reducing the cost manufacturing described thin-film transistor.
In the present invention, intermediate tone mask plate can be utilized to form described source electrode via hole and described drain via, particularly, the step forming source electrode via hole and drain via comprises:
Insulating barrier 200 is formed the second photoresist layer;
Intermediate tone mask plate is utilized to expose described second photoresist layer;
The second photoresist layer after exposure is developed;
Described insulating barrier is etched.
Utilizing intermediate tone mask plate to form source electrode via hole and drain via can the manufacture method of thin-film transistor described in Simplified flowsheet.
Described intermediate tone mask plate comprises light tight district, semi-opaque region and transparent area.The position of light tight district, semi-opaque region and transparent area can be determined according to the concrete material of the second photoresist layer.Such as, when utilizing positive photoresist to form described second photoresist layer, the position in described light tight district corresponds to the position in described source electrode via portion and described drain via portion, the position of described semi-opaque region corresponds to the position of described source portion and described drain portion, and described other parts of intermediate tone mask plate are transparent area.When utilizing negative photoresist to form described second photoresist layer, the position of described light tight district and described transparent area is with to utilize positive photoresist to form the situation of described second photoresist layer contrary.That is, the position of described transparent area corresponds to the position in described source electrode via portion and described drain via portion, and other parts described intermediate tone mask plate removed outside described transparent area and described semi-opaque region are transparent area.
As noted before, described thin-film transistor comprises substrate 500, and in order to prevent the Impurity Diffusion in substrate to be with in active layer 100, preferably, described manufacture method is carried out before being also included in the step being formed with active layer 100:
Form resilient coating 600.
As a kind of preferred implementation of the present invention, polycrystalline silicon material can be utilized to make active layer 100.Particularly, the step being formed with active layer comprises:
Form amorphous silicon layer;
Amorphous silicon layer is annealed, to obtain polysilicon layer;
Patterning processes is carried out to polysilicon layer, to obtain described active layer.
Herein, carry out patterning processes to polysilicon layer can comprise the following steps:
Form the 3rd photoresist layer on the polysilicon layer;
To utilizing mask plate to carry out exposure imaging to the 3rd photoresist layer, to form the mask pattern corresponding to active layer;
Other parts on polysilicon layer except the part covered by mask pattern are etched, to obtain described active layer.
As noted before, utilize manufacture method provided by the present invention to manufacture thin-film transistor provided by the present invention and can reduce the number of times using mask plate, thus simplify the step manufacturing thin-film transistor, and then reduce the total cost manufacturing thin-film transistor.
Be understandable that, the illustrative embodiments that above execution mode is only used to principle of the present invention is described and adopts, but the present invention is not limited thereto.For those skilled in the art, without departing from the spirit and substance in the present invention, can make various modification and improvement, these modification and improvement are also considered as protection scope of the present invention.

Claims (10)

1. a thin-film transistor, described thin-film transistor includes active layer, the grid arranged with described active layer insulation gap, be arranged on the insulating barrier above described active layer, the drain electrode that the source electrode contacted with described active layer by the source electrode via hole running through described insulating barrier is contacted with described active layer with the drain via by running through described insulating barrier, it is characterized in that, described source electrode via hole comprises source portion and is formed in source electrode via portion through with this source portion below described source portion, the width of described source portion is greater than the width of described source electrode via portion, shoulder hole is formed as to make described source electrode via hole, described source electrode is formed in described source portion, the source conductive material connecting described active layer and described source electrode is filled with in described source electrode via portion, described drain via comprises drain portion and is formed in drain via portion through with this drain portion below described drain portion, the width of described drain portion is greater than the width in described drain via portion, shoulder hole is formed as to make described drain via, described drain electrode is formed in described drain portion, the Drain Electrodes Conductive materials connecting described active layer and described drain electrode is filled with in described drain via portion.
2. thin-film transistor according to claim 1, is characterized in that, described active layer is made up of polycrystalline silicon material.
3. thin-film transistor according to claim 1, it is characterized in that, described insulating barrier comprises gate insulator and interlayer insulating film, described gate insulator covers described active layer, described grid is formed on described gate insulator, described interlayer insulating film covers described gate insulator, and described source portion and described drain portion are formed on described interlayer insulating film.
4. thin-film transistor according to claim 3, is characterized in that, described thin-film transistor comprises substrate and is arranged on the resilient coating between described active layer and described substrate.
5. an array base palte, described array base palte comprises thin-film transistor, it is characterized in that, described thin-film transistor is the thin-film transistor in Claims 1-4 described in any one.
6. a display floater, described display floater comprises array base palte, it is characterized in that, described array base palte is array base palte according to claim 5.
7. a manufacture method for thin-film transistor, is characterized in that, described manufacture method comprises:
Formation includes active layer;
Form gate insulator;
Form grid, described grid is by described gate insulator and described active layer insulation gap;
Form interlayer insulating film, described interlayer insulating film covers described grid and described gate insulator;
Form source electrode via hole and drain via, described source electrode via hole comprises source portion and source electrode via portion, described source electrode via portion is positioned at below described source portion, and it is through with described source portion, described source electrode via portion runs through described insulating barrier and arrives described active layer, the width of described source portion is greater than the width of described source electrode via portion, shoulder hole is formed as to make described source electrode via hole, described drain via portion is positioned at below described drain portion, and it is through with described drain portion, described drain via portion runs through described insulating barrier and arrives described active layer, the width of described drain portion is greater than the width in described drain via portion, shoulder hole is formed as to make described drain via,
Form source-drain electrode metal level, the metal material forming described source-drain electrode metal level is filled in described source electrode via hole and described drain via;
Form the first photoresist layer, described first photoresist layer covers described source-drain electrode metal level, and the upper surface of described first photoresist layer is plane;
Ashing is carried out to described first photoresist layer, removes the Other substrate materials of other parts except above described source electrode via hole and above described drain via in described first photoresist layer;
Be not coated with the metal material of the part of Other substrate materials in source-drain electrode metal level described in ablation, to obtain source electrode and drain electrode, described source electrode and drain electrode lay respectively in described source portion and described drain portion.
8. manufacture method according to claim 7, is characterized in that, the step forming source electrode via hole and drain via comprises:
Described insulating barrier is formed the second photoresist layer;
Intermediate tone mask plate is utilized to expose described second photoresist layer;
The second photoresist layer after exposure is developed;
Described insulating barrier is etched.
9. the manufacture method according to claim 7 or 8, is characterized in that, described manufacture method is carried out before being also included in the step being formed with active layer:
Form resilient coating.
10. the manufacture method according to claim 7 or 8, is characterized in that, the step being formed with active layer comprises:
Form amorphous silicon layer;
Amorphous silicon layer is annealed, to obtain polysilicon layer;
Patterning processes is carried out to polysilicon layer, to obtain described active layer.
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