CN104465788A - Thin film transistor, preparing method of thin film transistor, array substrate, preparing method of array substrate and display device - Google Patents
Thin film transistor, preparing method of thin film transistor, array substrate, preparing method of array substrate and display device Download PDFInfo
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- CN104465788A CN104465788A CN201510001865.4A CN201510001865A CN104465788A CN 104465788 A CN104465788 A CN 104465788A CN 201510001865 A CN201510001865 A CN 201510001865A CN 104465788 A CN104465788 A CN 104465788A
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- 238000000034 method Methods 0.000 title claims abstract description 85
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- 239000010410 layer Substances 0.000 claims abstract description 207
- 239000004065 semiconductor Substances 0.000 claims abstract description 101
- 239000011229 interlayer Substances 0.000 claims abstract description 76
- 239000010408 film Substances 0.000 claims description 85
- 238000009413 insulation Methods 0.000 claims description 44
- 238000000059 patterning Methods 0.000 claims description 39
- 229910044991 metal oxide Inorganic materials 0.000 claims description 34
- 150000004706 metal oxides Chemical group 0.000 claims description 34
- 238000002360 preparation method Methods 0.000 claims description 28
- 229910052751 metal Inorganic materials 0.000 claims description 15
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- 229910052738 indium Inorganic materials 0.000 description 8
- 238000002161 passivation Methods 0.000 description 8
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- 229910020923 Sn-O Inorganic materials 0.000 description 3
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- 229910052718 tin Inorganic materials 0.000 description 3
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- 229910052721 tungsten Inorganic materials 0.000 description 2
- YSRUGFMGLKANGO-UHFFFAOYSA-N zinc hafnium(4+) indium(3+) oxygen(2-) Chemical compound [O-2].[Zn+2].[In+3].[Hf+4] YSRUGFMGLKANGO-UHFFFAOYSA-N 0.000 description 2
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- TYHJXGDMRRJCRY-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) tin(4+) Chemical compound [O-2].[Zn+2].[Sn+4].[In+3] TYHJXGDMRRJCRY-UHFFFAOYSA-N 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
Abstract
The embodiment of the invention provides a thin film transistor, a preparing method of the thin film transistor, an array substrate, a preparing method of the array substrate and a display device, and relates to the technical field of displaying. The grid control capability of the thin film transistor can be enhanced, the performance of the thin film transistor can be kept stable for a long time, and the service life of the thin film transistor can be further prolonged. The thin film transistor comprises a first grid electrode, a grid insulating layer located on the first grid electrode, a semiconductor active layer located on the grid insulating layer, a source electrode and a drain electrode, wherein the source electrode and the drain electrode are in contact with the semiconductor active layer. The thin film transistor further comprises an interlayer insulating layer and a second grid layer, wherein the interlayer insulating layer is arranged between the second grid electrode and the semiconductor active layer. The thin film transistor can be used for manufacturing a display component.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of thin-film transistor and preparation method, array base palte and preparation method, display unit.
Background technology
Along with the development of Display Technique, flat-panel monitor has progressively goed deep into the life of people.Flat-panel monitor common at present mainly comprises LCD (Liquid Crystal Display, liquid crystal display) and OLED (Organic Light-Emitting Diode, Organic Light Emitting Diode) display.In imaging process, each pixel cell is driven by the TFT be integrated on array base palte (Thin Film Transistor, thin-film transistor), by the control of peripheral drive circuit, to realize image display.
In above-mentioned display, TFT is the switch controlling image display, is the key realizing LCD and OLED display, is directly connected to further developing of high performance flat display.But traditional TFT only comprises a grid; The grid-control ability of single grid TFT is relatively weak, TFT so just can be made easily short-channel effect to occur, thus cause its unstable properties, and affects the useful life of TFT further.
Summary of the invention
Embodiments of the invention provide a kind of thin-film transistor and preparation method, array base palte and preparation method, display unit, can the grid-control ability of enhanced film transistor, to make the property retention of described thin-film transistor steady in a long-term, and improve its useful life further.
For achieving the above object, embodiments of the invention adopt following technical scheme:
On the one hand, provide a kind of thin-film transistor, comprise first grid, be positioned at gate insulation layer above described first grid, be positioned at the semiconductor active layer above described gate insulation layer, the source electrode contacted with described semiconductor active layer and drain electrode; It is characterized in that, also comprise interlayer insulating film and second grid; Wherein, described interlayer insulating film is arranged between described second grid and described semiconductor active layer.
Optionally, described second grid is electrically connected with described first grid by least gate contact hole be arranged in described gate insulation layer and described interlayer insulating film.
Optionally, described semiconductor active layer is metal-oxide semiconductor (MOS) active layer.
Further alternative, described interlayer insulating film is etching barrier layer.
Preferably, described second grid and described source electrode and described drain electrode are arranged with layer.
Further preferred, described second grid and described source electrode and described drain electrode are metal electrode.
A kind of array base palte is also provided, comprises above-mentioned thin-film transistor.
Optionally, described array base palte also comprises the pixel electrode be electrically connected with the drain electrode of described thin-film transistor; Wherein, described second grid and described pixel electrode are arranged with layer.
A kind of display unit is also provided, comprises above-mentioned array base palte.
On the other hand, there is provided a kind of preparation method of thin-film transistor, described method comprises: form first grid, be positioned at gate insulation layer above described first grid, be positioned at the semiconductor active layer above described gate insulation layer, the source electrode contacted with described semiconductor active layer and drain electrode; Described method also comprises: form interlayer insulating film; And formation second grid; Wherein, described interlayer insulating film is formed between described second grid and described semiconductor active layer.
Optionally, described method is also included in the step forming gate contact hole in described gate insulation layer and described interlayer insulating film; Wherein, described second grid is electrically connected with described first grid by described gate contact hole.
Preferably, described second grid and described source electrode and described drain electrode are formed by a patterning processes.
Preferred further, the forming step of described semiconductor active layer specifically comprises: above described gate insulation layer, form metal oxide semiconductor films, and forms metal-oxide semiconductor (MOS) active layer by a patterning processes; The forming step of described source electrode and described drain electrode and described second grid specifically comprises: above described interlayer insulating film, form membrane of conducting layer, with described interlayer insulating film for etching barrier layer, form described source electrode and described drain electrode and described second grid by patterning processes; Wherein, described second grid is electrically connected with described first grid by described gate contact hole.
Further, describedly above described interlayer insulating film, form membrane of conducting layer be specially: at the disposed thereon metal layer thin film of described interlayer insulating film.
Also provide a kind of preparation method of array base palte, described method comprises the preparation method of above-mentioned thin-film transistor.
Optionally, described method also comprises the pixel electrode being formed and be electrically connected with the drain electrode of described thin-film transistor; Wherein, described second grid and described pixel electrode are formed by a patterning processes.
Embodiments of the invention provide a kind of thin-film transistor and preparation method, array base palte and preparation method, display unit.Based on this, by thin-film transistor described in described first grid and described second grid co-controlling, thus effective its grid-control ability of enhancing, make the property retention of described thin-film transistor steady in a long-term, and improve its useful life further.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
The structural representation one of the thin-film transistor that Fig. 1 provides for embodiments of the invention;
The structural representation two of the thin-film transistor that Fig. 2 provides for embodiments of the invention;
The structural representation three of the thin-film transistor that Fig. 3 provides for embodiments of the invention;
The structural representation four of the thin-film transistor that Fig. 4 provides for embodiments of the invention;
The structural representation one of the array base palte that Fig. 5 provides for embodiments of the invention;
The structural representation two of the array base palte that Fig. 6 provides for embodiments of the invention;
The structural representation three of the array base palte that Fig. 7 provides for embodiments of the invention;
The structural representation four of the array base palte that Fig. 8 provides for embodiments of the invention;
Preparation method's flow chart of the thin-film transistor that Fig. 9 provides for embodiments of the invention;
The preparation process schematic diagram of the thin-film transistor that Figure 10 (a) provides to 10 (h) for embodiments of the invention and array base palte;
The forming process schematic diagram that Figure 11 (a) is the interlayer insulating film shown in Figure 10 (c) to 11 (d);
Preparation method's flow chart of the array base palte that Figure 12 provides for embodiments of the invention.
Reference numeral:
10-thin-film transistor; 100-substrate; 101-first grid; 102-gate insulation layer; 103-semiconductor active layer; 104-source electrode; 105-drains; 106-interlayer insulating film; 1060-insulating layer of thin-film; 107-second grid; 108-source contact openings; 109-drain contact hole; 110-gate contact hole; 111-passivation layer; 112-pixel electrode contact hole; 20-pixel electrode; 30-photoresist; The complete reserve part of 301-photoresist; 302-photoresist half reserve part.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Embodiments of the invention provide a kind of thin-film transistor 10, as shown in Figures 1 to 4, comprise first grid 101, be positioned at gate insulation layer 102 above described first grid 101, be positioned at semiconductor active layer 103, the source electrode 104 contacted with described semiconductor active layer 103 above described gate insulation layer 102 and drain 105; On this basis, described thin-film transistor 10 also comprises interlayer insulating film 106 and second grid 107; Wherein, described interlayer insulating film 106 is arranged between described second grid 107 and described semiconductor active layer 103.
Concrete, described interlayer insulating film 106 can be arranged on described source electrode 104 and between described drain electrode 105 and described semiconductor active layer 103 and/or be arranged on the side that described source electrode 104 and described drain electrode 105 deviate from described semiconductor active layer 103.
It should be noted that, first, described source electrode 104 and need to remain in contact with one another between described drain electrode 105 and described semiconductor active layer 103, here described source electrode 104 and described drain electrode 105 are not specifically limited with the way of contact of described semiconductor active layer 103, it can directly be overlapped on described semiconductor active layer 103, can certainly realize the contact with described semiconductor active layer 103 by contact hole.Wherein, at described source electrode 104 with when being also provided with interlayer insulating film 106 between described drain electrode 105 and described semiconductor active layer 103, just contact hole need be set in described interlayer insulating film 106, can be contacted with described semiconductor active layer 103 by described contact hole to make described source electrode 104 and described drain electrode 105.
The second, described first grid 101 and described second grid 107, for controlling described thin-film transistor 10, therefore need to be connected with signal control line, so that provide control signal for it; On this basis, the signal control line be connected with described second grid 107 with described first grid 101 can be identical, also can be different.Embodiments of the invention are not specifically limited for the control mode of described first grid 101 and described second grid 107.
3rd, described interlayer insulating film 106 refers to the patterned layer being positioned at and having insulation effect between layers, it may comprise one deck (as shown in Figure 1 to Figure 3) or multilayer (as shown in Figure 4), specifically should be as the criterion with the practical structures of described thin-film transistor 10.
Embodiments of the invention provide a kind of thin-film transistor 10, comprise first grid 101, be positioned at gate insulation layer 102 above described first grid 101, be positioned at semiconductor active layer 103, the source electrode 104 contacted with described semiconductor active layer 103 above described gate insulation layer 102 and drain 105; On this basis, described thin-film transistor 10 also comprises interlayer insulating film 106 and second grid 107; Wherein, described interlayer insulating film 106 is arranged between described second grid 107 and described semiconductor active layer 103.
Based on this, embodiments of the invention are by thin-film transistor 10 described in described first grid 101 and described second grid 107 co-controlling, thus effectively can strengthen its grid-control ability, make the property retention of described thin-film transistor 10 steady in a long-term, and improve its useful life further.
Based on foregoing description, optionally, described second grid 107 realizes being electrically connected with described first grid 101 by least gate contact hole be arranged in gate insulation layer 102 and interlayer insulating film 106.
Here it should be noted that, described being at least arranged in gate insulation layer 102 and interlayer insulating film 106 specifically refers to: for the structure of different thin-film transistors, the insulating barrier more than described gate insulation layer 102 of possibility between described first grid 101 and described second grid 107 and described interlayer insulating film 106; In the case, to realize the electrical connection between described first grid 101 and described second grid 107, just in all insulating barriers between described first grid 101 and described second grid 107, described gate contact hole need be all set.
Like this, described first grid 101 and described second grid 107 can be controlled by same signal control line such as grid line, thus avoid the circuit that causes because introducing signal control line respectively lengthy and jumbled.
On this basis, optionally, described semiconductor active layer 103 can be metal-oxide semiconductor (MOS) active layer.
Wherein, the material of described metal-oxide semiconductor (MOS) active layer can be amorphous IGZO (Indium Gallium Zinc Oxide, indium gallium zinc oxide), ITZO (Indium Tin ZincOxide, indium tin zinc oxide), HIZO (Hafnium Indium Zinc Oxide, hafnium indium-zinc oxide), IZO (Indium Zinc Oxide, indium-zinc oxide), a-InZnO, ZnO:F, In
2o
3: Sn, In
2o
3: Mo, Cd
2snO
4, ZnO:Al, TiO
2: any one in the transparent metal oxide semi-conducting materials such as Nb and Cd-Sn-O.
Here, with described transparent metal oxide semi-conducting material for base material prepare described semiconductor active layer 103 time, relatively high carrier mobility can be obtained; Like this, under the prerequisite that other condition is equivalent, the volume of described thin-film transistor 10 is reduced, and makes flat-panel monitor can obtain higher resolution.In addition, metal oxide thin-film transistor also has the advantages such as stability is high, band gap large, materials and process advantage of lower cost.Further, when described semiconductor active layer 103 is metal-oxide semiconductor (MOS) active layer, the formation of double-gate structure effectively can also reduce the threshold voltage shift of metal-oxide semiconductor (MOS) active layer, thus strengthens the stability of metal oxide thin-film transistor 10.
Based on foregoing description, shown in figure 1 and Fig. 3, when described semiconductor active layer 103 is metal-oxide semiconductor (MOS) active layer, described interlayer insulating film 106 is preferably arranged on described source electrode 104 and between described drain electrode 105 and described semiconductor active layer 103; In the case, described interlayer insulating film 106 can also as etching barrier layer.
Now, described source electrode 104 can contact with described semiconductor active layer 103 with drain contact hole respectively by the source contact openings be arranged in described interlayer insulating film 106 with described drain electrode 105.
Like this, when forming described source electrode 104 and described drain electrode 105 above described metal-oxide semiconductor (MOS) active layer, because described interlayer insulating film 106 is positioned on described semiconductor active layer 103, therefore can be described semiconductor active layer 103 and play etch stopper, described semiconductor active layer 103 can be made when being formed described source electrode 104 and described drain electrode 105 by etching technics to be etched away.
On this basis, preferably, described second grid 107 can be arranged with layer with described source electrode 104 and described drain electrode 105, and preferably, three has identical material.
It should be noted that, same layer described here arranges and in fact refers to that described source electrode 104 and described drain electrode 105 and described second grid 107 are by a same patterning processes, and preferably, three can be obtained by identical rete.By making described source electrode 104 and described drain electrode 105 and described second grid 107 being formed with in a patterning processes, not only can simplify preparation technology, can also material be saved simultaneously.Compared to the thin-film transistor of grid structure single in prior art, embodiments of the invention can prepare the thin-film transistor with double-gate structure under the prerequisite not increasing patterning processes number of times, thus improve the grid-control ability of described thin-film transistor 10, and extend its useful life further.
Further, described source electrode 104 and described drain electrode 105 and described second grid 107 are preferably metal electrode.
Like this, described second grid 107 not only can with thin-film transistor 10 described in described first grid 101 co-controlling, and due to described second grid 107 adopt opaque metal material obtain, it can also block above described semiconductor active layer 103, thus weaken the drift of the metal-oxide semiconductor (MOS) threshold voltage that illumination causes, to ensure the stability of described thin-film transistor 10.
Embodiments of the invention also provide a kind of array base palte, as shown in Figure 5 and Figure 6, comprise above-mentioned thin-film transistor 10, and the pixel electrode 20 be electrically connected with the drain electrode 105 of described thin-film transistor 10.
Wherein, the mode that described pixel electrode 20 is electrically connected with described drain electrode 105 can comprise following two kinds: the first, and shown in figure 5, described pixel electrode 20 is directly put up a bridge and is connected to the top of described drain electrode 105; The second, shown in figure 6, described pixel electrode 20 is connected with described drain electrode 105 by the pixel electrode contact hole be arranged in the passivation layer 111 above described thin-film transistor 10.
On this basis, preferably, as shown in Figure 7, described second grid 107 can be arranged with layer with described pixel electrode 20, and has identical material.
It should be noted that, described same layer arranges and refers to, described second grid 107 and described pixel electrode 20 are by a same patterning processes, and preferably, both are obtained by identical rete.
Known based on foregoing description, described second grid 107 is also likely formed by a same patterning processes with described source electrode 104 and described drain electrode 105; In the case, described source electrode 104 and described drain electrode 105, described second grid 107 and described pixel electrode 20 all being obtained by identical rete with in a patterning processes, now just need all to be set to transparency electrode by with top electrode.
Certainly, in an embodiment of the present invention, described second grid 107 also can only be arranged with layer with described source electrode 104 and described drain electrode 105; Or described second grid 107 can also only be arranged with layer with described pixel electrode 20.In both cases, the material of described second grid 107 other electrode that only need arrange with same layer is consistent.
Example, when the second grid 107 of described thin-film transistor 10 is arranged with the source electrode 104 of described thin-film transistor 10 and 105 different layers that drain, consider the simplification of preparation technology, described second grid 107 just can with described pixel electrode 20 by being formed with a patterning processes.Now, described second grid 107 is transparency electrode with described pixel electrode 20.
Or, as shown in Figure 8, when the second grid 107 of described thin-film transistor 10 is arranged with the source electrode 104 of described thin-film transistor 10 and 105 different layers that drain, described pixel electrode 20 can also to be arranged on described source electrode 104 and described drain electrode 105 and to be laid in the surface of whole substrate; Now, relative with described thin-film transistor 10 partial pixel electrode also can be used as described second grid 107 simultaneously.
Like this, described second grid 107 is actually a part for described pixel electrode 20, and because described pixel electrode 20 is electrically connected with described drain electrode 105, therefore the control signal of described second grid 107 is provided by the data wire controlling described drain electrode 105; Meanwhile, the control signal of described first grid 101 is provided by grid line.It can thus be appreciated that the control signal based on two grids of the thin-film transistor of said structure is provided by different signal control lines.
On this basis, optionally, described array base palte can also comprise public electrode (not shown).
Embodiments of the invention also provide a kind of display unit, comprise above-mentioned array base palte.
Known based on foregoing description, the described thin-film transistor 10 that embodiments of the invention provide has double-gate structure, and it comprises first grid 101 and second grid 107 simultaneously.Utilize each pixel cell that the thin-film transistor 10 of this double-gate structure controls in described array base palte, described thin-film transistor 10 grid-control ability can be strengthened, the property retention of described thin-film transistor 10 is stablized, and strengthens its useful life further.
Accordingly, embodiments of the invention also provide a kind of preparation method of thin-film transistor 10, and described method comprises: form first grid 101, be positioned at gate insulation layer 102 above described first grid 101, be positioned at semiconductor active layer 103, the source electrode 104 contacted with described semiconductor active layer 103 above described gate insulation layer 102 and drain 105; On this basis, described method also comprises: form interlayer insulating film 106 and form second grid 107; Wherein, described interlayer insulating film 106 is formed between described second grid 107 and described semiconductor active layer 103.
Concrete, described interlayer insulating film 103 can be formed in described semiconductor active layer 103 and between described source electrode 104 and described drain electrode 105 and/or be formed in the side that described source electrode 104 and described drain electrode 105 deviate from described semiconductor active layer 103.
The described thin-film transistor 10 formed based on said method can comprise following structure:
The first, shown in figure 1 and Fig. 3, described thin-film transistor 10 comprises the first grid 101 set gradually on the substrate 100, gate insulation layer 102, semiconductor active layer 103, interlayer insulating film 106, the source electrode 104 arranged with layer and drain 105 and second grid 107.
The second, shown in figure 2, described thin-film transistor 10 comprises the first grid 101 set gradually on the substrate 100, gate insulation layer 102, semiconductor active layer 103, source electrode 104 and drain electrode 105, interlayer insulating film 106, and second grid 107.
3rd, shown in figure 4, described thin-film transistor 10 comprises the first grid 101 set gradually on the substrate 100, gate insulation layer 102, semiconductor active layer 103, interlayer insulating film 106, source electrode 104 and drain electrode 105, interlayer insulating film 106, and second grid 107.
Based on this, by forming the above-mentioned thin-film transistor 10 with double-gate structure, effectively can strengthen the grid-control ability of described thin-film transistor 10, making the property retention of described thin-film transistor 10 steady in a long-term, and improving its useful life further.
Here, because described thin-film transistor 10 has double-gate structure, the side deviating from described semiconductor active layer 103 at described interlayer insulating film 106 is also formed with described second grid 107, therefore via hole should be provided with in the insulating barrier (comprising described gate insulation layer 102 and described interlayer insulating film 106) between described first grid 101 and described second grid 107, i.e. described gate contact hole, can keep electrical connection to make described first grid 101 and described second grid 107.
On this basis, described method can also be included in the step forming gate contact hole in described gate insulation layer 102 and described interlayer insulating film 106.
So, described second grid 107 just can realize being electrically connected with described first grid 101 by described gate contact hole.In the case, described first grid 101 and described second grid 107 just can be controlled by same signal, thus the circuit avoided signal control line various and cause is lengthy and jumbled.
Based on above-mentioned, described semiconductor active layer 103 can be metal-oxide semiconductor (MOS) active layer.The forming step of described metal-oxide semiconductor (MOS) active layer specifically can comprise: above described gate insulation layer 102, form metal oxide semiconductor films, and forms metal-oxide semiconductor (MOS) active layer by a patterning processes.
Wherein, the material of described metal oxide semiconductor films can be amorphous IGZO, ITZO, HIZO, IZO, a-InZnO, ZnO:F, In
2o
3: Sn, In
2o
3: Mo, Cd
2snO
4, ZnO:Al, TiO
2: any one in the transparent metal oxide semi-conducting materials such as Nb and Cd-Sn-O.
Because metal-oxide semiconductor (MOS) active layer has relatively high carrier mobility, therefore can, under the prerequisite that other condition is identical, the volume of described thin-film transistor 10 be reduced, thus improve the resolution of flat-panel monitor.In addition, metal oxide thin-film transistor also has the advantages such as stability is high, band gap large, materials and process advantage of lower cost.Further, when described semiconductor active layer 103 is metal-oxide semiconductor (MOS) active layer, the formation of double-gate structure effectively can also reduce the threshold voltage shift of metal-oxide semiconductor (MOS) active layer, thus strengthens the stability of metal oxide thin-film transistor 10.
In an embodiment of the present invention, described second grid 107 is formed preferably by with a patterning processes with described source electrode 104 and described drain electrode 105.
So, by making described source electrode 104 and described drain electrode 105 and described second grid 107 being formed with in a patterning processes, not only can simplify preparation technology, can also material be saved simultaneously.
Here, the forming step of described source electrode 104 and drain electrode 105 and second grid 107 specifically can comprise: above described interlayer insulating film 106, form membrane of conducting layer, with described interlayer insulating film 106 for etching barrier layer, form described source electrode 104 and described drain electrode 105 and described second grid 107 by patterning processes; Wherein, described second grid 107 passes through at least gate contact hole be formed in described interlayer insulating film 106 and described gate insulation layer 102 and is electrically connected with described first grid 101, and the mode that described source electrode 104 is connected by overlap joint or via hole with described drain electrode 105 contacts with described semiconductor active layer 103.
Based on this, at described source electrode 104 with when being also formed with interlayer insulating film 106 between described drain electrode 105 and described semiconductor active layer 103, just need in described interlayer insulating film 106 to be formed for the gate contact hole that makes described second grid 107 and described first grid 101 be electrically connected and for the source contact openings that makes described source electrode 104 and described drain electrode 105 contact with described semiconductor active layer 103 respectively and drain contact hole.
On this basis, the concrete forming step of described interlayer insulating film 106 can comprise: on the substrate being formed with described semiconductor active layer 103, form insulating layer of thin-film, and is formed the interlayer insulating film 106 comprising gate contact hole, source contact openings and drain contact hole by patterning processes; Described gate contact hole is at least also formed in described gate insulation layer 102; Wherein, described first grid 101 exposes by described gate contact hole; Described semiconductor active layer 103 exposes by described source contact openings and described drain contact hole respectively.
So, in follow-up preparation technology, described second grid 107 just can be electrically connected with described first grid 101 by described gate contact hole, and described source electrode 104 and described drain electrode 105 just can be contacted with described semiconductor active layer 103 with described drain contact hole by described source contact openings.
Further, when being formed described source electrode 104 and drain electrode 105 and second grid 107 by patterning processes, can directly at the disposed thereon metal layer thin film of described interlayer insulating film 106 using as membrane of conducting layer.That is, described source electrode 104 and described drain electrode 105 and described second grid 107 obtain by metal material.
Like this, described second grid 107 adopts opaque metal material to obtain, interception can be played above described semiconductor active layer 103, thus weaken the drift of the metal-oxide semiconductor (MOS) threshold voltage that illumination causes, to ensure the stability of described thin-film transistor 10.
Below the preparation method providing a specific embodiment to described thin-film transistor 10 is described in detail.
The preparation method of described thin-film transistor 10 as shown in Figure 9, specifically comprises:
S101, as shown in Figure 10 (a), form first grid 101 on the substrate 100 by a patterning processes.
Here, the forming process of described first grid 101 specifically can comprise: adopt sputtering method or thermal evaporation at the surface deposition metal layer thin film of described substrate 100, and form described first grid 101 by a patterning processes.
Wherein, the thickness of described metal layer thin film is about
it can be single thin film or plural layers; The material of described metal layer thin film can select the metals such as Cr, W, Cu, Ti, Ta, Mo or its alloy.
S102, as shown in Figure 10 (b), the substrate being formed with described first grid 101 forms gate insulation layer 102.
Concrete, the forming process of described gate insulation layer 102 can comprise: be about at the disposed thereon thickness of described first grid 101 by PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition) method
insulating layer of thin-film, to form described gate insulation layer 102.
Wherein, the material of described insulating layer of thin-film can select any one in oxide, nitride and oxynitrides.When forming silica by PECVD method, required reacting gas is SiH
4and N
2o; When forming nitride by PECVD method, required reacting gas is SiH
4, NH
3and N
2; When forming oxynitrides by PECVD method, required reacting gas is SiH
2cl
2, NH
3and N
2.
Shown in S103, reference Figure 10 (b), on the substrate being formed with described gate insulation layer 102, form semiconductor active layer 103 by a patterning processes.
Here, the forming process of described semiconductor active layer 103 specifically can comprise: adopt sputtering method or thermal evaporation at the disposed thereon layer of metal oxide semiconductor thin-film of described gate insulation layer 102, and form described semiconductor active layer 103 by a patterning processes.
Wherein, the thickness of described metal oxide semiconductor films is about
the material of described metal oxide semiconductor films can select amorphous IGZO, ITZO, HIZO, IZO, a-InZnO, ZnO:F, In
2o
3: Sn, In
2o
3: Mo, Cd
2snO
4, ZnO:Al, TiO
2: any one in the transparent metal oxide materials such as Nb and Cd-Sn-O.
S 104, as shown in Figure 10 (c), on the substrate being formed with described semiconductor active layer 103, form interlayer insulating film 106 by a patterning processes; Wherein, source contact openings 108 and drain contact hole 109 and gate contact hole 110 is formed in described interlayer insulating film 106.
Concrete, the forming process of described interlayer insulating film 106 can comprise: be about by the disposed thereon thickness of PECVD method at described semiconductor active layer
insulating layer of thin-film, in described insulating layer of thin-film, form source contact openings 108 and drain contact hole 109 and gate contact hole 110 by patterning processes.It should be noted that, when forming described gate contact hole 110 by patterning processes in described insulating layer of thin-film, described gate contact hole 110 is also formed in described gate insulation layer 102 simultaneously.
Wherein, the material of described insulating layer of thin-film can select any one in oxide, nitride and oxynitrides and aluminium oxide, and it can adopt single layer structure, also can adopt sandwich construction.
In this step, the patterning process of described interlayer insulating film 106 can be divided into following two kinds of situations:
The first, adopt intermediate tone mask plate or gray tone mask plate to carry out composition to described insulating layer of thin-film 1060.
Concrete, as shown in Figure 11 (a), the substrate being formed with described semiconductor active layer 103 forms insulating layer of thin-film 1060, and apply photoresist 30 above described insulating layer of thin-film 1060.
As shown in Figure 11 (b), adopt intermediate tone mask plate or gray tone mask plate expose described photoresist 30 and develop, form the complete reserve part 301 of photoresist, photoresist half reserve part 302 and photoresist and remove part (not shown) completely; Wherein, gate contact hole corresponding to part removed completely by described photoresist, the corresponding source contact openings to be formed of described photoresist half reserve part 302 and drain contact hole, the complete reserve part 301 of described photoresist other region corresponding.
By first time etching technics, described photoresist is removed described insulating layer of thin-film corresponding to part (comprising the insulating layer of thin-film of corresponding interlayer insulating film and the insulating layer of thin-film of corresponding gate insulation layer) completely to etch away, to form described gate contact hole (not shown).
As shown in Figure 11 (c), removed the described photoresist 30 of described photoresist half reserve area 302 correspondence by cineration technics.
As shown in Figure 11 (d), by second time etching technics, the described insulating layer of thin-film 1060 exposed is etched away, to form described source contact openings 108 and described drain contact hole 109.
Remaining photoresist is removed finally by stripping technology.
Based on foregoing description, described intermediate tone mask plate operation principle is as follows: by controlling the thickness of the described shading metal level of zones of different on described intermediate tone mask plate, make the intensity through light being exposed on zones of different different, thus after described photoresist is optionally exposed, developing, formed and remove part completely with the complete opaque section of described intermediate tone mask plate, translucent portion, transparent part is corresponding completely the complete reserve part of photoresist, photoresist half reserve part, photoresist respectively.Like this, after first time etches, the film that the complete reserve part of described photoresist and described photoresist half reserve part cover all is retained, after this, photoresist thickness due to the complete reserve part of described photoresist is greater than the photoresist thickness of described photoresist half reserve part, after the photoresist of described photoresist half reserve part is got rid of by ashing process, the photoresist of the complete reserve part of described photoresist still exists, so just, optionally can etch the film of exposed portion, thus obtain at least two-layer different patterned layer.
The principle of described gray tone mask plate and described intermediate tone mask plate is similar, does not repeat them here.
Wherein, in the embodiment of the present invention, the described photoresist of indication is positive photoresist, and namely in described intermediate tone mask plate, region corresponding to part removed completely by described photoresist is complete exposure area, and the material of corresponding described intermediate tone mask plate is light transmissive material; The region that described photoresist half reserve part is corresponding is half exposure area, and the material of corresponding described intermediate tone mask plate is semi transparent material; The region that the complete reserve part of described photoresist is corresponding is not exposure area, and the material of corresponding described intermediate tone mask plate is light-proof material.
The second, adopt common mask plate to carry out composition to described insulating layer of thin-film.
Concrete, the substrate being formed with described semiconductor active layer 103 forms insulating layer of thin-film, and apply photoresist above described insulating layer of thin-film.
Adopt common mask plate expose described photoresist and develop, form photoresist reserve part and photoresist removal part; Wherein, described photoresist removes gate contact hole corresponding to part, source contact openings and drain contact hole, described photoresist reserve part other region corresponding.
The described insulating layer of thin-film (comprising the film of interlayer insulating film and the film of gate insulation layer) described photoresist being removed part corresponding by etching technics etches away; Herein, because the etching selection ratio of the material of described insulating layer of thin-film and the material of described metal-oxide semiconductor (MOS) active layer is very large, therefore directly described gate contact hole, source contact openings and drain contact hole can be formed by dry quarter.
Remaining photoresist is removed finally by stripping technology.
S105, as shown in Figure 10 (d), on the substrate being formed with described interlayer insulating film 106, form source electrode 104 and drain electrode 105 and second grid 107 by patterning processes.
Wherein, described source electrode 104 contacts with described semiconductor active layer 103 with drain contact hole 109 respectively by the source contact openings 108 being arranged in described interlayer insulating film 106 with described drain electrode 105, and described second grid 107 is electrically connected with described first grid 101 by the gate contact hole 110 being arranged in described interlayer insulating film 106 and described gate insulation layer 102.
Here, the forming process of described source electrode 104 and described drain electrode 105 and described second grid 107 specifically can comprise: adopt sputtering method or thermal evaporation at the disposed thereon metal layer thin film of described interlayer insulating film 106, and form described source electrode 104 and described drain electrode 105 by a patterning processes, and described second grid 107.
The thickness of described metal layer thin film is about
it can be single thin film or plural layers; The material of described metal layer thin film can select the metals such as Cr, W, Cu, Ti, Ta, Mo or its alloy.
Based on above-mentioned steps S101-S105, embodiments of the invention can form the thin-film transistor 10 shown in Fig. 1 by four patterning processes.Compared to the thin-film transistor 10 of grid structure single in prior art, the method has prepared the thin-film transistor with double-gate structure under the prerequisite not increasing patterning processes number of times, can improve the grid-control ability of described thin-film transistor 10, and extend its useful life.
Embodiments of the invention also provide a kind of preparation method of array base palte, specifically can comprise the preparation method of above-mentioned thin-film transistor 10, on this basis, described method can also comprise the pixel electrode 20 being formed and be electrically connected with the drain electrode 105 of described thin-film transistor 10.
Wherein, when second grid 107 and the described thin-film transistor 10 of described thin-film transistor 10 source electrode 104 and drain 105 formed by different patterning processes, described second grid 107 and described pixel electrode 20 can pass through a patterning processes and be formed.
Based on this, reoffer the preparation method of specific embodiment to described array base palte below and be described in detail.
The preparation method of described array base palte as shown in figure 12; Wherein, step S201-S203 and step S101-S103 is similar.On this basis, described method comprises further:
S204, as shown in Figure 10 (e), on the substrate being formed with described semiconductor active layer 103, form interlayer insulating film 106 by a patterning processes; Wherein, source contact openings 108 and drain contact hole 109 is formed with in described interlayer insulating film 106.
S205, as shown in Figure 10 (f), on the substrate being formed with described interlayer insulating film 106, form source electrode 104 and drain electrode 105 by patterning processes.
Wherein, described source electrode 104 is contacted with described semiconductor active layer 103 with drain contact hole 109 by the source contact openings 108 be formed in described interlayer insulating film 106 with described drain electrode 105.
S206, as shown in Figure 10 (g), on the substrate being formed with described source electrode 104 and described drain electrode 105, form passivation layer 111 by a patterning processes; Wherein, pixel electrode contact hole 112 and gate contact hole 110 is formed with in described passivation layer 111.
Described pixel electrode contact hole 112 is for realizing the electrical connection between described pixel electrode 20 and described drain electrode 105, and described gate contact hole 110 is for realizing the electrical connection between described second grid 107 and described first grid 101.It should be noted that, described gate contact hole 110 is also formed in described interlayer insulating film 106 and described gate insulation layer 102 simultaneously.
Here, the concrete forming process of described passivation layer 111 can see the concrete forming process of interlayer insulating film 106 described in a upper embodiment, that is, it can adopt common masking process or intermediate tone mask technique, repeats no more here.
S207, as shown in Figure 10 (h), on the substrate being formed with described passivation layer 111, form second grid 107 and pixel electrode 20 by a patterning processes.
Wherein, described pixel electrode 20 is electrically connected with described drain electrode 105 by the pixel electrode contact hole 112 being arranged in described passivation layer 111, and described second grid 107 is electrically connected with described first grid 101 by the gate contact hole 110 being arranged in described passivation layer 111, described interlayer insulating film 106 and described gate insulation layer 102.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.
Claims (16)
1. a thin-film transistor, comprises first grid, is positioned at gate insulation layer above described first grid, is positioned at the semiconductor active layer above described gate insulation layer, the source electrode contacted with described semiconductor active layer and drain electrode; It is characterized in that, also comprise interlayer insulating film and second grid;
Wherein, described interlayer insulating film is arranged between described second grid and described semiconductor active layer.
2. thin-film transistor according to claim 1, is characterized in that, described second grid passes through at least gate contact hole be arranged in described gate insulation layer and described interlayer insulating film and is electrically connected with described first grid.
3. thin-film transistor according to claim 1, is characterized in that, described semiconductor active layer is metal-oxide semiconductor (MOS) active layer.
4. the thin-film transistor according to any one of claims 1 to 3, is characterized in that, described interlayer insulating film is etching barrier layer.
5. thin-film transistor according to claim 1, is characterized in that, described second grid and described source electrode and described drain electrode are arranged with layer.
6. thin-film transistor according to claim 5, is characterized in that, described second grid and described source electrode and described drain electrode are metal electrode.
7. an array base palte, is characterized in that, comprises the thin-film transistor described in any one of claim 1-5.
8. array base palte according to claim 7, is characterized in that, described array base palte also comprises the pixel electrode be electrically connected with the drain electrode of described thin-film transistor;
Wherein, described second grid and described pixel electrode are arranged with layer.
9. a display unit, is characterized in that, comprises the array base palte described in any one of claim 7-8.
10. a preparation method for thin-film transistor, comprising: form first grid, be positioned at gate insulation layer above described first grid, be positioned at the semiconductor active layer above described gate insulation layer, the source electrode contacted with described semiconductor active layer and drain electrode; It is characterized in that, described method also comprises:
Form interlayer insulating film;
And formation second grid;
Wherein, described interlayer insulating film is formed between described second grid and described semiconductor active layer.
11. methods according to claim 10, is characterized in that, described second grid and described source electrode and described drain electrode are formed by a patterning processes.
12. methods according to claim 11, is characterized in that, described method is also included in the step forming gate contact hole in described gate insulation layer and described interlayer insulating film;
Wherein, described second grid is electrically connected with described first grid by described gate contact hole.
13. methods according to claim 12, it is characterized in that, the forming step of described semiconductor active layer specifically comprises: above described gate insulation layer, form metal oxide semiconductor films, and forms metal-oxide semiconductor (MOS) active layer by a patterning processes;
The forming step of described source electrode and described drain electrode and described second grid specifically comprises:
Above described interlayer insulating film, form membrane of conducting layer, with described interlayer insulating film for etching barrier layer, form described source electrode and described drain electrode and described second grid by patterning processes;
Wherein, described second grid is electrically connected with described first grid by described gate contact hole.
14. methods according to claim 13, is characterized in that, describedly above described interlayer insulating film, form membrane of conducting layer be specially:
At the disposed thereon metal layer thin film of described interlayer insulating film.
The preparation method of 15. 1 kinds of array base paltes, is characterized in that, described method comprises the preparation method of the thin-film transistor described in any one of claim 10-13.
16. methods according to claim 15, is characterized in that, described method also comprises the pixel electrode being formed and be electrically connected with the drain electrode of described thin-film transistor;
Wherein, described second grid and described pixel electrode are formed by a patterning processes.
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| CN111710725A (en) * | 2020-06-10 | 2020-09-25 | 深圳市华星光电半导体显示技术有限公司 | Double-gate electrode metal oxide thin film transistor and preparation method thereof |
| CN112071268A (en) * | 2020-08-12 | 2020-12-11 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
| CN112967998A (en) * | 2021-02-03 | 2021-06-15 | 京东方科技集团股份有限公司 | Display substrate, preparation method thereof, display panel and display device |
| CN112967998B (en) * | 2021-02-03 | 2024-03-08 | 京东方科技集团股份有限公司 | Display substrate, preparation method thereof, display panel and display device |
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