CN108987480A - Double gate thin-film transistor and preparation method thereof, display panel and preparation method thereof - Google Patents
Double gate thin-film transistor and preparation method thereof, display panel and preparation method thereof Download PDFInfo
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- CN108987480A CN108987480A CN201710407375.3A CN201710407375A CN108987480A CN 108987480 A CN108987480 A CN 108987480A CN 201710407375 A CN201710407375 A CN 201710407375A CN 108987480 A CN108987480 A CN 108987480A
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- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 title claims abstract description 55
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- 229910052697 platinum Inorganic materials 0.000 description 6
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- ZKATWMILCYLAPD-UHFFFAOYSA-N niobium pentoxide Inorganic materials O=[Nb](=O)O[Nb](=O)=O ZKATWMILCYLAPD-UHFFFAOYSA-N 0.000 description 2
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- SMZOUWXMTYCWNB-UHFFFAOYSA-N 2-(2-methoxy-5-methylphenyl)ethanamine Chemical compound COC1=CC=C(C)C=C1CCN SMZOUWXMTYCWNB-UHFFFAOYSA-N 0.000 description 1
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- 239000004695 Polyether sulfone Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910003107 Zn2SnO4 Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
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- 229910052733 gallium Inorganic materials 0.000 description 1
- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- NJWNEWQMQCGRDO-UHFFFAOYSA-N indium zinc Chemical compound [Zn].[In] NJWNEWQMQCGRDO-UHFFFAOYSA-N 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
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- 229910010272 inorganic material Inorganic materials 0.000 description 1
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- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- 239000002210 silicon-based material Substances 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
- H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/78654—Monocrystalline silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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Abstract
The embodiment of the invention discloses a kind of double gate thin-film transistors and preparation method thereof, display panel and preparation method thereof, wherein, the double gate thin-film transistor includes substrate, first gate electrode on substrate, the first gate insulation layer in first gate electrode, active layer on the first gate insulation layer, the second gate insulation layer on active layer, the second gate electrode on the second gate insulation layer, interlayer insulating film on the second gate electrode, source electrode and drain electrode on interlayer insulating film, source electrode and drain electrode is electrically connected by the opening on interlayer insulating film and the second gate insulation layer with active layer.By adopting the above technical scheme, by inputting bias voltage signal to first gate electrode, the threshold voltage of thin film transistor (TFT) is adjusted, threshold voltage is avoided polarization or partially negative situation occur.
Description
Technical field
The present embodiments relate to technical field of semiconductors more particularly to a kind of double gate thin-film transistor and its preparation sides
Method, display panel and preparation method thereof.
Background technique
Organic light emitting diode (Organic Light-Emitting Diode, OLED) have small in size, structure it is simple,
From main light emission, brightness is high, image quality is good, visible angle is big, the low in energy consumption and response time is short the advantages that, thus cause to close extensively
Note most probably becomes the next-generation display technology for replacing liquid crystal.
In the prior art, two transistors T1 and T2 are generallyd use, the pixel-driving circuit of the 2T1C of a capacitor C is used to
OLED is driven, as shown in Figure 1.But since the threshold voltage of transistor T2 can drift about with the working time, cause the threshold of T2
Threshold voltage is born partially or polarization；And since processing procedure, material property or other reasons are also possible to cause the threshold voltage of T2 inclined
Negative or polarization (not near 0V), will increase the charging power consumption of capacitor C, and cause shining for OLED unstable.
Summary of the invention
In view of this, the embodiment of the present invention provide a kind of double gate thin-film transistor and preparation method thereof, display panel and its
Preparation method, it is because of threshold voltage polarization or partially negative in existing OLED display technology to solve, increase the skill of capacitor charging power consumption
Art problem.
In a first aspect, the embodiment of the invention provides a kind of double gate thin-film transistors, comprising:
Substrate；
First gate electrode on the substrate；
The first gate insulation layer in the first gate electrode, first gate insulation layer cover the first gate electrode
With the substrate；
Active layer on first gate insulation layer, the upright projection of the active layer on the substrate with it is described
There are overlapping regions for the upright projection of first gate electrode on the substrate；
The second gate insulation layer on the active layer, second gate insulation layer cover the active layer and described the
One gate insulation layer；
The second gate electrode on second gate insulation layer, the vertical throwing of second gate electrode on the substrate
There are overlapping regions with the upright projection of the active layer on the substrate for shadow；
Interlayer insulating film on second gate electrode, the interlayer insulating film cover second gate electrode and institute
State the second gate insulation layer；
Source electrode and drain electrode on the interlayer insulating film, the source electrode and the drain electrode pass through the layer
Between opening on insulating layer and second gate insulation layer be electrically connected with the active layer.
Second aspect, the embodiment of the invention also provides a kind of display panels, including double grid described in above-mentioned first aspect
Thin film transistor (TFT), further includes:
Capacitance structure, the capacitance structure include the first electrode on the substrate and are located at second gate insulation
Second electrode on layer, the upright projection of the first electrode on the substrate and the second electrode are on the substrate
There are overlapping regions for upright projection, wherein the first electrode of the capacitance structure and the first gate electrode same layer are arranged, described
The second electrode of capacitance structure and the second gate electrode same layer are arranged.
The third aspect, the embodiment of the invention also provides a kind of preparation methods of double gate thin-film transistor, comprising:
One substrate is provided, and prepares first gate electrode on the substrate；
The first gate insulation layer is prepared in the first gate electrode, first gate insulation layer covers the first gate electrode
With the substrate；
Prepare active layer on first gate insulation layer, the upright projection of the active layer on the substrate with it is described
There are overlapping regions for the upright projection of first gate electrode on the substrate；
Prepare the second gate insulation layer on the active layer, second gate insulation layer covers the active layer and described the
One gate insulation layer；
The second gate electrode, the vertical throwing of second gate electrode on the substrate are prepared on second gate insulation layer
There are overlapping regions with the upright projection of the active layer on the substrate for shadow；
Interlayer insulating film is prepared on second gate electrode, the interlayer insulating film covers second gate electrode and institute
State the second gate insulation layer；
Source electrode and drain electrode is prepared on the interlayer insulating film, the source electrode and the drain electrode pass through the layer
Between opening on insulating layer and second gate insulation layer be electrically connected with the active layer.
Fourth aspect, the embodiment of the invention also provides a kind of preparation methods of display panel, comprising:
One substrate is provided, and prepare on the substrate double gate thin-film transistor first gate electrode and capacitance structure
One electrode, the first gate electrode are formed with the same procedure of the first electrode；
The first gate insulation layer, the first gate insulation layer covering are prepared in the first gate electrode and the first electrode
The first gate electrode, first electrode and the substrate；
The active layer of the double gate thin-film transistor is prepared on first gate insulation layer, the active layer is in the base
There are overlapping regions with the upright projection of the first gate electrode on the substrate for upright projection on plate；
Prepare the second gate insulation layer on the active layer, second gate insulation layer covers the active layer and described the
One gate insulation layer；
The second gate electrode and the capacitance structure of the double gate thin-film transistor are prepared on second gate insulation layer
Second electrode, second gate electrode formed with the same procedure of the second electrode, and second gate electrode is in the base
There are overlapping regions with the upright projection of the active layer on the substrate for upright projection on plate；
Interlayer insulating film is prepared on second gate electrode and the second electrode, described in the interlayer insulating film covering
Second gate electrode, second electrode and second gate insulation layer；
Source electrode and drain electrode is prepared on the interlayer insulating film, the source electrode and the drain electrode pass through the layer
Between opening on insulating layer and second gate insulation layer be electrically connected with the active layer.
Double gate thin-film transistor provided in an embodiment of the present invention and preparation method thereof, display panel and preparation method thereof, it is double
Gate thin-film transistors include first gate electrode, the second gate electrode, active layer, source electrode and drain electrode source electrode and drain electrode, by first gate electrode
Bias voltage signal is inputted, the threshold voltage of thin film transistor (TFT) is adjusted, avoids threshold voltage from polarization or partially negative situation occur, guarantees
Threshold voltage reduces the charging power consumption of capacitor closer to 0V, guarantees OLED normal luminous.
Detailed description of the invention
In order to more clearly illustrate the technical scheme of the exemplary embodiment of the present invention, below to required in description embodiment
The attached drawing to be used does a simple introduction.Obviously, the attached drawing introduced is present invention a part of the embodiment to be described
Attached drawing, rather than whole attached drawings without creative efforts, may be used also for those of ordinary skill in the art
To obtain other attached drawings according to these attached drawings.
Fig. 1 is the driving circuit figure of OLED a kind of；
Fig. 2 is a kind of structural schematic diagram for double gate thin-film transistor that inventive embodiments provide；
Fig. 3 is the structural schematic diagram of another double gate thin-film transistor provided in an embodiment of the present invention；
Fig. 4 is a kind of structural schematic diagram of display panel provided in an embodiment of the present invention；
Fig. 5 is the structural schematic diagram of another display panel provided in an embodiment of the present invention；
Fig. 6 is a kind of flow diagram of the preparation method of double gate thin-film transistor provided in an embodiment of the present invention；
Fig. 7 is a kind of flow diagram of the preparation method of display panel provided in an embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below with reference to attached in the embodiment of the present invention
Figure, by specific embodiment, is fully described by technical solution of the present invention.Obviously, described embodiment is of the invention
A part of the embodiment, instead of all the embodiments, based on the embodiment of the present invention, those of ordinary skill in the art are not doing
The every other embodiment obtained under the premise of creative work out, falls within the scope of protection of the present invention.
Fig. 2 is a kind of structural schematic diagram for double gate thin-film transistor that inventive embodiments provide, referring to FIG. 2, of the invention
Embodiment provide double gate thin-film transistor may include:
Substrate 101；
First gate electrode 102 on substrate 101；
The first gate insulation layer 103 in first gate electrode 102, the first gate insulation layer 103 cover first gate electrode 102
With substrate 101；
Active layer 104 on the first gate insulation layer 103, the upright projection of active layer 104 on the substrate 101 and first
The upright projection of gate electrode 102 on the substrate 101；
The second gate insulation layer 105 on active layer 104, the second gate insulation layer 105 cover active layer 104 and the first grid
Insulating layer 103；
The second gate electrode 106 on the second gate insulation layer 105, the vertical throwing of the second gate electrode 106 on the substrate 101
There are overlapping regions with the upright projection of active layer 104 on the substrate 101 for shadow；
Interlayer insulating film 107 on the second gate electrode 106, interlayer insulating film 107 cover the second gate electrode 106 and the
Two gate insulation layers 105；
Source electrode 108 and drain electrode 109 on interlayer insulating film 107, source electrode 108 and drain electrode 109 pass through layer
Between opening on insulating layer 107 and the second gate insulation layer 105 be electrically connected with active layer 104.
Illustratively, substrate 101 can be flexible base board, and material may include polyimides, poly terephthalic acid second
At least one of diol ester, polyethylene naphthalate, polycarbonate, polyarylate and polyether sulfone；Substrate 101 can be with
For rigid substrates, it is specifically as follows glass substrate or other rigid substrates.The embodiment of the present invention not to the type of substrate and
Material is defined.
First gate electrode 102 is located on substrate 101, the material of first gate electrode 102 may include Au, Ag, Cu, Ni, Pt,
At least one of Pd, Al, Mo, W and Ti, or can use the metal alloy shape of Al-Nd alloy and Mo-W alloy etc.
At, but not limited to this.In fact, first gate electrode 102 can consider such as with the adhesiveness of adjacent layer, planarization, resistance
Or it can be formed using a variety of materials, the embodiment of the present invention is to first gate electrode 102 in the case where the properties such as formative or characteristic
Material is without limiting.
First gate insulation layer 103 is located at the side in first gate electrode 102 far from substrate 101, and the first gate insulation layer 103 covers
Lid first gate electrode 102 and substrate 101.Optionally, the material of the first gate insulation layer 103 can be silica, silicon nitride, oxidation
At least one of inorganic insulating materials such as aluminium or hafnium oxide, for example, the first gate insulation layer 103 can be to be made of silicon nitride
Single layer structure, be made of silica single layer structure, can also be for by silicon nitride layer, silicon oxide layer, aluminium oxide or oxidation
The multilayered structure of the compositions such as hafnium.
Active layer 104 is located at the side on the first gate insulation layer 103 far from first gate electrode 102, and active layer 104 is in substrate
Upright projection and the upright projection of first gate electrode 102 on the substrate 101 on 101.Optionally, the material of active layer 104 can
Think that at least one of monocrystalline silicon, polysilicon and oxide semiconductor material, the oxide semiconductor material may include
ZnO、SnO2、In2O3、Zn2SnO4、Ga2O3And/or HfO2At least one of.Moreover, active layer 104 can use transparent Indium
Object semiconductor is formed.For example, transparent oxide semiconductor may include zinc oxide, tin oxide, oxidation gallium indium zinc, indium zinc oxide
And/or tin indium oxide, but not limited to this.
Second gate insulation layer 105 is located at the side on active layer 104 far from the first gate insulation layer 103, the second gate insulation layer
105 covering active layers 104 and the first gate insulation layer 103.Optionally, the material of the second gate insulation layer 105 can be exhausted with the first grid
The material of edge layer 103 is identical, for example, can be silica or silicon nitride.
Second gate electrode 106 is located at the side on the second gate insulation layer 105 far from active layer 104, and the second gate electrode 106 exists
There are overlapping regions with the upright projection of active layer 104 on the substrate 101 for upright projection on substrate 101.Optionally, second gate
The material of electrode 106 can be identical with the material of first gate electrode 102, for example including Au, Ag, Cu, Ni, Pt, Pd, Al, Mo, W
At least one of with Ti, or it can use the metal alloy of Al-Nd alloy and Mo-W alloy etc. and formed.
Interlayer insulating film 107 is located at the side on the second gate electrode 106 far from the second gate insulation layer 105, interlayer insulating film
107 the second gate electrodes 106 of covering and the second gate insulation layer 105.Optionally, the material of interlayer insulating film can use including oxidation
The insulating materials of silicon or silicon nitride is formed, or be can use insulating organic material and formed.
Source electrode 108 and drain electrode 109 are located at the side on interlayer insulating film 107 far from the second gate electrode 106, source electrode
108 and drain electrode 109 be electrically connected by the opening on interlayer insulating film 107 and the second gate insulation layer 105 with active layer 104.It can
Choosing, source electrode 108 is also electrically connected (not shown) with data line.Optionally, the material of source electrode 108 and drain electrode 109
Can be conductive material, such as can be Cr, Pt, Ru, Au, Ag, Mo, Al, W, Cu and/or AlNd metal, or including ITO,
The metal or conductive oxide of GIZO, GZO, IZO (InZnO) or AZO (AlZnO).
Optionally, it when above-mentioned double gate thin-film transistor works, by inputting bias voltage signal to first gate electrode 102, adjusts
The threshold voltage for saving thin film transistor (TFT) avoids threshold voltage from polarization or partially negative situation occur, guarantees that threshold voltage is closer
0V.For example, by the bias negative to the input of first gate electrode 102, making threshold when thin film transistor (TFT) has the threshold voltage of negative value
Threshold voltage is mobile toward positive direction, guarantees threshold voltage closer to 0V；Alternatively, when thin film transistor (TFT) has the threshold voltage of positive value
When, by inputting positive bias to first gate electrode 102, keeps threshold voltage mobile toward negative direction, guarantee that threshold voltage is closer
0V。
To sum up, double gate thin-film transistor provided in an embodiment of the present invention, double gate thin-film transistor include first gate electrode,
Two gate electrode, active layer, source electrode and drain electrode adjust thin film transistor (TFT) by inputting bias voltage signal to first gate electrode
Threshold voltage avoids threshold voltage from polarization or partially negative situation occur, guarantees that threshold voltage closer to 0V, reduces filling for capacitor
Electrical power consumed guarantees OLED normal luminous.With in existing structure using the cathode electrode in display panel as double gate thin-film transistor
The structure of top-gated electrode compare, the structure of double gate thin-film transistor provided in an embodiment of the present invention is simple, is forming second gate
Opening is not necessarily formed when electrode (top-gated electrode), preparation process is simple, while guaranteeing that the aperture opening ratio of display panel is larger.
Referring to FIG. 3, Fig. 3 is the structural schematic diagram of another double gate thin-film transistor provided in an embodiment of the present invention, tool
Body, buffer layer is increased on the basis of the double gate thin-film transistor shown in Fig. 2 of double gate thin-film transistor described in Fig. 3, such as
Shown in Fig. 3, double gate thin-film transistor may include:
Substrate 101；
Buffer layer 110 on substrate 101；
First gate electrode 102 on buffer layer 110；
The first gate insulation layer 103 in first gate electrode 102, the first gate insulation layer 103 cover first gate electrode 102
With substrate 101；
Active layer 104 on the first gate insulation layer 103, the upright projection of active layer 104 on the substrate 101 and first
There are overlapping regions for the upright projection of gate electrode 102 on the substrate 101；
The second gate insulation layer 105 on active layer 104, the second gate insulation layer 105 cover active layer 104 and the first grid
Insulating layer 103；
The second gate electrode 106 on the second gate insulation layer 105, the vertical throwing of the second gate electrode 106 on the substrate 101
There are overlapping regions with the upright projection of active layer 104 on the substrate 101 for shadow；
Interlayer insulating film 107 on the second gate electrode 106, interlayer insulating film 107 cover the second gate electrode 106 and the
Two gate insulation layers 105；
Source electrode 108 and drain electrode 109 on interlayer insulating film 107, source electrode 108 and drain electrode 109 pass through layer
Between opening on insulating layer 107 and the second gate insulation layer 105 be electrically connected with active layer 104.
Illustratively, buffer layer 110 is located on substrate 101, and material may include silica and/or silicon nitride.Pass through
Buffer layer 110 is formed on the substrate 101, and the impurity that can prevent or reduce substrate 101 penetrates into the film for being arranged in 101 top of substrate
In layer structure, that is, the impurity for preventing or reducing substrate 101 penetrates into the first gate electrode 102 for being arranged in 101 top of substrate.
Referring to FIG. 4, Fig. 4 is a kind of structural schematic diagram of display panel provided in an embodiment of the present invention, specifically, Fig. 4
Shown in increase capacitance structure on the basis of display panel double gate thin-film transistor shown in Fig. 2, as shown in figure 4, display
Panel may include:
Substrate 101；
The first electrode 201 of first gate electrode 102 and capacitance structure 20 on substrate 101, first gate electrode 102 with
The setting of 201 same layer of first electrode；
The first gate insulation layer 103 in first gate electrode 102 and first electrode 201, the covering of the first gate insulation layer 103
First gate electrode 102, first electrode 201 and substrate 101；
Active layer 104 on the first gate insulation layer 103, the upright projection of active layer 104 on the substrate 101 and first
There are overlapping regions for the upright projection of gate electrode 102 on the substrate 101；
The second gate insulation layer 105 on active layer 104, the second gate insulation layer 105 cover active layer 104 and the first grid
Insulating layer 103；
The second electrode 202 of the second gate electrode 106 and capacitance structure 20 on the second gate insulation layer 105, second gate
Electrode 106 and the setting of 202 same layer of second electrode, the upright projection of the second gate electrode 106 on the substrate 101 and active layer 104 exist
There are overlapping region, the upright projection of first electrode 201 on the substrate 101 and second electrodes 202 for upright projection on substrate 101
There are overlapping regions for upright projection on the substrate 101；
Interlayer insulating film 107 on the second gate electrode 106 and second electrode 202, the covering of interlayer insulating film 107 second
Gate electrode 106, second electrode 202 and the second gate insulation layer 105；
Source electrode 108 and drain electrode 109 on interlayer insulating film 107, source electrode 108 and drain electrode 109 pass through layer
Between opening on insulating layer 107 and the second gate insulation layer 105 be electrically connected with active layer 104.
Illustratively, the first electrode 201 of capacitance structure 20 upright projection on the substrate 101 and second electrode 202 exist
For upright projection on substrate 101 there are overlapping region, first electrode 201 is identical with the material of second electrode 202, can be to lead
Electric material, for example, can be Cr, Pt, Ru, Au, Ag, Mo, Al, W, Cu and/or AlNd metal, or including ITO, GIZO, GZO,
The metal or conductive oxide of IZO (InZnO) or AZO (AlZnO).Optionally, the of first gate electrode 102 and capacitance structure 20
One electrode 201 is arranged simultaneously, can prepare simultaneously during the preparation process；Second electricity of the second gate electrode 106 and capacitance structure 20
The setting of 202 same layer of pole, can prepare simultaneously during the preparation process.
To sum up, display panel provided in an embodiment of the present invention, including the crystalline substance of double grid film described in any embodiment of that present invention
Body pipe further includes capacitance structure, and the first electrode of capacitance structure and the first electrode same layer of double gate thin-film transistor are arranged, capacitor
The second electrode of structure and the second electrode same layer of double gate thin-film transistor are arranged, not only the threshold value of adjustable thin film transistor (TFT)
Voltage avoids threshold voltage from polarization or partially negative situation occur, guarantees that threshold voltage closer to 0V, reduces the charging function of capacitor
Consumption guarantees OLED normal luminous；And display panel structure is simple.
Referring to FIG. 5, Fig. 5 is the structural schematic diagram of another display panel provided in an embodiment of the present invention, specifically, figure
Display function layer is increased on the basis of the display panel shown in Fig. 4 of display panel shown in 5, as shown in figure 5, display panel
May include:
Substrate 101；
The first electrode 201 of first gate electrode 102 and capacitance structure 20 on substrate 101, first gate electrode 102 with
The setting of 201 same layer of first electrode；
The first gate insulation layer 103 in first gate electrode 102 and first electrode 201, the covering of the first gate insulation layer 103
First gate electrode 102, first electrode 201 and substrate 101；
Active layer 104 on the first gate insulation layer 103, the upright projection of active layer 104 on the substrate 101 and first
There are overlapping regions for the upright projection of gate electrode 102 on the substrate 101；
The second gate insulation layer 105 on active layer 104, the second gate insulation layer 105 cover active layer 104 and the first grid
Insulating layer 103；
The second electrode 202 of the second gate electrode 106 and capacitance structure 20 on the second gate insulation layer 105, second gate
Electrode 106 and the setting of 202 same layer of second electrode, the upright projection of the second gate electrode 106 on the substrate 101 and active layer 104 exist
There are overlapping region, the upright projection of first electrode 201 on the substrate 101 and second electrodes 202 for upright projection on substrate 101
There are overlapping regions for upright projection on the substrate 101；
Interlayer insulating film 107 on the second gate electrode 106 and second electrode 202, the covering of interlayer insulating film 107 second
Gate electrode 106, second electrode 202 and the second gate insulation layer 105；
Source electrode 108 and drain electrode 109 on interlayer insulating film 107, source electrode 108 and drain electrode 109 pass through layer
Between opening on insulating layer 107 and the second gate insulation layer 105 be electrically connected with active layer 104；
Passivation layer 111 in source electrode 108 and drain electrode 109, passivation layer 111 cover source electrode 108 and electric leakage
Pole 109；
Planarization layer 112 on passivation layer 111；
Anode electrode layer 113 in planarization 112, anode electrode layer 113 pass through planarization layer 112 and passivation layer
Opening on 111 is electrically connected with drain electrode 109；
Pixel defining layer 114 on anode electrode layer 113；
Supporting layer 115 in pixel defining layer 114；
Organic luminous layer 116 on anode electrode 113 and between two neighboring pixel defining layer 114；
Negative electrode layer 117 on organic luminous layer 116 and pixel defining layer 114.
Illustratively, passivation layer 111 is located at one far from interlayer insulating film 107 on source electrode 108 and drain electrode 109
Side, passivation layer 111 cover source electrode 108 and drain electrode 109, and passivation layer 111 is positioned below or the double grid of lower section for protecting
Thin film transistor (TFT).Optionally, the material of passivation layer 111 can be silica or silicon nitride.
Planarization layer 112 is located on passivation layer 111 side far from source electrode 108 or drain electrode 109, planarization layer
112 for protecting and planarizing in its lower section or the passivation layer 111 of lower section.Planarization layer 112 can be by utilizing various methods
One of formed, and can use the organic material including benzocyclobutene or acrylic acid or the inorganic material including silicon nitride
It is formed, moreover, planarization layer 112 can be formed as single layer, bilayer or multilayer.
Anode electrode layer 113 is located at the side on planarization layer 112 far from passivation layer 111, and anode electrode layer 113 passes through flat
Opening on smoothization layer 112 and passivation layer 111 is electrically connected with drain electrode 109.Optionally, the material of anode electrode layer 113 can be with
For at least one of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li and Ca.
Pixel defining layer 114 is located at the side on anode electrode layer 113 far from planarization layer 112, and pixel defining layer 114 can
To prevent or reduce the color mixing between pixel.Optionally, the material of pixel defining layer 114 may include polyimides, polyamides
Amine, acrylic resin and at least one of organic insulating materials such as cyclobutane and phenolic resin；Pixel defining layer 114 may be used also
To include SiO2、SiNx、Al2O3、CuOx、Tb4O7、Y2O3、Nb2O5And Pr2O3At least one of equal inorganic insulating materials；And
And the multilayered structure that pixel defining layer 114 can also have organic insulating material and inorganic insulating material to be alternatively formed.
Supporting layer 115 is located at the side in pixel defining layer 114 far from anode electrode layer 113, and supporting layer 115 is used to support
The film layer in face or top disposed thereon.Optionally, the material of supporting layer 115 can be identical with the material of pixel defining layer 114,
Such as may include polyimides, polyamide, acrylic resin, and the organic insulating materials such as cyclobutane and phenolic resin in extremely
Few one kind；It can also include SiO2、SiNx、Al2O3、CuOx、Tb4O7、Y2O3、Nb2O5And Pr2O3In equal inorganic insulating materials extremely
Few one kind.
Organic luminous layer 116 is located on anode electrode 113 and between two neighboring pixel defining layer 114, You Jifa
Photosphere 116 may include the hole injection layer sequentially stacked, hole transmission layer, emission layer, electron transfer layer and electron injecting layer.
Optionally, organic luminous layer 116 can use low molecule or macromolecule organic material is formed.
Negative electrode layer 117 is located at the side in organic luminous layer 116 and pixel defining layer 114 far from anode electrode 113,
The material of anode electrode layer 117 can be at least one of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li and Ca.
To sum up, display panel provided in an embodiment of the present invention, including double gate thin-film transistor and capacitance structure and position
Various display function layers above double gate thin-film transistor and capacitance structure, a gate electrode of double gate thin-film transistor and source
Electrode and drain electrode are collectively as the switching element of circuit, another gate electrode of double gate thin-film transistor is by being applied partially
Pressure, adjusts the threshold voltage of thin film transistor (TFT), avoids threshold voltage from polarization or partially negative situation occur, guarantees threshold voltage more
Close to 0V, the charging power consumption of capacitor is reduced, guarantees OLED normal luminous.Anode electrode layer is located at as an individual electrode
The top layer of entire display panel, with the gate electrode that anode electrode layer is multiplexed with to double gate thin-film transistor in the prior art
Scheme compare, display panel provided in an embodiment of the present invention can guarantee the image quality of display panel, avoid by anode electricity
Pole layer is multiplexed with gate electrode and is biased the case where may interfering to display, and without in film layers such as pixel defining layers
Structure split shed saves the process flows such as preparation opening, and process is simple, and anode electrode layer is individually electric as one
Pole, it can also be ensured that the biggish aperture opening ratio of display panel.
Referring to FIG. 6, the process that Fig. 6 is a kind of preparation method of double gate thin-film transistor provided in an embodiment of the present invention is shown
It is intended to, as shown in fig. 6, the preparation method of double gate thin-film transistor may include:
S110, a substrate is provided, and prepares first gate electrode on the substrate.
Illustratively, first gate electrode is prepared on substrate can be one layer of first gate electrode material of deposition on substrate,
And patterned process is carried out to the gate material of flood, obtain first gate electrode.
S120, the first gate insulation layer, the first gate insulation layer covering described first are prepared in the first gate electrode
Gate electrode and the substrate.
The first gate insulation layer is prepared in first gate electrode, be can be and is deposited gate insulator layer material in first gate electrode,
The first gate insulation layer is obtained, the first gate insulation layer covers first gate electrode and substrate.
S130, active layer, the upright projection of the active layer on the substrate are prepared on first gate insulation layer
There are overlapping regions with the upright projection of the first gate electrode on the substrate.
Active layer is prepared on the first gate insulation layer, can be and deposit active layer material on the first gate insulation layer, and is right
Active layer material carries out patterned process, obtains active layer, active layer is corresponding with first gate electrode.Optionally, the active layer
Material can be at least one of for monocrystalline silicon, polysilicon and oxide semiconductor material.Optionally, the polysilicon can be with
By the method for low pressure chemical vapor phase deposition (Low Pressure Chemical Vapor Deposition, LPCVD) or
The method that amorphous silicon is converted to polysilicon is obtained by laser melting technology.
S140, prepare the second gate insulation layer on the active layer, second gate insulation layer cover the active layer and
First gate insulation layer.
The second gate insulation layer is prepared on active layer, can be and deposit gate insulator layer material on active layer, obtains second
Gate insulation layer, the second gate insulation layer are covered with active layer and the first gate insulation layer.
S150, the second gate electrode is prepared on second gate insulation layer, second gate electrode is on the substrate
There are overlapping regions with the upright projection of the active layer on the substrate for upright projection.
The second gate electrode is prepared on the second gate insulation layer can be one layer of gate electrode material of deposition on the second gate insulation layer
Material, and patterned process is carried out to the gate material of flood, the second gate electrode is obtained, the second gate electrode is vertical on substrate
There are overlapping regions for the upright projection of projection and active layer on substrate.
S160, interlayer insulating film is prepared on second gate electrode, the interlayer insulating film covers the second gate electricity
Pole and second gate insulation layer.
Interlayer insulating film is prepared on the second gate electrode, the depositing insulating layer material on the second gate electrode is can be, obtains
Interlayer insulating film, interlayer insulating film cover the second gate electrode and the second gate insulation layer.
S170, source electrode and drain electrode is prepared on the interlayer insulating film, the source electrode and the drain electrode pass through
Opening on the interlayer insulating film and second gate insulation layer is electrically connected with the active layer.
It is prepared after interlayer insulating film, in the position of corresponding source electrode and drain electrode, to interlayer insulating film and second
Gate insulation layer carries out opening processing, later, source electrode and drain electrode is prepared on interlayer insulating film, source electrode and drain electrode passes through
Opening on interlayer insulating film and the second gate insulation layer is electrically connected with active layer.Optionally, when the material of active layer is monocrystalline silicon
Or when polycrystalline silicon material, ion note can be carried out to the contact zone of active layer before the second gate insulation layer is prepared on active layer
Enter, to reduce source electrode.The contact resistance of drain electrode and active layer.
Optionally, the preparation method of the double gate thin-film transistor can be with before preparing first gate electrode on substrate
Include:
Buffer layer is prepared on substrate.
Illustratively, buffer layer is prepared on substrate and can be prepared by the method for the buffer layer material on substrate delays
Layer is rushed, the material of the buffer layer may include silica and/or silicon nitride.
To sum up, the preparation method of double gate thin-film transistor provided in an embodiment of the present invention, by preparing first grid electricity respectively
Pole, the second gate electrode, active layer, source electrode and drain electrode source electrode and drain electrode, the second gate electrode and source electrode and drain electrode are collectively as circuit
Switching element, first gate electrode adjust the threshold voltage of thin film transistor (TFT), avoid threshold voltage from occurring inclined by being applied bias
Just or partially negative situation guarantees that threshold voltage closer to 0V, reduces the charging power consumption of capacitor, guarantees OLED normal luminous；And
And the preparation method simple process of above-mentioned double gate thin-film transistor.
Referring to FIG. 7, Fig. 7 is a kind of flow diagram of the preparation method of display panel provided in an embodiment of the present invention,
Shown in Fig. 7, the preparation method of display panel may include:
S210, a substrate is provided, and prepares the first gate electrode and capacitive junctions of double gate thin-film transistor on the substrate
The first electrode of structure, the first gate electrode are formed with the same procedure of the first electrode.
Illustratively, the material of the first electrode of the first gate electrode and capacitance structure of double gate thin-film transistor can phase
Together, it and can be formed in a procedure, specifically can be the gate material for depositing flood on substrate, pass through patterning
The first electrode of first gate electrode and capacitance structure is obtained after processing.
S220, the first gate insulation layer, first gate insulation are prepared in the first gate electrode and the first electrode
Layer covers the first gate electrode, first electrode and the substrate.
Gate insulator layer material is deposited in first gate electrode and first electrode, obtains the first gate insulation layer, the first gate insulation
Layer covering first gate electrode, first electrode and substrate.
S230, the active layer that the double gate thin-film transistor is prepared on first gate insulation layer, the active layer exist
There are Chong Die for the upright projection of upright projection on the substrate and the first gate electrode on the substrate.
S240, prepare the second gate insulation layer on the active layer, second gate insulation layer cover the active layer and
First gate insulation layer.
S250, the second gate electrode and the capacitor that the double gate thin-film transistor is prepared on second gate insulation layer
The second electrode of structure, second gate electrode are formed with the same procedure of the second electrode, and second gate electrode is in institute
There are overlapping region, the first electrodes with the upright projection of the active layer on the substrate for the upright projection for stating on substrate
There are overlapping regions with the upright projection of the second electrode on the substrate for upright projection on the substrate.
Illustratively, on the second gate electrode prepare double gate thin-film transistor the second gate electrode and capacitance structure second
The material of electrode, the second gate electrode and second electrode can be identical, and can be formed in same procedure, specifically can be
The gate material that flood is deposited on second gate insulation layer, by obtaining the second gate electrode and capacitance structure after patterned process
Second electrode, upright projection and active layer upright projection on substrate of second gate electrode on substrate there are overlapping region,
There are overlapping regions for upright projection and second electrode upright projection on substrate of the first electrode on substrate.
S260, interlayer insulating film is prepared on second gate electrode and the second electrode, the interlayer insulating film covers
Cover second gate electrode, second electrode and second gate insulation layer.
The depositing insulating layer material on the second gate electrode and second electrode obtains interlayer insulating film, interlayer insulating film covering
Second gate electrode, second electrode and the second gate insulation layer.
S270, source electrode and drain electrode is prepared on the interlayer insulating film, the source electrode and the drain electrode pass through
Opening on the interlayer insulating film and second gate insulation layer is electrically connected with the active layer.
To sum up, the preparation method of display panel provided in an embodiment of the present invention, the first gate electrode of double grid film crystal and
The first electrode of capacitance structure is formed in same procedure, and the second of the second grid of double gate thin-film transistor and capacitance structure
Electrode is formed in same procedure, and preparation process is simple, is not necessarily to additional masks process, is saved the preparation time of display panel,
Promote the preparation efficiency of display panel.
Optionally, the preparation method of the display panel can also include other film layer structures for preparing display panel, example
Such as each display function layer, as passivation layer, planarization layer, anode electrode layer, pixel defining layer, supporting layer, organic luminous layer with
And negative electrode layer etc..Optionally, the preparation method of display panel can also include:
Passivation layer is prepared on the source and drain electrodes, and passivation layer covers source electrode and drain electrode；
Planarization layer is prepared on the passivation layer；
Anode electrode layer is prepared on planarization layer, anode electrode layer passes through opening and institute on planarization layer and passivation layer
State drain electrode electrical connection；
Pixel defining layer is prepared on anode electrode layer；
Supporting layer is prepared in pixel defining layer；
On the anode electrode, and between two neighboring pixel defining layer organic luminous layer is prepared；
Negative electrode layer is prepared on machine luminescent layer and pixel defining layer.
The preparation of above-mentioned display function layer can be prepared using preparation method in the prior art, no longer superfluous here
It states.
It should be noted that the preparation method of display panel provided in an embodiment of the present invention, lunar calendar electrode layer is as independent
Display film layer, be not multiplexed with the top-gated electrode of double gate thin-film transistor, lunar calendar electrode layer is complete flood structure, and existing
The method that negative electrode layer is multiplexed with top-gated electrode is compared in technology, without by being prepared on the film layer structures such as planarization layer
Opening, reduces mask process, preparation method is simple and efficient.Also, negative electrode layer makees subject display film layer, Ke Yibao
The image quality of display panel is demonstrate,proved, and guarantees the biggish aperture opening ratio of display panel.
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that
The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above embodiments to the present invention
It is described in further detail, but the present invention is not limited to the above embodiments only, without departing from the inventive concept, also
It may include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.
Claims (10)
1. a kind of double gate thin-film transistor characterized by comprising
Substrate；
First gate electrode on the substrate；
The first gate insulation layer in the first gate electrode, first gate insulation layer cover the first gate electrode and institute
State substrate；
Active layer on first gate insulation layer, the upright projection of the active layer on the substrate and described first
There are overlapping regions for the upright projection of gate electrode on the substrate；The second gate insulation layer on the active layer, it is described
Second gate insulation layer covers the active layer and first gate insulation layer；
The second gate electrode on second gate insulation layer, the upright projection of second gate electrode on the substrate with
There are overlapping regions for the upright projection of the active layer on the substrate；
Interlayer insulating film on second gate electrode, the interlayer insulating film cover second gate electrode and described the
Two gate insulation layers；
Source electrode and drain electrode on the interlayer insulating film, the source electrode and the drain electrode are exhausted by the interlayer
Opening in edge layer and second gate insulation layer is electrically connected with the active layer.
2. double gate thin-film transistor according to claim 1, which is characterized in that the material of the active layer be monocrystalline silicon,
At least one of polysilicon and oxide semiconductor material.
3. double gate thin-film transistor according to claim 1, which is characterized in that further include:
Buffer layer, between the substrate and the first gate electrode.
4. a kind of display panel, which is characterized in that including the described in any item double gate thin-film transistors of claim 1-3, also wrap
It includes:
Capacitance structure, the capacitance structure include the first electrode on the substrate and are located on second gate insulation layer
Second electrode, the upright projection of the first electrode on the substrate and the second electrode on the substrate vertical
There are overlapping regions for projection, wherein the first electrode of the capacitance structure and the first gate electrode same layer are arranged, the capacitor
The second electrode of structure and the second gate electrode same layer are arranged.
5. display panel according to claim 4, which is characterized in that further include:
Passivation layer in the source electrode and drain electrode, the passivation layer cover the source electrode and drain electrode；
Planarization layer on the passivation layer；
Anode electrode layer in the planarization, the anode electrode layer pass through on the planarization layer and the passivation layer
Opening be electrically connected with the drain electrode；
Pixel defining layer on the anode electrode layer；
Supporting layer in the pixel defining layer；
Organic luminous layer on the anode electrode and between the two neighboring pixel defining layer；
Negative electrode layer on the organic luminous layer and the pixel defining layer.
6. a kind of preparation method of double gate thin-film transistor characterized by comprising
One substrate is provided, and prepares first gate electrode on the substrate；
The first gate insulation layer is prepared in the first gate electrode, first gate insulation layer covers the first gate electrode and institute
State substrate；
Active layer, the upright projection of the active layer on the substrate and described first are prepared on first gate insulation layer
There are overlapping regions for the upright projection of gate electrode on the substrate；
The second gate insulation layer is prepared on the active layer, and second gate insulation layer covers the active layer and the first grid
Insulating layer；
Prepare the second gate electrode on second gate insulation layer, the upright projection of second gate electrode on the substrate with
There are overlapping regions for the upright projection of the active layer on the substrate；
Prepare interlayer insulating film on second gate electrode, the interlayer insulating film covers second gate electrode and described the
Two gate insulation layers；
It is exhausted by the interlayer that source electrode and drain electrode, the source electrode and the drain electrode are prepared on the interlayer insulating film
Opening in edge layer and second gate insulation layer is electrically connected with the active layer.
7. preparation method according to claim 6, which is characterized in that the material of the active layer is monocrystalline silicon, polysilicon
At least one of with oxide semiconductor material.
8. preparation method according to claim 6, which is characterized in that before preparing first gate electrode on the substrate,
Further include:
Buffer layer is prepared on the substrate.
9. a kind of preparation method of display panel characterized by comprising
One substrate is provided, and prepares the first gate electrode of double gate thin-film transistor and the first electricity of capacitance structure on the substrate
Pole, the first gate electrode are formed with the same procedure of the first electrode；
The first gate insulation layer is prepared in the first gate electrode and the first electrode, described in the first gate insulation layer covering
First gate electrode, first electrode and the substrate；
The active layer of the double gate thin-film transistor is prepared on first gate insulation layer, the active layer is on the substrate
Upright projection there are overlapping regions with the upright projection of the first gate electrode on the substrate；
The second gate insulation layer is prepared on the active layer, and second gate insulation layer covers the active layer and the first grid
Insulating layer；
Prepared on second gate insulation layer double gate thin-film transistor the second gate electrode and the capacitance structure
Two electrodes, second gate electrode are formed with the same procedure of the second electrode, and second gate electrode is on the substrate
Upright projection there are overlapping regions with the upright projection of the active layer on the substrate, the first electrode is in the base
There are overlapping regions with the upright projection of the second electrode on the substrate for upright projection on plate；
Interlayer insulating film, the interlayer insulating film covering described second are prepared on second gate electrode and the second electrode
Gate electrode, second electrode and second gate insulation layer；
It is exhausted by the interlayer that source electrode and drain electrode, the source electrode and the drain electrode are prepared on the interlayer insulating film
Opening in edge layer and second gate insulation layer is electrically connected with the active layer.
10. preparation method according to claim 9, which is characterized in that further include:
Passivation layer is prepared in the source electrode and the drain electrode, the passivation layer covers the source electrode and drain electrode；
Planarization layer is prepared on the passivation layer；
Anode electrode layer is prepared on the planarization layer, the anode electrode layer passes through the planarization layer and the passivation layer
On opening be electrically connected with the drain electrode；
Pixel defining layer is prepared on the anode electrode layer；
Supporting layer is prepared in the pixel defining layer；
Organic luminous layer is prepared on the anode electrode, and between the two neighboring pixel defining layer；
On the organic luminous layer and negative electrode layer is prepared in the pixel defining layer.
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