CN111682073A - Double-gate self-alignment structure and preparation method thereof - Google Patents
Double-gate self-alignment structure and preparation method thereof Download PDFInfo
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- CN111682073A CN111682073A CN202010536950.1A CN202010536950A CN111682073A CN 111682073 A CN111682073 A CN 111682073A CN 202010536950 A CN202010536950 A CN 202010536950A CN 111682073 A CN111682073 A CN 111682073A
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- 238000002360 preparation method Methods 0.000 title abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 77
- 239000002184 metal Substances 0.000 claims abstract description 77
- 239000004065 semiconductor Substances 0.000 claims abstract description 57
- 239000011521 glass Substances 0.000 claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 claims abstract description 7
- 238000005468 ion implantation Methods 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 6
- 230000009977 dual effect Effects 0.000 claims description 4
- 230000003071 parasitic effect Effects 0.000 abstract description 7
- 239000010409 thin film Substances 0.000 abstract description 6
- 238000004377 microelectronic Methods 0.000 abstract description 2
- 238000002347 injection Methods 0.000 description 19
- 239000007924 injection Substances 0.000 description 19
- 230000009286 beneficial effect Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 229910052725 zinc Inorganic materials 0.000 description 2
- 239000011701 zinc Substances 0.000 description 2
- 206010070834 Sensitisation Diseases 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 230000008313 sensitization Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
- H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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Abstract
The invention relates to the technical field of microelectronics, in particular to a double-gate self-alignment structure and a preparation method thereof, wherein the double-gate self-alignment structure comprises a glass layer, a first metal layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second metal layer, a third insulating layer, a flat layer and a third metal layer; the first metal layer, the first insulating layer, the semiconductor layer, the second insulating layer, the second metal layer, the third insulating layer and the flat layer are sequentially arranged on the surface of the glass layer; on the premise of maintaining the manufacturing process flow of the existing Thin Film Transistor (TFT) device, the double-gate self-alignment structure is formed by arranging the third metal layer and the second metal layer, parasitic capacitance can be reduced, miniaturization of the device is met, channel electron mobility of the device and charging rate of local current of the multi-way distributor to a display area are improved, the size of the multi-way distributor device is reduced, namely, a screen frame is narrowed, and the double-gate self-alignment structure designed by the scheme not only reduces the use cost of a photomask, but also meets the requirements of a comprehensive screen narrow frame.
Description
Technical Field
The invention relates to the technical field of microelectronics, in particular to a double-gate self-alignment structure and a preparation method thereof.
Background
With the development and progress of display technology, people put higher demands on the quality and appearance design of displays, and low-cost, full-screen and narrow-frame technologies have become the trend of display panel industry at present.
The bottom gate structure of a common thin film field effect transistor (TFT) has a larger overlapping area, so that the parasitic capacitance is larger, the size of a device is not favorably reduced, the working speed of a driving circuit is reduced, and the electron mobility of a channel of the device cannot be improved; in the prior art, the current is increased by lengthening the width of the channel so as to improve the charging rate, but the width of the lengthened channel cannot meet the design of a full-face screen and a narrow frame. Therefore, it is particularly necessary to provide a self-aligned structure capable of reducing the size of a device and a method for manufacturing the same to realize a full-screen and a narrow bezel.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: a dual-gate self-aligned structure and a method for fabricating the same are provided.
In order to solve the above technical problems, a first technical solution adopted by the present invention is:
a double-gate self-aligned structure comprises a glass layer, a first metal layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second metal layer, a third insulating layer, a flat layer and a third metal layer;
the first metal layer, the first insulating layer, the semiconductor layer, the second insulating layer, the second metal layer, the third insulating layer and the flat layer are sequentially arranged on the surface of the glass layer, at least two first via holes are formed in the second insulating layer, at least two second via holes are formed in the third insulating layer, at least two third via holes are formed in the flat layer, the third via holes are connected with the first via holes through the second via holes, the first via holes, the second via holes and the third via holes are oppositely arranged and communicated, the third metal layer is filled in the first via holes, the second via holes and the third via holes respectively, and the third metal layer filled in the first via holes is in contact with one side face, far away from the glass layer, of the semiconductor layer.
The second technical scheme adopted by the invention is as follows:
a preparation method of a double-gate self-aligned structure comprises the following steps:
s1, providing a glass layer, and covering the glass layer with a first metal layer;
s2, forming a first insulating layer covering the surface of the first metal layer and contacting with the glass layer;
s3, forming a semiconductor layer covering the surface of the first insulating layer;
s4, forming a second insulating layer covering the surface of the semiconductor layer and contacting with the first insulating layer;
s5, forming a second metal layer covering the surface of the second insulating layer;
s6, forming a third insulating layer covering the surface of the second metal layer and contacting with the second insulating layer;
s7, forming a flat layer covering the surface of the third insulating layer;
s8, at least two first via holes are formed in the second insulating layer, at least two second via holes are formed in the third insulating layer, at least two third via holes are formed in the flat layer, third metal layers are respectively formed in the first via holes, the second via holes and the third via holes, and the third metal layers formed in the first via holes are in contact with one side face, away from the glass layer, of the semiconductor layer.
The invention has the beneficial effects that:
on the premise of maintaining the manufacturing process flow of the existing Thin Film Transistor (TFT) device, the double-gate self-alignment structure is formed by arranging the third metal layer and the second metal layer, parasitic capacitance can be reduced, miniaturization of the device is met, channel electron mobility of the device and charging rate of local current of the multi-way distributor to a display area are improved, the size of the multi-way distributor device is reduced, namely, a screen frame is narrowed, and the double-gate self-alignment structure designed by the scheme not only reduces the use cost of a photomask, but also meets the requirements of a comprehensive screen narrow frame.
Drawings
FIG. 1 is a schematic diagram of a dual gate self-aligned structure according to the present invention;
FIG. 2 is a flow chart illustrating the steps of a method for fabricating a dual gate self-aligned structure according to the present invention;
description of reference numerals:
1. a glass layer; 2. a first metal layer; 3. a first insulating layer; 4. a semiconductor layer; 5. a second insulating layer; 6. a third insulating layer; 7. a second metal layer; 8. a planarization layer; 9. and a third metal layer.
Detailed Description
In order to explain technical contents, achieved objects, and effects of the present invention in detail, the following description is made with reference to the accompanying drawings in combination with the embodiments.
The most key concept of the invention is as follows: the double-gate self-alignment structure is formed by arranging the third metal layer and the second metal layer, so that the channel electron mobility of the device can be improved, and further, the comprehensive screen narrow frame is realized.
Referring to fig. 1, a technical solution provided by the present invention:
a double-gate self-aligned structure comprises a glass layer, a first metal layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second metal layer, a third insulating layer, a flat layer and a third metal layer;
the first metal layer, the first insulating layer, the semiconductor layer, the second insulating layer, the second metal layer, the third insulating layer and the flat layer are sequentially arranged on the surface of the glass layer, at least two first via holes are formed in the second insulating layer, at least two second via holes are formed in the third insulating layer, at least two third via holes are formed in the flat layer, the third via holes are connected with the first via holes through the second via holes, the first via holes, the second via holes and the third via holes are oppositely arranged and communicated, the third metal layer is filled in the first via holes, the second via holes and the third via holes respectively, and the third metal layer filled in the first via holes is in contact with one side face, far away from the glass layer, of the semiconductor layer.
From the above description, the beneficial effects of the present invention are:
on the premise of maintaining the manufacturing process flow of the existing Thin Film Transistor (TFT) device, the double-gate self-alignment structure is formed by arranging the third metal layer and the second metal layer, parasitic capacitance can be reduced, miniaturization of the device is met, channel electron mobility of the device and charging rate of local current of the multi-way distributor to a display area are improved, the size of the multi-way distributor device is reduced, namely, a screen frame is narrowed, and the double-gate self-alignment structure designed by the scheme not only reduces the use cost of a photomask, but also meets the requirements of a comprehensive screen narrow frame.
Furthermore, the semiconductor layer comprises a sub-semiconductor layer, a first ion injection layer and a second ion injection layer, the first ion injection layer is arranged at one end of the semiconductor layer, the second ion injection layer is arranged at the other end of the semiconductor layer which is symmetrical to the first ion injection layer in terms of a central axis, the sub-semiconductor layer is arranged between the first ion injection layer and the second ion injection layer, and the sub-semiconductor layer is respectively connected with the first ion injection layer and the second ion injection layer.
As is apparent from the above description, by providing the first ion implantation layer and the second ion implantation layer, the source region and the drain region having low sheet resistance can be formed.
Furthermore, the third metal layer is T-shaped.
The above description shows that the T-shaped gate structure has good stability, which is beneficial to improving the electron mobility of the device channel and avoiding the problem of overlarge parasitic capacitance.
Further, the oxide medium of the semiconductor layer is IGZO.
As can be seen from the above description, IGZO is an amorphous oxide containing indium, gallium, and zinc, and has high carrier mobility, which can greatly increase the charge/discharge rate of the field effect transistor to the pixel electrode, increase the response speed of the pixel, and have a faster panel refresh rate.
Referring to fig. 2, another technical solution provided by the present invention:
a preparation method of a double-gate self-aligned structure comprises the following steps:
s1, providing a glass layer, and covering the glass layer with a first metal layer;
s2, forming a first insulating layer covering the surface of the first metal layer and contacting with the glass layer;
s3, forming a semiconductor layer covering the surface of the first insulating layer;
s4, forming a second insulating layer covering the surface of the semiconductor layer and contacting with the first insulating layer;
s5, forming a second metal layer covering the surface of the second insulating layer;
s6, forming a third insulating layer covering the surface of the second metal layer and contacting with the second insulating layer;
s7, forming a flat layer covering the surface of the third insulating layer;
s8, at least two first via holes are formed in the second insulating layer, at least two second via holes are formed in the third insulating layer, at least two third via holes are formed in the flat layer, third metal layers are respectively formed in the first via holes, the second via holes and the third via holes, and the third metal layers formed in the first via holes are in contact with one side face, away from the glass layer, of the semiconductor layer.
Further, step S5 further includes:
the semiconductor layer is divided into a semiconductor region and an ion implantation region, and an ion implantation layer is formed in the ion implantation region.
As is apparent from the above description, by forming an ion-implanted layer in the ion-implanted region, a source region and a drain region having low sheet resistance can be formed.
Furthermore, the third metal layer is T-shaped.
From the above description, the T-shaped gate structure has good stability, which is beneficial to improving the electron mobility of the device channel and avoiding the problem of overlarge parasitic capacitance.
Further, the oxide medium of the semiconductor layer is IGZO.
From the above description, IGZO is an amorphous oxide containing indium, gallium and zinc, and has high carrier mobility, which can greatly improve the charge and discharge rate of the field effect transistor to the pixel electrode, improve the response speed of the pixel, and have faster panel refresh frequency.
Referring to fig. 1, a first embodiment of the present invention is:
a double-gate self-aligned structure comprises a glass layer 1, a first metal layer 2, a first insulating layer 3, a semiconductor layer 4, a second insulating layer 5, a second metal layer 7, a third insulating layer 6, a flat layer 8 and a third metal layer 9.
The oxide medium of the semiconductor layer 4 is IGZO.
The semiconductor layer 4 comprises a sub-semiconductor layer, a first ion injection layer and a second ion injection layer, the first ion injection layer is arranged at one end of the semiconductor layer 4, the second ion injection layer is arranged at the other end of the semiconductor layer 4 which is symmetrical to the first ion injection layer in a central axis mode, the sub-semiconductor layer is arranged between the first ion injection layer and the second ion injection layer, and the sub-semiconductor layer is connected with the first ion injection layer and the second ion injection layer respectively.
Referring to fig. 2, the second embodiment of the present invention is:
a preparation method of a double-gate self-aligned structure comprises the following steps:
s1, providing a glass layer 1, and covering the glass layer 1 with a first metal layer 2;
s2, forming a first insulating layer 3 covering the surface of the first metal layer 2 and contacting the glass layer 1;
s3, forming a semiconductor layer 4 covering the surface of the first insulating layer 3;
s4, forming a second insulating layer 5 covering the surface of the semiconductor layer 4 and contacting with the first insulating layer 3;
s5, forming a second metal layer 7 covering the surface of the second insulating layer 5;
s6, forming a third insulating layer 6 covering the surface of the second metal layer 7 and contacting with the second insulating layer 5;
s7, forming a flat layer 8 covering the surface of the third insulating layer 6;
s8, forming two first via holes in the second insulating layer 5, forming two second via holes in the third insulating layer 6, forming two third via holes in the planarization layer 8, forming third metal layers 9 in the first via holes, the second via holes, and the third via holes, respectively, and the third metal layers 9 formed in the first via holes are in contact with a side of the semiconductor layer 4 away from the glass layer 1.
Step S5 further includes:
the semiconductor layer 4 is divided into a semiconductor region and an ion implantation region, and an ion implantation layer is formed in the ion implantation region.
The ion injection layer is obtained by depositing an IGZO thin film and then performing N2 plasma treatment; the resistivity of the IGZO film can be reduced by the N2 plasma treatment.
Step S8 specifically includes:
plating a layer of photoresist on the flat layer 8, transferring the electrode pattern to the flat layer through chemical reaction of photoresist sensitization, washing off the unnecessary photoresist through a developing technology, forming a groove on the photoresist, enabling substances capable of reacting with the flat layer 8, the third insulating layer 6 and the second insulating layer 5 to respectively perform chemical reaction with the flat layer 8, the third insulating layer 6 and the second insulating layer 5 to respectively form a first via hole, a second via hole and a third via hole, and plating third metal on the first via hole, the second via hole and the third via hole through an evaporation machine, so that a third metal layer 9 is formed to be in contact with one side face, far away from the glass layer 1, of the semiconductor layer 4.
In summary, the double-gate self-aligned structure and the manufacturing method thereof provided by the invention form the double-gate self-aligned structure by arranging the third metal layer and the second metal layer on the premise of maintaining the manufacturing process flow of the existing Thin Film Transistor (TFT) device, can reduce parasitic capacitance, meet the miniaturization of the device, improve the channel electron mobility of the device and the charging rate of the current in the demultiplexer region to the display region, and reduce the size of the demultiplexer device, i.e., narrow the screen frame.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent changes made by using the contents of the present specification and the drawings, or applied directly or indirectly to the related technical fields, are included in the scope of the present invention.
Claims (8)
1. A double-gate self-aligned structure is characterized by comprising a glass layer, a first metal layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second metal layer, a third insulating layer, a flat layer and a third metal layer;
the first metal layer, the first insulating layer, the semiconductor layer, the second insulating layer, the second metal layer, the third insulating layer and the flat layer are sequentially arranged on the surface of the glass layer, at least two first via holes are formed in the second insulating layer, at least two second via holes are formed in the third insulating layer, at least two third via holes are formed in the flat layer, the third via holes are connected with the first via holes through the second via holes, the first via holes, the second via holes and the third via holes are oppositely arranged and communicated, the third metal layer is filled in the first via holes, the second via holes and the third via holes respectively, and the third metal layer filled in the first via holes is in contact with one side face, far away from the glass layer, of the semiconductor layer.
2. The dual gate self-aligned structure of claim 1, wherein the semiconductor layer comprises a sub-semiconductor layer, a first ion implanted layer and a second ion implanted layer, the first ion implanted layer is disposed at one end of the semiconductor layer, the second ion implanted layer is disposed at the other end of the semiconductor layer that is axially symmetric to the first ion implanted layer, the sub-semiconductor layer is disposed between the first ion implanted layer and the second ion implanted layer, and the sub-semiconductor layer is connected to the first ion implanted layer and the second ion implanted layer respectively.
3. The double gate self-aligned structure of claim 1, wherein the third metal layer is T-shaped.
4. The double gate self-aligned structure of claim 1, wherein the oxide dielectric of the semiconductor layer is IGZO.
5. A method of fabricating the double gate self-aligned structure of claim 1, comprising the steps of:
s1, providing a glass layer, and covering the glass layer with a first metal layer;
s2, forming a first insulating layer covering the surface of the first metal layer and contacting with the glass layer;
s3, forming a semiconductor layer covering the surface of the first insulating layer;
s4, forming a second insulating layer covering the surface of the semiconductor layer and contacting with the first insulating layer;
s5, forming a second metal layer covering the surface of the second insulating layer;
s6, forming a third insulating layer covering the surface of the second metal layer and contacting with the second insulating layer;
s7, forming a flat layer covering the surface of the third insulating layer;
s8, at least two first via holes are formed in the second insulating layer, at least two second via holes are formed in the third insulating layer, at least two third via holes are formed in the flat layer, third metal layers are respectively formed in the first via holes, the second via holes and the third via holes, and the third metal layers formed in the first via holes are in contact with one side face, away from the glass layer, of the semiconductor layer.
6. The method for fabricating a dual gate self-aligned structure as claimed in claim 5, step S5 further comprises:
the semiconductor layer is divided into a semiconductor region and an ion implantation region, and an ion implantation layer is formed in the ion implantation region.
7. The method as claimed in claim 5, wherein the third metal layer is T-shaped.
8. The method of claim 5, wherein the oxide dielectric of the semiconductor layer is IGZO.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030094611A1 (en) * | 2001-11-14 | 2003-05-22 | Semiconductor Energy Laboratory Co., Ltd | Semiconductor device and method of fabricating the same |
| CN102315278A (en) * | 2010-07-07 | 2012-01-11 | 三星移动显示器株式会社 | Double grid thin-film transistor and comprise the OLED display unit of double grid thin-film transistor |
| CN104681628A (en) * | 2015-03-17 | 2015-06-03 | 京东方科技集团股份有限公司 | Polycrystalline silicon thin film transistor, array substrate, manufacturing methods and display device |
| CN108987480A (en) * | 2017-06-02 | 2018-12-11 | 上海和辉光电有限公司 | Double gate thin-film transistor and preparation method thereof, display panel and preparation method thereof |
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2020
- 2020-06-12 CN CN202010536950.1A patent/CN111682073A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030094611A1 (en) * | 2001-11-14 | 2003-05-22 | Semiconductor Energy Laboratory Co., Ltd | Semiconductor device and method of fabricating the same |
| CN102315278A (en) * | 2010-07-07 | 2012-01-11 | 三星移动显示器株式会社 | Double grid thin-film transistor and comprise the OLED display unit of double grid thin-film transistor |
| CN104681628A (en) * | 2015-03-17 | 2015-06-03 | 京东方科技集团股份有限公司 | Polycrystalline silicon thin film transistor, array substrate, manufacturing methods and display device |
| CN108987480A (en) * | 2017-06-02 | 2018-12-11 | 上海和辉光电有限公司 | Double gate thin-film transistor and preparation method thereof, display panel and preparation method thereof |
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