CN110993613A

CN110993613A - Array substrate and manufacturing method thereof

Info

Publication number: CN110993613A
Application number: CN201911183195.7A
Authority: CN
Inventors: 李治福; 肖军城; 艾飞; 尹国恒
Original assignee: Wuhan China Star Optoelectronics Technology Co Ltd
Current assignee: Wuhan China Star Optoelectronics Technology Co Ltd
Priority date: 2019-11-27
Filing date: 2019-11-27
Publication date: 2020-04-10

Abstract

The invention discloses a manufacturing method of an array substrate, which comprises the steps of (1) forming a first grid precursor of an LTPS thin film transistor and a second grid precursor of an oxide thin film transistor by taking a photoresist pattern as a mask in a photoetching process, (2) carrying out ion heavy doping by taking the photoresist pattern as the mask to form ion heavy doping areas on two opposite sides of a polycrystalline silicon layer, (3) etching the first grid precursor and the second grid precursor to form a first grid and a second grid, (4) removing the photoresist pattern and carrying out ion light doping by taking the first grid as the mask to form ion light doping areas on two opposite sides of the polycrystalline silicon layer, and (5) forming two first source and drain electrodes of the LTPS thin film transistor and two second source and drain electrodes of the oxide thin film transistor in another photoetching process so as to avoid influencing the compatibility of the LTPS thin film transistor process and the oxide thin film transistor process, reducing the number of masks required. The present disclosure also discloses an array substrate manufactured by the method.

Description

Array substrate and manufacturing method thereof

Technical Field

The present disclosure relates to the field of Liquid Crystal Display (LCD) technology, and more particularly, to an array substrate and a method for fabricating the same.

Background

LCDs have high image quality, low power consumption, and light weight, and are widely used. In recent years, LCDs have been increasingly developed toward narrow bezels and low power consumption. In order to save more power for LCDs with limited space and battery capacity, low temperature Poly-Oxide (LTPO) technology has been developed. The LTPO technology generally uses Low Temperature Polysilicon (LTPS) thin film transistors in a Gate driver on Array (GOA) area of an Array substrate, and has the advantages of high mobility, small size, and fast charging, thereby effectively reducing the size of a frame. Also, an oxide thin film transistor, such as an Indium Gallium Zinc Oxide (IGZO) thin film transistor, which has a small dark current and can be driven at a low frequency, is used in the display Area (AA). Therefore, LTPO technology can achieve both narrow bezel and low power consumption.

However, to solve the compatibility problem between the LTPS tft process and the oxide tft process, the LTPO technology requires more than ten masks, which is costly. Therefore, there is a need to develop a new array substrate and a method for manufacturing the same to reduce the number of masks required without affecting the compatibility of the LTPS tft process and the oxide tft process.

Disclosure of Invention

In order to effectively solve the technical problem of high mask cost of the conventional Low Temperature Poly-Oxide (LTPO) array substrate without affecting the compatibility of the LTPS TFT process and the Oxide TFT process, the disclosure provides a manufacturing method of the array substrate. The manufacturing method of the array substrate comprises the following steps: providing a substrate, wherein the substrate comprises a display area and a gate driving circuit area surrounding the display area; forming a polysilicon layer on the gate drive circuit region of the substrate; coating a gate insulating layer on the substrate and the polycrystalline silicon layer; forming a first metal layer on the gate insulating layer; forming a photoresist pattern on the first metal layer; etching the first metal layer using the photoresist pattern as a mask to form a first gate precursor in the gate driving circuit region and a second gate precursor in the display region; carrying out ion heavy doping by using the photoresist pattern as a mask to form two ion heavy doping areas on two opposite sides of the polycrystalline silicon layer; etching the first grid precursor and the second grid precursor by using the photoresist pattern as a mask to form a first grid and a second grid; removing the photoresist pattern; and carrying out ion light doping by using the first grid electrode as a mask so as to form two ion light doped regions on two opposite sides of the polycrystalline silicon layer.

In one embodiment, the heavily and lightly ion-doped regions are formed by N-type or P-type ions.

In one embodiment, the method for manufacturing an array substrate further includes: coating a dielectric layer on the gate insulating layer, the first gate and the second gate; forming an oxide layer on the dielectric layer in a region corresponding to the second gate; forming two first through holes penetrating through the dielectric layer and the gate insulating layer, wherein the two first through holes enable the two ion heavily doped regions to be partially exposed; and forming two first source-drain electrodes and two second source-drain electrodes on the dielectric layer, wherein the two first source-drain electrodes are electrically connected to the two ion heavily doped regions through the two first through holes respectively, and the two second source-drain electrodes are directly electrically connected to the oxide layer.

In one embodiment, the oxide layer is made of indium gallium zinc oxide, indium gallium oxide, gallium zinc oxide, indium hafnium zinc oxide, indium tin oxide, indium zinc oxide, tin zinc oxide, indium aluminum zinc oxide, and combinations thereof, but is not limited thereto.

In one embodiment, the gate driving circuit region comprises a low-temperature polysilicon thin film transistor consisting of a polysilicon layer, a gate insulating layer, a first gate, a dielectric layer and two first source and drain electrodes, wherein the polysilicon layer comprises two ion heavily doped regions and two lightly doped regions; and the second grid electrode, the dielectric layer, the oxide layer and the two second source and drain electrodes in the display area form an oxide thin film transistor.

In one embodiment, the method for manufacturing an array substrate further includes: forming a first insulating layer on the dielectric layer, the two first source/drain electrodes, the oxide layer and the two second source/drain electrodes, wherein the first insulating layer is provided with a second through hole so that one part of the two second source/drain electrodes is exposed; forming a flat layer on the first insulating layer, wherein the flat layer is provided with a third through hole communicated with the second through hole; forming a common electrode layer on the flat layer in the display area, wherein the common electrode layer is provided with a fourth through hole communicated with the third through hole; forming a second insulating layer on the flat layer and the common electrode layer, wherein the second insulating layer is provided with a fifth through hole communicated with the second through hole; and forming a pixel electrode layer on the second insulating layer in the display area, wherein the pixel electrode layer is electrically connected to the partially exposed second source/drain electrode through the fifth through hole of the second insulating layer and the second through hole of the first insulating layer.

In another embodiment, the method for manufacturing an array substrate further includes, after performing ion light doping: coating a dielectric layer on the gate insulating layer, the first gate and the second gate; forming an oxide layer on the dielectric layer in a region corresponding to the second gate; forming a protective layer on the dielectric layer and the oxide layer; forming two first through holes and two second through holes, wherein the two first through holes are formed in the gate driving circuit region and penetrate through the protective layer, the dielectric layer and the gate insulating layer to expose parts of the two ion heavily doped regions, and the two second through holes are formed in the display region and penetrate through the protective layer to expose two opposite sides of the oxide layer; and forming two first source-drain electrodes and two second source-drain electrodes on the protective layer, wherein the two first source-drain electrodes are electrically connected to the two ion heavily doped regions through the two first through holes respectively, and the two second source-drain electrodes are electrically connected to the oxide layer through the two second through holes respectively.

In another embodiment, the low temperature polysilicon thin film transistor is composed of a polysilicon layer, a gate insulating layer, a first gate, a dielectric layer, a protective layer and two first source/drain electrodes, which contain two ion heavily doped regions and two lightly doped regions in the gate driving circuit region, and the oxide thin film transistor is composed of a second gate, a dielectric layer, an oxide layer, a protective layer and two second source/drain electrodes in the display region.

In another embodiment, the method for manufacturing an array substrate further includes: forming a flat layer on the protective layer, the two first source-drain electrodes and the two second source-drain electrodes, wherein the flat layer is provided with a third through hole so that one part of the two second source-drain electrodes is exposed; forming a common electrode layer on the flat layer in the display area, wherein the common electrode layer is provided with a fourth through hole communicated with the third through hole; forming an insulating layer on the flat layer and the common electrode layer, wherein the insulating layer is provided with a fifth through hole at a fourth through hole corresponding to the common electrode layer and a third through hole corresponding to the flat layer; and forming a pixel electrode layer on the insulating layer in the display area, wherein the pixel electrode layer is electrically connected to the partially exposed second source/drain electrode through a fifth through hole of the insulating layer.

The present disclosure also provides an array substrate including a substrate, a polysilicon layer, a gate insulating layer, a first gate and a second gate. The substrate comprises a display area and a gate driving circuit area surrounding the display area. The polycrystalline silicon layer is arranged on the gate driving circuit region of the substrate and comprises two ion heavily doped regions positioned on two opposite sides of the polycrystalline silicon layer and two lightly doped regions which are close to the center of the polycrystalline silicon layer and are respectively adjacent to the two ion heavily doped regions. The grid insulating layer covers the substrate and the polycrystalline silicon layer. The first grid electrode is arranged on a region of the grid insulating layer corresponding to a part of the polycrystalline silicon layer between the two ion lightly doped regions. The second grid electrode is arranged on the grid insulation layer in the display area.

In one embodiment, the array substrate further includes: a dielectric layer, an oxide layer, two first source-drain electrodes and two second source-drain electrodes. The dielectric layer covers the gate insulating layer, the first gate and the second gate. The oxide layer is disposed on a region of the dielectric layer corresponding to the second gate. The two first source-drain electrodes are arranged on the dielectric layer of the gate driving circuit region and penetrate through the dielectric layer and the gate insulating layer to be electrically connected with the two ion heavily doped regions. The two second source and drain electrodes are arranged on the dielectric layer in the display area and are electrically connected to two opposite sides of the oxide layer.

In an embodiment, the low temperature polysilicon thin film transistor is composed of a polysilicon layer, a gate insulating layer, a first gate, a dielectric layer and two first source and drain electrodes, wherein the polysilicon layer, the gate insulating layer, the first gate, the dielectric layer and the two first source and drain electrodes are provided with two ion heavily doped regions and two lightly doped regions in the gate driving circuit region. And the second grid electrode, the dielectric layer, the oxide layer and the two second source and drain electrodes in the display area form an oxide thin film transistor.

In another embodiment, the array substrate including the substrate, the polysilicon layer, the gate insulating layer, the first gate electrode and the second gate electrode further includes: a dielectric layer, an oxide layer, a protection layer, two first source/drain electrodes and two second source/drain electrodes. The dielectric layer covers the gate insulating layer, the first gate and the second gate. The oxide layer is disposed on a region of the dielectric layer corresponding to the second gate. The protective layer covers the dielectric layer and the oxide layer. The two first source and drain electrodes are arranged on the protective layer in the gate driving circuit region and penetrate through the protective layer, the dielectric layer and the gate insulating layer to be electrically connected with the two ion heavily doped regions. The two second source and drain electrodes are arranged on the protective layer in the display area and penetrate through the protective layer to be electrically connected with the two opposite sides of the oxide layer.

Compared with the prior art, the manufacturing method of the array substrate provided by the present disclosure includes (1) forming a first gate precursor of the LTPS tft and a second gate precursor of the oxide tft in the same photolithography process by using a photoresist pattern as a mask, (2) performing ion heavy doping by using the photoresist pattern as a mask to form ion heavy doped regions on two opposite sides of the polysilicon layer, (3) etching the first gate precursor and the second gate precursor by using the photoresist pattern as a mask to form a first gate and a second gate, (4) performing ion light doping by using the first gate as a mask after removing the photoresist pattern to form ion light doped regions on two opposite sides of the polysilicon layer, and (5) forming two first source drains of the LTPS tft and two second source drains of the oxide tft in the same photolithography process, the number of masks used for manufacturing the LTPO array substrate can be reduced under the condition of not influencing the compatibility of the LTPS thin film transistor manufacturing process and the oxide thin film transistor manufacturing process, and the technical problem of high mask cost of the existing LTPO array substrate is effectively solved.

Drawings

In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 to 12 are schematic flow charts illustrating a method for manufacturing an array substrate according to a first embodiment of the present disclosure, wherein fig. 12 is an array substrate manufactured by the method according to the first embodiment of the present disclosure.

Fig. 1 to 6 and fig. 13 to 19 are schematic flow charts illustrating a method for manufacturing an array substrate according to a second embodiment of the present disclosure, wherein fig. 19 is an array substrate manufactured by the method according to the second embodiment of the present disclosure.

Detailed Description

Referring to fig. 1 to 12, a method for manufacturing an array substrate 1000 according to a first embodiment of the present disclosure includes steps S1-S20.

Step S1: a substrate 10 is provided, wherein the substrate 10 includes a display area AA and a gate driving circuit area GOA surrounding the display area AA (see fig. 1). The substrate 10 may be a transparent substrate. The substrate 10 may be made of a non-metal material having a certain strength and guiding light, such as glass, quartz, and transparent resin.

Step S2: a buffer layer 20 is coated on the substrate 10 (see fig. 1). The buffer layer 20 may be made of SiOx, SiNx, or a combination thereof.

Step S3: a polysilicon layer 30 is formed on the buffer layer 20 in the gate driving circuit region GOA (see fig. 1). The method comprises the following steps: an amorphous silicon layer is formed on the buffer layer 20, and then crystallized by a laser annealing method to form a polysilicon layer, and then patterned by a photolithography process to obtain a polysilicon layer 30.

Step S4: a gate insulating layer 40 is coated on the polysilicon layer 30 and the buffer layer 20 (see fig. 2). The gate insulating layer 40 may be made of SiOx, SiNx, or a combination thereof. The material of the gate insulating layer 40 may be the same as or different from the material of the buffer layer 20.

Step S5: a first metal layer 50 is formed on the gate insulating layer 40 (see fig. 2). The first metal layer 50 may be made by Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD).

Step S6: a photoresist pattern 60 is formed on the first metal layer 50 (see fig. 2). The method comprises the following steps: a photoresist is coated on the first metal layer 50 and patterned by a full exposure process to form a photoresist pattern 60.

Step S7: using the photoresist pattern 60 as a mask, the first metal layer 50 is etched to form a first gate precursor 51 in the gate driving circuit area GOA and a second gate precursor 52 in the display area AA (see fig. 3).

Step S8: using the photoresist pattern 60 as a mask, ion heavily doping is performed to form two heavily doped regions 31 on two opposite sides of the polysilicon layer 30 not covered by the photoresist pattern 60 (see fig. 3).

Step S9: the first gate precursor 51 and the second gate precursor 52 are etched (re-etch) using the photoresist pattern 60 as a mask, and opposite sides of the first gate precursor 51 and the second gate precursor 52 under the photoresist pattern 60 are removed to form a first gate 53 and a second gate 54 (see fig. 4).

Step S10: the photoresist pattern 60 is removed (see fig. 5).

Step S11: with the first gate 53 as a mask, ion lightly doping is performed, so that two ion lightly doped regions 32 are formed on two opposite sides of the polysilicon layer 30 not covered by the first gate 53 and not formed with the ion heavily doped region 31 (see fig. 5). The ion heavy doping and the ion light doping are performed using N-type ions. The heavy ion doping and the light ion doping can also be performed using P-type ions.

Step S12: a dielectric layer (dielectric layer)70 is coated on the gate insulating layer 40, the first gate electrode 53 and the second gate electrode 54 (see fig. 6). The dielectric layer 70 may be made of SiOx, SiNx, or a combination thereof. The materials of the dielectric layer 70, the gate insulating layer 40, and the buffer layer 20 may be identical, completely different, or both.

Step S13: an oxide layer 80 is formed on the dielectric layer 70 in the region corresponding to the second gate 54. The orthographic projection of the oxide layer 80 on the substrate 10 can completely overlap with the orthographic projection of the second gate 54 on the substrate 10 (see fig. 6). The oxide layer 80 is comprised of a semiconductor oxide. The semiconductor oxide includes indium gallium zinc oxide, indium gallium oxide, gallium zinc oxide, indium hafnium zinc oxide, indium tin oxide, indium zinc oxide, tin zinc oxide, and indium aluminum zinc oxide, but is not limited thereto.

Step S14: two first vias 71 are formed through the dielectric layer 70 and the gate insulating layer 40. The two first through holes 71 partially expose the two heavily doped regions 31 (see fig. 7).

Step S15: a second metal layer 90 is deposited on the dielectric layer 70 and the oxide layer 80, and fills the two first vias 71 (see fig. 8). The second metal layer 90 may be made by Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), or Atomic Layer Deposition (ALD).

Step S16: the second metal layer 90 is patterned to form two first source/

drain electrodes

91 and 92 and two second source/

drain electrodes

93 and 94. The first source/

drain electrodes

91 and 92 are electrically connected to the heavily doped regions 31 through the first vias 71. Two second source and drain

electrodes

93 and 94 are electrically connected directly to the oxide layer 80. The LTPS thin film transistor is formed by the polysilicon layer 30, the gate insulating layer 40, the first gate 53, the dielectric layer 70, and the two first source/

drain electrodes

91 and 92, which contain the two heavily doped ion regions 31 and the two lightly doped regions 32 in the gate driving circuit region GOA. The second gate 54, the dielectric layer 70, the oxide layer 80 and the two second source/

drain electrodes

93 and 94 in the display area AA constitute an oxide thin film transistor (see fig. 9).

Step S17: a first insulating layer 100 is formed on the dielectric layer 70, the two first source/

drain electrodes

91 and 92, the oxide layer 80, and the two second source/

drain electrodes

93 and 94. The first insulating layer 100 is provided with a second via hole 101, so that a portion of the second source/drain 94 is exposed (see fig. 10). The first insulating layer 100 may be composed of SiOx.

Step S18: a planarization layer 110 is formed on the first insulating layer 100. The planarization layer 110 has a third via 111, which is connected to the second via 101 of the first insulating layer 100, so that the exposed portion of the second source/drain 94 remains exposed (see fig. 10). The planarization layer 110 is made of an insulating material.

Step S19: a common electrode layer 120 is formed on the planarization layer 110 in the display area AA. The common electrode layer 120 has a fourth via 111, which is connected to the third via 111 of the planarization layer 110 and the second via 101 of the first insulating layer 100, so that the exposed portion of the second source/drain 94 remains exposed (see fig. 10). The common electrode 120 may be composed of a transparent conductive metal oxide.

Step S20: a second insulating layer 130 is formed on the planarization layer 110 and the common electrode layer 120. The second insulating layer 130 is provided with a fifth through hole 131. The fifth via 131 is communicated with the second via 101 of the first insulating layer 100, so that the exposed portion of the second source/drain 94 remains exposed, the sidewall of the fourth via 111 of the common electrode layer 120 and the sidewall of the third via 111 of the planarization layer 110 are covered by the second insulating layer 130, and the sidewall of the second via 101 of the first insulating layer 100 is connected to the second insulating layer 130. That is, the second insulating layer 130 and the first insulating layer 100 cover the common electrode layer 120 and the planarization layer 110 (see fig. 11).

Step S21: a pixel electrode layer 140 is formed on the second insulating layer 130 in the display area AA, covering the sidewall of the fifth via 131 of the second insulating layer 130, the sidewall of the second via 101 of the first insulating layer 100, and the exposed portion of the second source/drain 94. That is, the pixel electrode layer 140 is electrically connected to the second source/drain electrode 94 through the fifth via 131 of the second insulating layer 130 and the second via 101 of the first insulating layer 100 (see fig. 12). The method comprises the following steps: the pixel electrode material is deposited on the second insulating layer 130 by a physical vapor deposition method, a chemical vapor deposition method, or an atomic layer deposition method, and then patterned by a photolithography process and an etching process to form the pixel electrode layer 140.

Referring to fig. 12, the first embodiment of the present disclosure further provides an array substrate 1000, which can be manufactured by the foregoing manufacturing method. The array substrate 1000 is a Low Temperature Poly-Oxide (LTPO) array substrate. The array substrate 1000 includes a substrate 10, a polysilicon layer 30, a gate insulating layer 40, a first gate 53 and a second gate 54. The substrate 10 includes a display area AA and a gate driving circuit area GOA surrounding the display area. The substrate 10 may be a transparent substrate. The substrate 10 may be made of a non-metal material having a certain strength and guiding light, such as glass, quartz, and transparent resin. The polysilicon layer 30 is disposed on the gate driving circuit region GOA of the substrate 10, and includes two ion heavily doped regions 31 located at two opposite sides thereof and two ion lightly doped regions 32 near the center thereof and respectively adjacent to the two ion heavily doped regions 31. The two heavily doped ion regions 31 and the two lightly doped ion regions 32 can be N-type ion doped regions or P-type ion doped regions. The gate insulating layer 40 covers the substrate 10 and the polysilicon layer 30. The gate insulating layer 40 may be made of SiOx, SiNx, or a combination thereof. The material of the gate insulating layer 40 may be the same as or different from the material of the buffer layer 20. The first gate electrode 53 is disposed on a portion of the polysilicon layer 30 in the gate insulating layer 40 corresponding to a portion between the two lightly doped regions 32. The second gate electrode 54 is disposed on the gate insulating layer 40 in the display area AA. The first gate 53 and the second gate 54 are made of a metal material.

In an embodiment, the array substrate 1000 may further include: a buffer layer 20. The buffer layer 20 is disposed between the substrate 10 and the polysilicon layer 30. The buffer layer 20 may be made of SiOx, SiNx, or a combination thereof.

In one embodiment, the array substrate 1000 further includes: a dielectric layer 70, an oxide layer 80, two first source/

drain electrodes

91, 92 and two second source/

drain electrodes

93, 94. The dielectric layer 70 covers the gate insulating layer 40, the first gate 53 and the second gate 54. The dielectric layer 70 may be made of SiOx, SiNx, or a combination thereof. The materials of the dielectric layer 70, the gate insulating layer 40, and the buffer layer 20 may be identical, completely different, or both. An oxide layer 80 is disposed on a region of the dielectric layer 70 corresponding to the second gate 54. An orthogonal projection of the oxide layer 80 on the substrate 10 may completely overlap with an orthogonal projection of the second gate 54 on the substrate 10. The oxide layer 80 is comprised of a semiconductor oxide. The semiconductor oxide includes indium gallium zinc oxide, indium gallium oxide, gallium zinc oxide, indium hafnium zinc oxide, indium tin oxide, indium zinc oxide, tin zinc oxide, and indium aluminum zinc oxide, but is not limited thereto. The two first source/

drain electrodes

91 and 92 are disposed on the dielectric layer 70 of the gate driving circuit area GOA and electrically connected to the heavily doped regions 31 through the dielectric layer 70 and the gate insulating layer 40. Two second source/

drain electrodes

93, 94 are disposed on the dielectric layer 70 in the display area AA and electrically connected to two opposite sides of the oxide layer 80. The first source-

drain electrodes

91 and 92 and the second source-

drain electrodes

93 and 94 are made of a metal material.

The polysilicon layer 30, the gate insulating layer 40, the first gate 53, the dielectric layer 70, and the first source/

drain electrodes

91 and 92 in the gate driving circuit area GOA include two heavily doped ion regions 31 and two lightly doped regions 32, which form a low temperature polysilicon thin film transistor. The second gate 54, the dielectric layer 70, the oxide layer 80 and the two second source/

drain electrodes

93 and 94 in the display area AA constitute an oxide thin film transistor. In one embodiment, the array substrate 1000 further includes: a first insulating layer 100, a planarization layer 110, a common electrode layer 120, a second insulating layer 130, and a pixel electrode layer 140. Referring to fig. 10-12, a first insulating layer 100 covers the dielectric layer 70, the two first source/

drain electrodes

91 and 92, the oxide layer 80, and the two second source/

drain electrodes

93 and 94. The first insulating layer 100 is provided with a second via hole 101 exposing a portion of the second source/drain 94. The first insulating layer 100 may be composed of SiOx. The planarization layer 110 is disposed on the first insulating layer 100. The planarization layer 110 has a third through hole 111, which is connected to the second through hole 101 of the first insulating layer 100. The planarization layer 110 is made of an insulating material. The common electrode layer 120 is disposed on the planarization layer 110 in the display area AA. The common electrode layer 120 has a fourth through hole 111, which is communicated with the third through hole 111 of the planarization layer 110 and the second through hole 101 of the first insulating layer 100. The common electrode 120 may be composed of a transparent conductive metal oxide. The second insulating layer 130 covers the planarization layer 110 and the common electrode layer 120. The second insulating layer 130 is provided with a fifth through hole 131. The fifth via 131 communicates with the second via 101 of the first insulating layer 100. The sidewall of the fourth via hole 111 of the common electrode layer 120 and the sidewall of the third via hole 111 of the planarization layer 110 are covered by the second insulating layer 130, and the sidewall of the second via hole 101 of the first insulating layer 100 is connected to the second insulating layer 130. That is, the second insulating layer 130 and the first insulating layer 100 cover the common electrode layer 120 and the planarization layer 110. The pixel electrode layer 140 is disposed on the second insulating layer 130 in the display area AA, and covers the sidewall of the fifth via 131 of the second insulating layer 130, the sidewall of the second via 101 of the first insulating layer 100, and the exposed portion of the second source/drain 94. That is, the pixel electrode layer 140 is electrically connected to the second source/drain electrode 94 through the fifth via 131 of the second insulating layer 130 and the second via 101 of the first insulating layer 100.

The second embodiment of the present disclosure provides another method for manufacturing an array substrate 2000, which includes steps S201-S220. Steps S201-S213 of the second embodiment of the present disclosure are the same as steps S1-S13 of the first embodiment of the present disclosure, please refer to FIGS. 1-6. Steps S214-S220 of the second embodiment of the present disclosure are described below with reference to FIGS. 13-18.

Step S214: a passivation layer 200 is formed on the dielectric layer 70 and the oxide layer 80 (see fig. 13). The protection layer 200 is for preventing the oxide layer 80 from being deteriorated by exposure to harmful substances such as oxygen and moisture. The protection layer 200 may be composed of an insulating material such as silicon oxide (SiOx). The protection layer 200 may be made by chemical vapor deposition, but is not limited thereto.

Step S215: two first vias 201 and two second vias 202 are formed. Two first through holes 201 are formed in the gate driving circuit area GOA, and penetrate through the protection layer 200, the dielectric layer 70 and the gate insulating layer 40, so that the two heavily doped ion regions 31 are partially exposed. Two second through holes 202 are formed in the display area AA, penetrating through the passivation layer 200, so that the oxide layer 80 is partially exposed (see fig. 14).

Step S216: a second metal layer 210 is deposited on the passivation layer 200 and fills the two first vias 201 and the two second vias 202 (see fig. 15).

Step S217: the second metal layer 210 is patterned to form two first source/

drain electrodes

211 and 212 and two second source/

drain electrodes

213 and 214. The two first source/

drain electrodes

211 and 212 are electrically connected to the heavily doped ion regions 31 through the two first vias 201, respectively. Two second source/

drain electrodes

213 and 214 are electrically connected to the oxide layer 80 through two second vias 202, respectively. The LTPS thin film transistor is formed by the polysilicon layer 30, the gate insulating layer 40, the first gate 53, the dielectric layer 70, the passivation layer 200, and the two first source/

drain electrodes

211 and 212, which are contained in the gate driving circuit area GOA and include the two heavily doped ion regions 31 and the two lightly doped regions 32. The second gate 54, the dielectric layer 70, the oxide layer 80, the passivation layer 200 and the two second source/

drain electrodes

213 and 214 in the display area AA constitute an oxide thin film transistor (see fig. 16).

Step S218: a planarization layer 220 is formed on the passivation layer 200, the two first source/

drain electrodes

211 and 212, and the two second source/

drain electrodes

213 and 214. The planarization layer 220 has a third via 221 exposing a portion of the second source/drain 214 (see fig. 17).

Step S219: a common electrode layer 230 is formed on the planarization layer 220 in the display area AA. The common electrode layer 230 has a fourth via 231, which is connected to the third via 221 of the planarization layer 220, so that the exposed portion of the second source/drain electrode 214 remains exposed (see fig. 17).

Step S220: an insulating layer 240 is formed on the planarization layer 220 and the common electrode layer 230. The insulating layer 240 is provided with a fifth through hole 241 at a position corresponding to the fourth through hole 231 of the common electrode layer 230 and the third through hole 221 of the planarization layer 220, so that the exposed portion of the second source/drain electrode 244 remains exposed, and the sidewall of the fourth through hole 231 of the common electrode layer 230 and the sidewall of the third through hole 221 of the planarization layer 220 are covered by the insulating layer 240 (see fig. 18).

Step S221: a pixel electrode layer 250 is formed on the insulating layer 240 in the display area AA, covering the sidewall of the fifth via 241 of the insulating layer 240 and the exposed portion of the second source/drain 214. That is, the pixel electrode layer 250 is electrically connected to the second source/drain electrode 94 through the fifth via 241 of the insulating layer 240 (see fig. 19).

Referring to fig. 19, a second embodiment of the present disclosure further provides an array substrate 2000, which can be manufactured by the above-mentioned manufacturing method including steps S201 to S220. The array substrate 2000 is a Low temperature poly-Oxide (LTPO) array substrate. The array substrate 2000 includes a substrate 10, a polysilicon layer 30, a gate insulating layer 40, a first gate 53 and a second gate 54. The substrate 10 includes a display area AA and a gate driving circuit area GOA surrounding the display area. The substrate 10 may be a transparent substrate. The substrate 10 may be made of a non-metal material having a certain strength and guiding light, such as glass, quartz, and transparent resin. The polysilicon layer 30 is disposed on the gate driving circuit region GOA of the substrate 10, and includes two ion heavily doped regions 31 located at two opposite sides thereof and two ion lightly doped regions 32 near the center thereof and respectively adjacent to the two ion heavily doped regions 31. The two heavily doped ion regions 31 and the two lightly doped ion regions 32 can be N-type ion doped regions or P-type ion doped regions. The gate insulating layer 40 covers the substrate 10 and the polysilicon layer 30. The gate insulating layer 40 may be made of SiOx, SiNx, or a combination thereof. The material of the gate insulating layer 40 may be the same as or different from the material of the buffer layer 20. The first gate electrode 53 is disposed on a portion of the polysilicon layer 30 in the gate insulating layer 40 corresponding to a portion between the two lightly doped regions 32. The second gate electrode 54 is disposed on the gate insulating layer 40 in the display area AA. The first gate 53 and the second gate 54 are made of a metal material.

In an embodiment, the array substrate 2000 may further include: a buffer layer 20. The buffer layer 20 is disposed between the substrate 10 and the polysilicon layer 30. The buffer layer 20 may be made of SiOx, SiNx, or a combination thereof.

In one embodiment, the array substrate 2000 further includes: a dielectric layer 70, an oxide layer 80, a passivation layer 200, two first source/

drain electrodes

211, 212 and two second source/

drain electrodes

213, 214. The dielectric layer 70 covers the gate insulating layer 40, the first gate 53 and the second gate 54. The dielectric layer 70 may be made of SiOx, SiNx, or a combination thereof. The materials of the dielectric layer 70, the gate insulating layer 40, and the buffer layer 20 may be identical, completely different, or both. An oxide layer 80 is disposed on a region of the dielectric layer 70 corresponding to the second gate 54. An orthogonal projection of the oxide layer 80 on the substrate 10 may completely overlap with an orthogonal projection of the second gate 54 on the substrate 10. The oxide layer 80 is comprised of a semiconductor oxide. The semiconductor oxide includes indium gallium zinc oxide, indium gallium oxide, gallium zinc oxide, indium hafnium zinc oxide, indium tin oxide, indium zinc oxide, tin zinc oxide, and indium aluminum zinc oxide, but is not limited thereto. The passivation layer 200 covers the dielectric layer 70 and the oxide layer 80. The protection layer 200 is for preventing the oxide layer 80 from being deteriorated by exposure to harmful substances such as oxygen and moisture. The protection layer 200 may be composed of an insulating material such as silicon oxide (SiOx). The two first source/

drain electrodes

211, 212 are disposed on the protection layer 200 of the gate driving circuit area GOA, and electrically connected to the two heavily doped ion regions 31 through the protection layer 200, the dielectric layer 70 and the gate insulating layer 40. The two second source and drain

electrodes

213, 214 are disposed on the passivation layer 200 in the display area AA, and electrically connected to the two opposite sides of the oxide layer 80 through the passivation layer 200. The first source-

drain electrodes

211 and 212 and the second source-

drain electrodes

213 and 214 are made of a metal material.

The polysilicon layer 30, the gate insulating layer 40, the first gate 53, the dielectric layer 70, the passivation layer 200 and the two first source/

drain electrodes

211 and 212 in the gate driving circuit area GOA form a low temperature polysilicon thin film transistor. The second gate 54, the dielectric layer 70, the oxide layer 80, the passivation layer 200 and the two second source/

drain electrodes

213 and 214 in the display area AA constitute an oxide thin film transistor.

In one embodiment, the array substrate 2000 further includes: a planarization layer 220, a common electrode layer 230, an insulating layer 240 and a pixel electrode layer 250. Referring to fig. 17-19, a planarization layer 220 covers the passivation layer 200, the two first source/

drain electrodes

211 and 212, and the two second source/

drain electrodes

213 and 214. The planarization layer 220 has a third via 221 exposing a portion of the second source/drain 214. The common electrode layer 230 is disposed on the planarization layer 220 in the display area AA. The common electrode layer 230 has a fourth through hole 231 communicating with the third through hole 221 of the planarization layer 220. The insulating layer 240 is disposed on the planarization layer 220 and the common electrode layer 230. The insulating layer 240 is provided with a fifth through hole 241 at a position corresponding to the fourth through hole 231 of the common electrode layer 230 and the third through hole 221 of the planarization layer 220, so that the exposed portion of the second source/drain electrode 244 remains exposed, and the sidewall of the fourth through hole 231 of the common electrode layer 230 and the sidewall of the third through hole 221 of the planarization layer 220 are covered by the insulating layer 240. The pixel electrode layer 250 is disposed on the insulating layer 240 in the display area AA, and covers a sidewall of the fifth via 241 of the insulating layer 240 and the exposed portion of the second source/drain 214. That is, the pixel electrode layer 250 is electrically connected to the second source/drain electrode 94 through the fifth via 241 of the insulating layer 240. The manufacturing method of the array substrate comprises the steps of (1) forming a first grid precursor of an LTPS thin film transistor and a second grid precursor of an oxide thin film transistor by taking a photoresist pattern as a mask in the same photoetching process, (2) carrying out ion heavy doping by taking the photoresist pattern as a mask to form ion heavy doping areas on two opposite sides of a polycrystalline silicon layer, (3) etching the first grid precursor and the second grid precursor by taking the photoresist pattern as a mask to form a first grid and a second grid, (4) removing the photoresist pattern, carrying out ion light doping by taking the first grid as a mask to form ion light doping areas on two opposite sides of the polycrystalline silicon layer, and (5) forming two first source-drain electrodes of the LTPS thin film transistor and two second source-drain electrodes of the oxide thin film transistor in the same photoetching process without influencing the compatibility of the LTPS thin film transistor process and the oxide thin film transistor process, the number of masks used for manufacturing the LTPO array substrate is reduced, and further the production cost is reduced. Therefore, the technical problem of high mask cost of the existing LTPO array substrate is solved.

Although the present invention has been described with reference to the preferred embodiments, it is to be understood that the present invention is not limited to the disclosed embodiments, and that various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present invention.

Claims

1. A manufacturing method of an array substrate is characterized in that: which comprises the following steps:

providing a substrate, wherein the substrate comprises a display area and a gate driving circuit area surrounding the display area;

forming a polysilicon layer on the gate drive circuit region of the substrate;

coating a gate insulating layer on the substrate and the polycrystalline silicon layer;

forming a first metal layer on the gate insulating layer;

forming a photoresist pattern on the first metal layer;

etching the first metal layer using the photoresist pattern as a mask to form a first gate precursor in the gate driving circuit region and a second gate precursor in the display region;

carrying out ion heavy doping by using the photoresist pattern as a mask to form two ion heavy doping areas on two opposite sides of the polycrystalline silicon layer;

etching the first grid precursor and the second grid precursor by using the photoresist pattern as a mask to form a first grid and a second grid;

removing the photoresist pattern; and

and performing ion light doping by using the first grid electrode as a mask, so that two ion light doped regions are formed in regions, which are not covered by the first grid electrode and are not formed with ion heavy doped regions, of the two opposite sides of the polycrystalline silicon layer.

2. The method of manufacturing an array substrate according to claim 1, wherein: it also includes: coating a dielectric layer on the gate insulating layer, the first gate and the second gate;

forming an oxide layer on the dielectric layer in a region corresponding to the second gate;

forming two first through holes penetrating through the dielectric layer and the gate insulating layer, wherein the two first through holes enable the two ion heavily doped regions to be partially exposed; and

and forming two first source-drain electrodes and two second source-drain electrodes on the dielectric layer, wherein the two first source-drain electrodes are electrically connected to the two ion heavily doped regions through the two first through holes respectively, and the two second source-drain electrodes are directly electrically connected to the oxide layer.

3. The method of claim 2, wherein: the gate driving circuit region comprises a polycrystalline silicon layer, a gate insulating layer, a first grid, a dielectric layer and two first source and drain electrodes which are provided with two ion heavily doped regions and two lightly doped regions to form a low-temperature polycrystalline silicon thin film transistor; and the second grid electrode, the dielectric layer, the oxide layer and the two second source and drain electrodes in the display area form an oxide thin film transistor.

4. The method of manufacturing an array substrate according to claim 1, wherein: it also includes: coating a dielectric layer on the gate insulating layer, the first gate and the second gate;

forming a protective layer on the dielectric layer and the oxide layer;

forming two first through holes and two second through holes, wherein the two first through holes are formed in the gate driving circuit region and penetrate through the protective layer, the dielectric layer and the gate insulating layer to expose parts of the two ion heavily doped regions, and the two second through holes are formed in the display region and penetrate through the protective layer to expose two opposite sides of the oxide layer; and

and forming two first source-drain electrodes and two second source-drain electrodes on the protective layer, wherein the two first source-drain electrodes are electrically connected with the two ion heavily doped regions through the two first through holes respectively, and the two second source-drain electrodes are electrically connected with the oxide layer through the two second through holes respectively.

5. The method of claim 4, wherein: the low-temperature polycrystalline silicon thin film transistor is composed of a polycrystalline silicon layer, a gate insulating layer, a first grid electrode, a dielectric layer, a protective layer and two first source and drain electrodes, wherein the polycrystalline silicon layer, the gate insulating layer, the first grid electrode, the dielectric layer, the protective layer and the two first source and drain electrodes are provided with two ion heavily doped regions and two lightly doped regions in the gate driving circuit region, and the oxide thin film transistor is composed of a second grid electrode, the dielectric layer, an oxide layer, the protective layer and two second source.

6. An array substrate, comprising: which comprises the following steps:

the display device comprises a substrate, a first electrode, a second electrode and a third electrode, wherein the substrate comprises a display area and a gate driving circuit area surrounding the display area;

the polycrystalline silicon layer is arranged on the gate driving circuit region of the substrate and comprises two ion heavily doped regions positioned on two opposite sides of the polycrystalline silicon layer and two lightly doped regions which are close to the center of the polycrystalline silicon layer and are respectively adjacent to the two ion heavily doped regions;

a gate insulating layer covering the substrate and the polysilicon layer;

the first grid is arranged on the region of the grid insulating layer corresponding to the part of the polycrystalline silicon layer between the two ion lightly doped regions; and

and the second grid electrode is arranged on the grid insulation layer in the display area.

7. The array substrate of claim 6, wherein: it also includes:

a dielectric layer covering the gate insulating layer, the first gate and the second gate;

an oxide layer disposed on a region of the dielectric layer corresponding to the second gate;

the two first source-drain electrodes are arranged on the dielectric layer of the gate driving circuit region and penetrate through the dielectric layer and the gate insulating layer to be electrically connected with the two ion heavily doped regions; and

and the two second source and drain electrodes are arranged on the dielectric layer in the display area and are electrically connected to the two opposite sides of the oxide layer.

8. The array substrate of claim 7, wherein: the gate driving circuit region comprises a polycrystalline silicon layer, a gate insulating layer, a first grid, a dielectric layer and two first source and drain electrodes which are provided with two ion heavily doped regions and two lightly doped regions to form a low-temperature polycrystalline silicon thin film transistor; and the second grid electrode, the dielectric layer, the oxide layer and the two second source and drain electrodes in the display area form an oxide thin film transistor.

9. The array substrate of claim 6, wherein: it also includes:

a protective layer covering the dielectric layer and the oxide layer;

the two first source-drain electrodes are arranged on the protective layer in the gate driving circuit region and penetrate through the protective layer, the dielectric layer and the gate insulating layer to be electrically connected with the two ion heavily doped regions; and

and the two second source and drain electrodes are arranged on the protective layer in the display area and penetrate through the protective layer to be electrically connected with the two opposite sides of the oxide layer.

10. The array substrate of claim 9, wherein: the gate drive circuit region comprises a low-temperature polycrystalline silicon thin film transistor consisting of a polycrystalline silicon layer, a gate insulating layer, a first grid electrode, a dielectric layer, a protective layer and two first source and drain electrodes, wherein the polycrystalline silicon layer, the gate insulating layer, the first grid electrode, the dielectric layer, the protective layer and the two first source and drain electrodes are provided with two ion heavily doped regions and two lightly doped regions, and the second grid electrode, the dielectric layer, the oxide layer, the protective layer and the two second source and drain electrodes are provided with.